the mechanical properties of ultra-low-dielectric-constant films

4
The mechanical properties of ultra-low-dielectric-constant films Y.H. Wang a, * , M.R. Moitreyee a , R. Kumar a , S.Y. Wu a , J.L. Xie a , P. Yew a , B. Subramanian a , L. Shen b , K.Y. Zeng b a Institute of Microelectronics, 11 Science Park Road, Singapore 117685, Singapore b Institute of Materials Research and Engineering, 3 Research Link, Singapore 117602, Singapore Available online 20 June 2004 Abstract In low-dielectric-constant (low-k) materials, the dielectric constant is reduced through a reduction in electronic polarization or through the introduction of porosity. For ultra-low-k (k value less than 2.4) materials, introduction of porosity is a common method. However, this reduces the mechanical strength of the materials. In this work, two types (carbon-based and silica-based) of spin-on porous ultra-low-k materials are studied. The mechanical properties, including hardness, Young’s modulus, stress, stress hysteresis, and adhesion properties of the films are investigated. Compared with the dense low-k materials, the hardness and Young’s modulus of the ultra-low-k films are low. The residual stress for the ultra-low-k films on bare Si wafer at room temperature is less than 100 MPa. The stress decreases from tensile to compressive with the increasing temperature up to 430 jC, and returns to the initial value as temperature decreasing to room temperature. Scotch tape test, Stud pull test, and chemical mechanical polishing (CMP) check are used for adhesion characterization. No peeling is found between the ultra-low-k materials and the underlying layer SiC after Scotch tape test. D 2004 Elsevier B.V. All rights reserved. Keywords: Porous ultra-low k; Thin film; Adhesion; Mechanical properties 1. Introduction As integrated circuit (IC) dimensions continue to shrink into ultra-large-scale integrated circuit regimes, the propa- gation delay, crosstalk noise, and power dissipation of the interconnect structure become limiting factors for ICs [1,2]. To address these problems, new low-dielectric-constant (low-k) materials are being developed to replace silica [3– 5]. Basically, in low-k materials, the dielectric constant is reduced through a reduction in electronic polarization or through the introduction of porosity. For ultra-low-k materi- als, introduction of porosity is a necessity. However, this reduces the mechanical strength of the materials, which makes the integration process more difficult. In this study, the mechanical properties of two types of ultra-low-k (k value less than 2.4) porous materials, Film A (carbon-based) and Film B (silica-based) porous films, are investigated. The hardness, Young’s modulus, stress, stress hysteresis, and adhesion properties of the films are reported. 2. Experimental details A nano-indentation system (MTS Nano Indenter XP) was used for hardness and Young’s modulus measurements. A three-side pyramid (Berkovich) diamond indenter was employed for the experiment. The indenter approached the surface until contact was detected, followed by a loading session with a strain rate of 0.05 s 1 to a pre-defined maximum depth, the load was held constant for about 10 s, and then the indenter was withdrawn from the sample, but not completely. The indenter was held in contact with the surface at a 10% of the maximum load for 60 s before it is withdrawn from the sample completely. The penetration depth and the corresponding load force were recorded. The data were collected from 10 points on the sample. Depth and force resolutions of the system were 0.1 nm and 0.02 mN, respectively. Before each measurement, a standard sample, bulk Si was used for calibration. The film thickness of Films A and B were about 250 and 540 nm, respectively. Eight- inch Si wafers were used as substrates for film coating. The stress and stress hysteresis measurements were performed by a stress and flatness measurement system (FSM 7800iTC). The system resolution is better than 10 7 0040-6090/$ - see front matter D 2004 Elsevier B.V. All rights reserved. doi:10.1016/j.tsf.2004.05.038 * Corresponding author. Tel.: +65-677-05797; fax: +65-677-31914. E-mail address: [email protected] (Y.H. Wang). www.elsevier.com/locate/tsf Thin Solid Films 462 – 463 (2004) 227 – 230

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Page 1: The mechanical properties of ultra-low-dielectric-constant films

www.elsevier.com/locate/tsf

Thin Solid Films 462–463 (2004) 227–230

The mechanical properties of ultra-low-dielectric-constant films

Y.H. Wanga,*, M.R. Moitreyeea, R. Kumara, S.Y. Wua, J.L. Xiea, P. Yewa,B. Subramaniana, L. Shenb, K.Y. Zengb

a Institute of Microelectronics, 11 Science Park Road, Singapore 117685, Singaporeb Institute of Materials Research and Engineering, 3 Research Link, Singapore 117602, Singapore

Available online 20 June 2004

Abstract

In low-dielectric-constant (low-k) materials, the dielectric constant is reduced through a reduction in electronic polarization or through the

introduction of porosity. For ultra-low-k (k value less than 2.4) materials, introduction of porosity is a common method. However, this

reduces the mechanical strength of the materials. In this work, two types (carbon-based and silica-based) of spin-on porous ultra-low-k

materials are studied. The mechanical properties, including hardness, Young’s modulus, stress, stress hysteresis, and adhesion properties of

the films are investigated. Compared with the dense low-k materials, the hardness and Young’s modulus of the ultra-low-k films are low. The

residual stress for the ultra-low-k films on bare Si wafer at room temperature is less than 100 MPa. The stress decreases from tensile to

compressive with the increasing temperature up to 430 jC, and returns to the initial value as temperature decreasing to room temperature.

Scotch tape test, Stud pull test, and chemical mechanical polishing (CMP) check are used for adhesion characterization. No peeling is found

between the ultra-low-k materials and the underlying layer SiC after Scotch tape test.

D 2004 Elsevier B.V. All rights reserved.

Keywords: Porous ultra-low k; Thin film; Adhesion; Mechanical properties

1. Introduction

As integrated circuit (IC) dimensions continue to shrink

into ultra-large-scale integrated circuit regimes, the propa-

gation delay, crosstalk noise, and power dissipation of the

interconnect structure become limiting factors for ICs [1,2].

To address these problems, new low-dielectric-constant

(low-k) materials are being developed to replace silica [3–

5]. Basically, in low-k materials, the dielectric constant is

reduced through a reduction in electronic polarization or

through the introduction of porosity. For ultra-low-k materi-

als, introduction of porosity is a necessity. However, this

reduces the mechanical strength of the materials, which

makes the integration process more difficult. In this study,

the mechanical properties of two types of ultra-low-k (k

value less than 2.4) porous materials, Film A (carbon-based)

and Film B (silica-based) porous films, are investigated. The

hardness, Young’s modulus, stress, stress hysteresis, and

adhesion properties of the films are reported.

0040-6090/$ - see front matter D 2004 Elsevier B.V. All rights reserved.

doi:10.1016/j.tsf.2004.05.038

* Corresponding author. Tel.: +65-677-05797; fax: +65-677-31914.

E-mail address: [email protected] (Y.H. Wang).

2. Experimental details

A nano-indentation system (MTS Nano Indenter XP) was

used for hardness and Young’s modulus measurements. A

three-side pyramid (Berkovich) diamond indenter was

employed for the experiment. The indenter approached the

surface until contact was detected, followed by a loading

session with a strain rate of 0.05 s� 1 to a pre-defined

maximum depth, the load was held constant for about 10 s,

and then the indenter was withdrawn from the sample, but

not completely. The indenter was held in contact with the

surface at a 10% of the maximum load for 60 s before it is

withdrawn from the sample completely. The penetration

depth and the corresponding load force were recorded. The

data were collected from 10 points on the sample. Depth and

force resolutions of the system were 0.1 nm and 0.02 mN,

respectively. Before each measurement, a standard sample,

bulk Si was used for calibration. The film thickness of Films

A and B were about 250 and 540 nm, respectively. Eight-

inch Si wafers were used as substrates for film coating.

The stress and stress hysteresis measurements were

performed by a stress and flatness measurement system

(FSM 7800iTC). The system resolution is better than 107

Page 2: The mechanical properties of ultra-low-dielectric-constant films

Fig. 1. Load force vs. displacement: (a) Film A and (b) Film B on Si

substrates.

Y.H. Wang et al. / Thin Solid Films 462–463 (2004) 227–230228

MPa. Standard sample was periodically used to calibrate the

system and ensure compliance with instrument specifica-

tions. A bare silicon wafer was used for the first scan as the

reference.

Scotch tape test, Stud pull test, and chemical mechanical

polishing (CMP) check were used for the adhesion test. For

Scotch tape test, ASTM D3359-97 method was used. A

Sebastian Five-A Pull Tester system was used for Stud pull

Fig. 2. Hardness and Young’s modulus vs. displacement: (a) Film A and (b)

Film B on Si substrates.

Fig. 3. Stress vs. temperature: (a) Film A and (b) Film B on Si substrates.

test. For CMP check, Film A or B was capped with 50 nm

SiC and 200 nm un-doped silicate glass (USG). After

removal of 200 nm USG with a normal process condition

(2.0 and 2.8 psi down force pressure), the stack was checked

using optical microscope and scanning electron microscope

(SEM) to see if there was a peeling. SEM investigation was

conducted using a JEOL JSM-6700F system.

The SiC cap layers were prepared by a multi-station

sequential parallel-plate plasma-enhanced chemical vapor

deposition (PECVD) system. The plasma was sustained

with two radio frequency (r.f.) generators at 13.56 MHz

(500 W) and 100 kHz (400 W). The Si (100) substrates (8

in. p-type single crystal wafers) were heated at 400 jCduring the deposition. The working pressure was maintained

at 2.5 torr. The precursors used were liquid tetramethylsilane

(4 MS, Si(CH3)4), CO2 gas. The un-doped silicate glass

Fig. 4. Stacks for Scotch tape test, all passed.

Page 3: The mechanical properties of ultra-low-dielectric-constant films

Fig. 5. Stud pull test structure and result: (a) Film A and (b) Film B.

Y.H. Wang et al. / Thin Solid Films 462–463 (2004) 227–230 229

films were also deposited by the same PECVD system with

a mixture of SiH4, N2, and N2O as source gases. The total

pressure and r.f. (13.56 MHz) power during deposition were

maintained constant at 2.4 torr and 1100 W, respectively.

Fig. 6. SEM cross-sectional images after Stud

3. Results and discussion

The hardness and Young’s modulus are measured by a

nano-indenter system. The penetration depth vs. the

corresponding load force for Films A and B on Si substrates

are shown in Fig. 1. The film thickness for Films A and B

are 250 and 540 nm, respectively. The arrows up and down

in Fig. 1 are loading and unloading curves, respectively. The

data are collected from 10 different points on each sample

(Film A or B), showing a very good repeatable result, as

shown in Fig. 1a–b for Films A and B, respectively.

The hardness and Young’s modulus vs. displacement of

the two samples are shown in Fig. 2. To avoid surface and

substrate effects, the average hardness and Young’s modulus

are calculated using the load–displacement data with pen-

etration depths between one tenth and one fifth of the film

thickness. The average hardness and Young’s modulus of

Film A are 0.16 and 4.17 GPa, respectively. Film B has a

higher hardness about of 0.52 GPa, and the Young’s

modulus is 3.78 GPa, which is close to the result of Film

A. Note that the hardness and Young’s modulus of spin-on

low-k materials (kf 2.7, aromatic hydrocarbon thermoset-

ting polymer, SiLK) are 0.38 and 2.45 GPa [4], respectively,

and the CVD low-k materials (kf 3.0, carbon-doped silicon

oxide) are 2.49 and 14.65 GPa [6], respectively. Thus, the

mechanical strength of porous ultra-low-k materials, Films

A and B, is obviously weak. The high Young’s modulus and

hardness at the film surface maybe due to the difficulty of

determining the point of contact and the inaccuracy of the

indenter tip function at the shallow depth of the indentation

[7]. It is also reported that the spontaneous bond contraction

pull tests: (a) Film A and (b) Film B.

Page 4: The mechanical properties of ultra-low-dielectric-constant films

Fig. 7. CMP adhesion checks: (a) Film A and (b) Film B.

Y.H. Wang et al. / Thin Solid Films 462–463 (2004) 227–230230

and non-pair interaction of a film surface may result in

ultrahigh hardness at the film surface [8].

Fig. 3 shows the stress and stress hysteresis measurement

results of the two films. The residual stress for Films A and B

on bare Si wafer at room temperature is less than 100 MPa.

The stress decreases from tensile to compressive with the

increase of temperature up to 430 jC, and returns to the

initial value as temperature is decreased to room temperature.

As shown in Fig. 3b, a relative sharp stress change is found

for Film B in the temperature range of 220–280 jC, which isdifferent from the gradually stress change of Film A.

Scotch tape test, Stud pull test, and CMP check are used

for the adhesion test. After Scotch tape test, the stacks, Film

A or B on Si, Film A or B on 50 nm SiC/500 nm USG/Si,

and 200 nm USG/50 nm SiC/Film A or B/50 nm SiC/500

nm USG/Si (as shown in Fig. 4) are checked using an

optical microscope. No peeling is found between the Film A

or B and the underlying layer SiC for all stacks.

For Stud pull test, the test structure is Film A or B on 50

nm SiC/500 nm USG/Si, as shown in Fig. 5. A stud is

mounted on the top surface of the test structure with epoxy.

After baking at 120 jC for 1 h, the Stud pull test is

performed. The results are also schematically shown in

Fig. 5. The detached stress for the stacks with Film A is

more than 70 MPa (as shown in Fig. 5a), while for the stacks

with Film B, the detached stress is in the range of 6–23 MPa

(as shown in Fig. 5b). It is noted that the strength of the

epoxy is in the range of 70–90 MPa. Thus, the above results

show a different failure mechanism of Films A and B.

The cross-sectional SEM is used to check the mark after

detachment for identification of the failure position, as

shown in Fig. 6. As shown in Fig. 6a, the images clearly

show that the interfacial adhesion is stronger than the epoxy

strength for Film A, because the detachment is within the

epoxy. But, for Film B, the detached stress is below 25 MPa.

As shown in Fig. 6b, the test result indicates a cohesive

failure of the Film B in the stack.

For CMP check, the test stack, 200 nm USG/50 nm SiC/

Film A or B/50 nm SiC/500 nm USG/Si is shown in Fig. 7.

After removal of 200 nm USG at normal condition with a

down force pressure of 2.0 or 2.8 psi, the stacks are checked

using SEM, optical microscope, and profiler. Initially, for

Film A, it was found that the stack could not pass the normal

CMP process for polishing the top 200 nm USG. Peeling

was found at the interface of Film A and its underlying layer

SiC, which was confirmed by cross-sectional SEM and

profiler. By an optimized bake sequence and CMP condi-

tion, the peeling issue is fixed. No peeling is found between

the Film B and the under-layer SiC after normal CMP

process of 200 nm USG on a stack with Film B. This result

indicates a good adhesion of Film B to the under-layer SiC.

4. Conclusion

The mechanical properties including adhesion, stress,

stress hysteresis, Young’s modulus, and hardness of Film

A (carbon-based) and Film B (silica-based) have been

investigated. No peeling is found between the Film A or

B and the underlying layer SiC after Scotch tape test. The

Stud pull test shows a cohesive failure of the Films B in the

stack of Film B/SiC/USG/Si. It is found that the stack USG

200 nm/SiC/Film A/SiC/USG/Si cannot pass the normal

CMP process (2.0 and 2.8 psi pressure) for polishing the top

200 nm USG. Peeling was found at the interface of Film A

and its underlying layer. By an optimized bake sequence and

CMP condition, this issue was fixed. No peeling was found

between the Film B and the under-layer SiC after normal

CMP process of 200 nm USG. The residual stress for Film

A or B on bare Si wafer at room temperature is less than 100

MPa. The stress decreases from tensile to compressive with

the increasing temperature up to 430 jC, and returns to the

initial value as temperature decreasing to room temperature.

The hardness and Young’s modulus of Film A are 0.16 and

4.17 GPa, respectively. For Film B, it has a higher hardness,

which is 0.52 GPa, the Young’s modulus is 3.78 GPa, a

result close to that of Film A.

Acknowledgements

The authors gratefully acknowledge the supports of ASM

Japan K.K., Cabot Microelectronics, Dow Chemical,

Honeywell (S), and Systems on Silicon Manufacturing.

References

[1] Semiconductor Industry Association (Ed.), The National Technology

Roadmap for Semiconductors-Interconnect, International SEMA-

TECH, Austin, TX, 2001.

[2] M.T. Bohr, Proceedings of International Electron Devices Meeting,

IEEE, Washington, DC, 1995, p. 241.

[3] G. Sugahara, N. Aoi, M. Kubo, K. Arai, K. Sawada, Proceedings of the

Third International Dielectrics for ULSI Multilevel Interconnection

Conference, Santa Clara, CA, USA, February 10–11, 1997, p. 19.

[4] S.J. Martin, J.P. Goldschalx, M.E. Mills, E.O. Shaffer II, P.H.

Townsend, Adv. Mater. 12 (2000) 1769.

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