the european system design show · 2011. 3. 11. · power formats: beyond upf and cpf room –...

Alpes Congrès, Grenoble, FranceMarch 14 - 18, 2011Design, Automation& Test in Europe

EVENT GUIDEevent guide

WWW.DATE-CONFERENCE.COMwww.date-conference.com

The European System Design ShowFrom Systems-on-Chip to Embedded Computing

CONTENTS

Welcome to DATE 11In this exhibition guide you will find listings of exhibitorscontact details and their products being demonstrated onthe exhibition floor. The classified product finder will helpyou locate the right solution within the show; maps andplans of Alpexpo, exhibition hall and additional exhibitionspace will also help you to get around.

DATE Event SecretariatEuropean Conferences3 Coates PlaceEdinburgh EH3 7AA, UK

T: +44 (0)131 225 2892E: [email protected] or E: [email protected] W: www.date-conference.com

At-a-Glance Timetable 4

Conference Highlights 5

Exhibition Theatre Programme 8

DATE 11 Commercial sponsors 12

Media Partners 13

Tool Seminars 14

Venue Plan 15

Exhibition Floorplan 16-17

Exhibitor List 18

Exhibitor Listings 19

Call for Papers 36

contents

Exhibition Opening Times:

Tuesday 15 March1000 - 1830*

(*Evening Reception offered by the City of Grenoble

from 1830 – 1930hrs)

Wednesday 16 March1000 - 1800

Thursday 17 March1000 - 1700

Entrance to the Exhibition is FREE

FREE - ENTRY to KEYNOTE SESSIONS & EXHIBITION THEATRE (see p.8)

& SPECIAL EVENTS!

OPENING PLENARY KEYNOTES –0830-1030, Tuesday 15 March, Auditorium DauphineBiologically-inspired massively-parallel architectures– computing beyond amillion processorsS Furber, ICL Professor of Computer Engineering,School of Computer Science,Manchester U, United KingdomHow technology R&D leadership brings a competitive advantage in the fieldsof multimedia convergence and power applicationsPhilippe Magarshack, Group Vice-President, Technology R&D - General Manager,Central CAD and Design Solutions, STMicroelectronics, France

LUNCH AND LEARN SESSION SPONSORED BYMENTOR GRAPHICS 1300-1400, Tuesday 15 March, Auditorium DauphineGrenoble EDA Ecosystem - From Research to Market

SPECIAL DAY KEYNOTE - WIRELESSINNOVATIONS FOR SMARTPHONES 1400-1430, Wednesday 16 March, Room OisansHannu Kauppinen, Director, Head of Radio Systems Laboratory, Nokia Research Center, Finland

SPECIAL DAY KEYNOTE - SMART ENERGY AT ST1330-1400, Thursday 17 March, Room OisansCarmelo Papa, Executive VP Industrial and Multisegment, STMicroelectronics, Italy

DATE 11 EVENT GUIDE 3

Room – Oisans Room – Meije Room – Belle-Etoile Room – Stendhal Room – Chartreuse Room – Bayard Room – Les Bans Exhibition Theatre

REGISTRATION & SPEAKERS’ BREAKFAST0730

0830 1.1 PLENARY: OPENING, KEYNOTE ADDRESSES AND AWARDS PRESENTATION, Auditorium Dauphine

3.1 EXECUTIVE SESSION – 22nmChallenges andWealth/Knowledge CreationOpportunities

3.2 Power Optimisation ofMulti-Core Architectures

3.3 Core Algorithms for FormalVerification Engines

3.4 Predicting Bugs andGenerating Tests forValidation

3.5 Timing Related Issues inTest

3.6 Performance and TimingAnalysis

3.7 Implementations forDigital BasebandProcessing

3.8 PANEL SESSION –Power Formats: BeyondUPF and CPF


4.1 EXECUTIVE SESSION –System Level Complexityand Innovation

4.2 Robust and Low PowerSystems

4.3 Formal VerificationTechniques andApplications

4.4 System Level Simulationand Validation

4.5 Advances in Analogue,Mixed Signal and RF Testing

4.6 Design AutomationMethodologies andArchitectures for Three-Dimensional ICs

4.7 Resource Management forQoS Guaranteed NoCs

SEE WEB OR EVENT GUIDEFOR LATEST EXHIBITIONPROGRAMME


2.1 EXECUTIVE SESSION – Ideason Future of EDA and IPIndustry

2.2 System-Level Techniques toHandle Performance,Reliability and ThermalIssues

2.3 Modelling and Simulation ofInterconnects

2.4 PANEL AND EMBEDDEDTUTORIAL SESSION – LogicSynthesis and Place and Route:After 20 Years of Engagement,Wedding in View

2.5 Transient Faults and SoftErrors

2.6 Networked EmbeddedSystems

2.7 Design of Energy-Efficientand Automotive Systems

2.8 EMBEDDED TUTORIAL– Addressing Critical PowerManagement VerificationIssues in Low PowerDesigns

1030-1130 Exhibition Break, 1300-1430 Lunch, 1600-1700 Exhibition Break (1600-1630 IP1)BREAKS

1130to1300

1430to1600

1700to 1830

SPECIAL TRACK EMERGING TECHNOLOGIES APPLICATIONS DESIGN TECHNOLOGY TEST EMBEDDED SOFTWARE SYSTEM DESIGN SPECIAL SESSIONS

1830 Evening Reception Offered by the City of Grenoble

1400 3.0 SPECIAL LUNCH-TIME SESSION 1300-1400 Grenoble EDA Ecosystem Session - From Research to Market sponsored by Mentor Graphics, Auditorium Dauphine

• TUESDAY • TUESDAY • TUESDAY • TUESDAY •tuesday 15 march

• WEDNESDAY • WEDNESDAY • WEDNESDAY •wednesday 16 march



REGISTRATION & SPEAKERS’ BREAKFAST0730

0830to1000

1100to1230

6.1.1 SMART DEVICES HOTTOPIC/EMBEDDED TUTORIAL– Ultra Low Power SmartDevices

6.2 Placement andFloorplanning

6.3 Power Modelling, Analysisand Optimisation

6.4 Design and Test of FaultResilient NoC Architectures

6.5 New Techniques forDiagnosis and Debug

6.6 Embedded Software forParallel Architectures

6.7 HOT TOPIC – VirtualManycore Platforms:Moving Towards 100+Processor Cores

6.8PANEL SESSION –Embedded Software Debugand Test


1430to1600

7.1 SMART DEVICES HOT TOPIC– Smart Medical Implants

7.2 Emerging MemoryTechnologies

7.3 Architectural Optimisationfor Low Power Systems

7.4 Advanced Technologies forNoC Implementation

7.5 Emerging Test Solutions forAdvanced Technologies, RFand MEMS Devices

7.6 Innovative Power-AwareSystems for a Green andHealthy Society

7.7 HOT TOPIC – Foundations ofComponent-Based Designfor Embedded Systems

7.8EMBEDDED TUTORIAL –Predictable SystemIntegration



5.1 SMART DEVICES EMBEDDEDTUTORIAL –Smart Devicesfor the Cloud Era

5.2 An Encyclopedia of Routing

5.3 Temperature and VariationAware Design in Low PowerSystems

5.4 Advanced NoC Tooling andArchitectures

5.5 INDUSTRIAL 1

5.6 Analysis, Compilation andRuntime Techniques

5.7 EMBEDDED TUTORIAL –Architectures for OnlineError Detection andRecovery in MulticoreProcessors

EXHIBITIONOPENS AT 1000

1340 6.1.2 SPECIAL DAY KEYNOTE AND AWARDS 1340-1400 Awards and 1400-1430 Keynote, Room – Oisans

1700to1830

8.1 SMART DEVICES PANELSESSION – Integrating theReal World Interfaces

8.2 System-Level DesignTechniques for AutomotiveSystems

8.3 Power/Error Tradeoffs

8.4 Memory SystemArchitectures

8.5 Testing and DesigningSRAM Memories

8.6 Cryptanalysis, Attacks andCountermeasures

8.7HOT TOPIC – Flows,Application and Future ofComponent-based Designfor Embedded Systems

8.8 EMBEDDED TUTORIAL –Communication Networksin Next GenerationAutomobiles


1000-1100 Exhibition Break, (1000-1030 IP2), 1230-1340 Lunch, 1600-1700 Exhibition Break (1600-1630 IP3)BREAKS

• THURSDAY • THURSDAY • THURSDAY • thursday 17 march


REGISTRATION & SPEAKERS’ BREAKFAST

10.1.1 INTELLIGENTENERGY MANAGEMENT –Smart Energy Generation:Design Automation and theSmart-Grid

10.2 Advanced Algorithms andApplications forReconfigurable Computing

10.3 System Optimisations andAdaptivity

10.4 Design and Simulation ofMixed-Signal Systems

10.5 Advances in TestGeneration and FaultSimulation

10.6 Model Based Verificationand Synthesis of EmbeddedSystems

10.7 EMBEDDED TUTORIAL – DieStacking Goes Mobile andEmbedded

10.8 PANEL SESSION –State ofthe Art VerificationMethodologies in 2015


11.1 INTELLIGENT ENERGYMANAGEMENT – SmartEnergy Utilisation: FromCircuits to ConsumerProducts

11.2 Architectural Innovationsfor ReconfigurableComputing

11.3 Asynchronous Circuits andAdvanced Timing Issues inLogic Synthesis

11.4 High Level Synthesis

11.5 New Directions in Testing

11.6 Hardware Design forMultimedia Applications

11.7 HOT TOPIC – New Frontiersin Embedded SystemsDesign: Technology andApplications

11.8 HOT TOPIC – StochasticCircuit Reliability Analysisin Nanometer CMOS



10.1.2 SPECIAL DAY KEYNOTE, 1330-1400 Keynote, Room – Oisans

12.1 INTELLIGENT ENERGYMANAGEMENT PANELSESSION – The Role of theEDA Community

12.2 Design and Run-TimeSupport for DynamicReconfigurability

12.3 Reliability and ErrorTolerance in LogicSynthesis

12.4 Reliability and ErrorTolerance in LogicSynthesis

12.5 Error Correction andResilience

12.6 Security Modules fromLayout to Network-on-Chip

12.7 HOT TOPIC – Sustainabilitythrough MassivelyIntegrated Computing...

12.8 HOT TOPIC – SynthesisSupported Increase ofEfficiency in AnalogueDesign


1000-1100 Exhibition Break, (1000-1030 IP4), 1230-1330 Lunch, 1530-1600 Break (1530-1600 IP5)BREAKS

1600to1730

1400to1530

1100to1230

0830to1000

0730

1330

9.1 INTELLIGENT ENERGYMANAGEMENT TUTORIAL –Energy Transfer, Generationand Power Electronics

9.2 Design AutomationMethodologies for EmergingTechnologies

9.3 System Modelling

9.4 Modelling and Verificationof Analogue and RF Circuits

9.5 INDUSTRIAL 2

9.6 Embedded System ResourceAllocation and Management

9.7 EMBEDDED TUTORIAL –Sub-Wave LengthLithography and VariabilityAware Test andCharacterisation Methods

EXHIBITIONOPENS AT 1000


Biologically-inspired massively-parallelarchitectures – computing beyond a millionprocessorsS Furber, ICL Professor of Computer Engineering, School of Computer Science,Manchester U, UKMoore's Law continues to deliver ever-more transistors on an integrated circuit, butdiscontinuities in the progress of technology mean that the future isn't simply an extrapolation of the past. For example,design cost and complexity constraints have recently caused the microprocessor industry to switch to multi-corearchitectures, even though these parallel machines present programming challenges that are far from solved. Moore's Lawnow translates into ever-more processors on a multi-, and soon many-core chip. The software challenge is compounded bythe need for increasing fault-tolerance as near-atomic-scale variability and robustness problems bite harder.

We look beyond this transitional phase to a future where the availability of processor resource is effectively unlimited andcomputations must be optimised for energy usage rather than load balancing, and we look to biology for examples of howsuch systems might work. Conventional concerns such as synchronisation and determinism are abandoned in favour of real-time operation and adapting around component failure with minimal loss of system efficacy.

PLENARY SESSIONplenary session

KEYNOTE ADDRESSfirst keynote address

How technology R&D leadership brings acompetitive advantage in the fields ofmultimedia convergence and power applicationsPhilippe Magarshack, Group Vice-President, Technology R&D - General Manager,Central CAD and Design Solutions, STMicroelectronics, FranceFrom 1985 to 1989, Magarshack designed microprocessors arithmetic blocks at AT&T Bell Labs inNew Jersey, Pennsylvania and California. In 1989, he joined Thomson-CSF in Grenoble, France, as libraries and ASIC Manager.In 1994, Magarshack joined the Central R&D of SGS-THOMSON Microelectronics (now STMicroelectronics), where he heldseveral Program Management roles in advanced CMOS Design Platforms. Since 2005, Magarshack heads ST’s Central Library,IP and CAD organisation, which defines and provides design solutions to all ST Product Groups in CMOS, embedded NVM andBCD processes, ranging from 0.35um to

20nm technologies.

In his current role, Magarshack oversees ST’s EDA vendor strategy, setting up and managing joint R&D programs to addressST’s future design needs. Magarshack is ST’s Enablement Executive at the IBM ISDA CMOS Bulk Alliance in 32/28nm and22/20nm.

Philippe Magarshack was born in London, UK, and graduated with an engineering degree in Physics from EcolePolytechnique in Palaiseau, France in 1983 and with an Electronics Engineering degree from Ecole Nationale Supérieure desTélécommunications in Paris, France in 1985.

KEYNOTE ADDRESSsecond keynote address

Tuesday, March 15, 2011, 0830 – 1030 • Opening Address – Awards – Keynote Speakers

TUESDAY tuesday 15 march

0930to1800

Low Power SOC Design: Best Practice– and what’s next?

Electronic System Level Design andVerification

Manufacturing, CAD and Thermal-Aware Design for 3D System-on-ChipDesign

A (Room - Belle-Etoile) B (Room – Chartreuse) C (Room – Les Bans)

0930to1300

MPSoC Hardware/SoftwareArchitectural and DesignChallenges/Solutions

On-chip interconnect for newgeneration of SoC

Renewable energy: solar powergeneration, conversion and delivery

Power-Aware Testing and TestStrategies for Low Power Devices

D1 (Room – Meije 3) E1 (Room – 7 Laux 4) F1 (Room – 7 Laux 5) G1 (Room – Room Meije 2)

1430to1800

Model-based MPSoC ArchitectureSynthesis for Highly-demandingEmbedded Applications

Design and Verification Challengesfor Automotive Electronics

Overcoming CMOS ReliabilityChallenges: From Devices to Circuitsand Systems

Testing TSV-Based 3D Stacked Ics

D2 (Room – Meije 3) E2 (Room – 7 Laux 4) F2 (Room – 7 Laux 5) G2 (Room – Meije 2)

TUTORIAL REGISTRATION AND WELCOME REFRESHMENTS0730

1800 Welcome Reception

1100-1130 Morning, 1300-1430 Lunch, 1600-1630 Afternoon.BREAKS

• MONDAY TUTORIALS • MONDAYmonday 14 march

WIRELESS NETWORK for LAPTOP USERSAccess will be FREE throughout the exhibition area for all attendees

LUNCH AND LEARNSESSION SPONSORED BYMENTOR GRAPHICS -

Grenoble EDA Ecosystem - From Research to Market –Time: 1300 - 1400Location / Auditorium Dauphine

Moderator: Mark Croft, Mentor Graphics, UK

Three views of the value of European Research to EDAand Semiconductors: CEA-LETI, ST and MentorGraphics speak of the value of close cooperation inthe EU.

1300 FROM RESEARCH TO MARKETLaurent Malier, CEO, CEA-LETI, FR

With its research centers, university campus, 500foreign companies and 40,000 scientists, engineersand technicians employed in the area, the Grenoble-Isere region, otherwise known as France's SiliconValley, mixes world-class intellectual and scientificdynamism with exceptional quality of life. It is theideal sprinboard for Academia-Industry collaboration.This presentation details collaboration schemesbetween Industry and research institutes and industryhappening in Grenoble. This often involves long-termprojects based on sharing research costs and requiresjoint technical programs with a predeterminabletimetable, with specific technology transfer andoperating conditions.

1320 SUCCESSFUL R&DCOLLABORATIONS AS ACOMPETITIVE ADVANTAGE

Philippe Magarshack, Group Vice-President, TechnologyR&D - General Manager, Central CAD and Design Solutions,STMicroelectronics, FRSTs Grenoble center was born as a spin-off from aGrenoble research lab several decades ago. Since thenwe have continued to maintain our innovationleadership with long-term Public-Private Partnershipsin Grenoble, France and Europe. Starting in 1992, SThas partnered with its competitors to build its 200mmand 300 mm R&D centers and fabs in Crolles, nearGrenoble. In 2008, ST joined ISDA alliance in FishkillNY to collaborate to its 32/28nm and 20nm CMOSprocesses. More recently, ST has reinforced andenlarged the scope of its local R&D partnership toDesign and Design Automation. This complete eco-system is now bringing valuable innovation to ourproducts and our customers.

1340 INVESTING IN THE TOP TALENTFOR EDA

Eric Selosse, Vice President andGeneral Manager, EmulationDivision, Mentor Graphics, FRMentor Graphics has a long track record of investingin Europe for R&D expertise. Over the last year,despite the economic conditions, we have continuedto recruit in France, the UK and Poland. Our industryis a meritocracy which relies on the hiring, nurturingand retention of the best world-class engineersavailable in electronics and associated fields. Thispresentation will outline why we invest in Europe,why France is such a significant part of this and lookat the particular place Grenoble has in this story.

Room – Oisans 0830-1000Organisers/Moderators:A Jerraya, CEA-LETI MINATEC, FRJ Goodacre, ARM, UKCloud computing will provide unlimited computing powerand mobile terminals will take benefit of these new flexiblecomputing platforms. This session presents the context offuture mobile terminals, the key evolutions that will enableaccess to cloud computing and the new functions that willrequire cloud computing.

Room – Oisans - 1340-1400 Awards and 1400-1430 Keynote

Awards Moderator:Z Peng, Linkoping U, SE

Awards: Presentation of the DATE 10 Best Paper Awards:

TRACK D - PROPERTIES OF AND IMPROVEMENTS TO TIME-DOMAIN DYNAMIC THERMAL ANALYSIS ALGORITHMSX Chen and R P Dick, U of Michigan, USL Shang, U of Colorado at Boulder, US

TRACK E - SKEWED PIPELINING FOR PARALLEL SIMULINKSIMULATIONSA Canedo, T Yoshizawa and H Komatsu, IBM Research, JP

BEST IP - TOWARDS A CHIP LEVEL RELIABILITY SIMULATORFOR COPPER/LOW-K BACKEND PROCESSESM Bashir and L Milor, Georgia Institute of Technology, US

Presentation of the EDAA Outstanding DissertationAwards

Organiser/Moderator: A Jerraya, CEA-LETI MINATEC, FR

Keynote Speaker:Hannu Kauppinen, Director, Head of Radio SystemsLaboratory, Nokia Research Center, FI

WIRELESS INNOVATIONS FOR SMARTPHONES

Abstract: The ever increasing demand for fast mobileinternet connectivity continues to set challenges forresearch in radio communications. On one hand thecapacity demand can be served by offloading data trafficto local networks. On the other hand using morebandwidth, and possibly dynamically allocating spectrumin a flexible way, will improve the usage of the availablespectrum. The future of wireless access continues to bedefined by the 3GPP and IEEE standards setting bodies.Radios can also provide innovative features that offer newfunctionalities for consumers, such as ultra fast localconnectivity, sensing and positioning.

1340

1400

5.1 EMBEDDED TUTORIAL – SmartDevices for the Cloud Era

6.1.2 LUNCH-TIME KEYNOTE AND AWARDS

Room – Oisans 1100-1230Organisers/Moderators:J Goodacre, ARM, UKA Jerraya, CEA-LETI MINATEC, FRLow power is considered the key enabling technology forfuture smart systems. For most applications stringentrequirements on power consumption has to be satisfied.This session presents power issues in different applicationdomains and how specific requirements are addressed. Thisis illustrated with hardware/software design techniques forconcrete products.

6.1.1HOT TOPIC/EMBEDDEDTUTORIAL – Ultra Low PowerSmart Devices

Room – Oisans 1430-1600Organisers:A Jerraya, CEA-LETI MINATEC, FRJ Goodacre, ARM, UK

Moderator: S Yoo, POSTECH, KR

Medical implants integrate a large number of heterogeneouscomponents (computing, sensors, actuators, antenna, RF)to implement sophisticated functions. Unlike classicdevices, the design of medical implants includes thebuilding of application specific architecture and specificinterfaces and other kinds of packaging required toefficiently interface with human body. This sessionintroduces the key technologies for the design of suchcomplex devices.

7.1 HOT TOPIC – Smart MedicalImplants

Room – Oisans 1700-1830

Organisers/Moderators:A Jerraya, CEA-LETI MINATEC, FRJ Goodacre, ARM, UK

Panellists:P Urard, STMicroelectronics, FRJ Rabaey, UC Berkeley, USR Bramley, STEricsson, FRA King-Smith, IMGTEC, UKW Burleson, Massachusetts U, USF Perruchot, CEA-LETI, FR

Smart systems require interfacing more of the world in anintegrated solution (Camera, gyroscope, compass, temp,direction…). This is imposed by social evolution and enabledby new integration technologies. So far, many productsfeaturing a variety of hardware and software have beendeveloped and many more seems to be coming in a fastgrowing market. The panel will present the most promisingproducts and solutions and discuss the innovations enablingfuture smart systems.

8.1 PANEL SESSION – Integratingthe Real World Interfaces

• WEDNESDAY • WEDNESDAY • WEDNESDAY •wednesday 16 march

• THURSDAY • THURSDAY • thursday 17 march

Smart Devices of theFuture Special Day

Intelligent Energy Management - Supply andUtilisation Special Day


Organisers:P Mitcheson, Imperial College, UKP K Wright, UC Berkeley, US

Moderator:P Mitcheson, Imperial College, UK

Issues relating to energy resources are set to play anincreasing role in all of our futures. This special day atDATE is intended to further involve the EDA community inenergy related matters at all scales. This session coverssetting the scene for the day on energy, covering topicsfrom levels of micro Watts to Giga Watts.

9.1 Energy Transfer, Generationand Power Electronics



Moderator:P K Wright, UC Berkeley, US

This session will look at issues relating to the supply sideof the electrical grid, including smart grids and the role ofelectric vehicles in future supply infrastructure andincludes talks from both industry and academia.

10.1.1Smart Energy Generation:Design Automation and theSmart-Grid



Moderator:P Mitcheson, Imperial College, UK

This session concentrates on smart use of energy at thedemand side - from energy issues at the circuit level tolarger scale issues with consumer products and use ofenergy in the home.

11.1Smart Energy Utilisation:From Circuits to ConsumerProducts


Organisers/Moderators:P K Wright, UC Berkeley, USP Mitcheson, Imperial College, UK

Panellists:L Bomhold, Synopsys, UST Green, Imperial College, UKA Ephrimides, Maryland U, USC Blumstein, California Institute for Energy andEnvironment, USS Henry, RTE, FR

Until recently the electrical power industry has reliedsolely on traditional technologies - copper and iron ascables, transformers and machines as the mainstreamsolution for the generation, transmission and distributionof power. Whilst use of these materials and technologiesis here to stay, improvements in power semiconductortechnology mean that the industry is moving into aposition where more and faster control of power systemscan be achieved. This high level control requires a sensingand communication infrastructure to be put in place acrossthe network. At the same time, the use of electricity inthe home, through the potential of real time consumerpricing requires new technologies.

This panel session aims to pull together heavy currentelectrical power engineers and light current electronicengineers to form a discussion and debate about thefuture role of EDA in applications which are being broughtabout by changes in the functioning of the power industry.Power engineers from both industry and academia willstimulate the discussion with requirements both from asystem perspective and consumer perspective. Therepresentatives from the EDA side will respond with whatcontributions they believe EDA can make, what alreadyexists or is a simple development problem and whatresearch issues remain in achieving these goals. Insummary, this panel aims to provide motivation for theEDA industry to work on useful technology that can beapplied to heavy power systems with a view to improvingglobal energy efficiency.

12.1The Role of the EDACommunity in the Future ofWorld Energy Supply andConservation?


• THURSDAY •thursday 17 march • FRIDAY • FRIDAY • FRIDAY •friday 18 march

Friday Workshops



Organiser:P K Wright, UC Berkeley, US

Keynote Speaker: Carmelo Papa, Executive VP Industrial and Multisegment,STMicroelectronics, IT

SMART ENERGY AT ST

The exponential increase of world energy demand, with aforecasted raise of 45%[1] between 2010 and 2030, makesenergy management one of the most urgent topics of thecentury and a key driver for semiconductors andelectronics products evolution. The main solutions forworld energy demand and global warming issues have beenindividuated in two main streams: an increasing offer fromalternative energy sources and their integration into thenew Smart Grid and a reduction of the demand through anincrease of systems efficiency.

In energy supply and distribution, the Smart Grid is in factimpacting for an estimated 14% of CO2[2] emissionsreduction in the global energy system by 2020. In additionit makes it possible to generate high cost savings forindustrial and economic system (188 Billion$ per yearestimated only for U.S.[2])

New measures for Energy Efficiency will contribute up to 8Giga-Tons of CO2 reduction (54% of total with theapplication of policy 450[1]) by 2020, mostly thanks topower electronics applications.

Along these two areas of intervention, ST is investing to provideboth effective power semiconductor technologies and ICs fornew topologies for power conversion, but not only. Newmaterials (SiC) for power transistors, innovative solutions forpower management and digital control, wired and wireless ICsare some examples of ST offer that apply to energy relatedapplications like PV converters, Smart Metering, Connectivity,Building Automation, Electrical Traction and Motor Control.

Along the energy theme, though at different orders ofmagnitude, innovation for portable systems is tackled at STR&D: extremely low consuming CMOS technology for digital ICs,low power RF transceivers, milliWatt capable super thin batteriesand 3D integration techniques are the base for miniaturised,long lasting battery based systems, that enable new scenariosespecially in portable Healthcare and Wireless AutonomousSensors Networks.

[1] Source: International Energy Agency

[2] Source: The Climate Group

[3] Source: Grid 2030 A National Vision for Electricity s Second 100 Years, United

States Department of Energy, Office of Electric Transmission and Distribution

10.1.2 SPECIAL DAY KEYNOTE

0830TO1700

Room – Les Bans Room – Meije Room – Bayard Room – Berlioz

WORKSHOP REGISTRATION & WELCOME REFRESHMENTS0730

W1 Workshop on Micro PowerManagement for Macro Systems onChip (uPM2SoC)

W2 Design Methods and Tools forFPGA-Based Acceleration ofScientific Computing

W3 Third Friday Workshop onDesigning for Embedded ParallelComputing Platforms: Architectures,Design Tools, and Applications

W4 Bringing Theory to Practice:Predictability and Performance inEmbedded Systems

0830TO1700

Room – Stendhal Room – 7 Laux 4 Room – Belle-Etoile Room – Chartreuse

Please see individual workshop programmes for lunch and break timesBREAKS

W5 3D Integration – Applications,Technology, Architecture, Design,Automation, and Test

W6 M-BED'2011, the 2nd Workshopon Model Based Engineering forEmbedded Systems Design

W7 Hardware Dependent SoftwareSolutions for SoC Design

W8 1st International QEMU UsersForum (QUF)

DATE 11 OPENING PLENARY

Auditorium Dauphine

Biologically-inspired massively-parallel architectures – computingbeyond a million processors

S Furber, ICL Professor of Computer Engineering,

School of Computer Science, Manchester U, UK

How technology R&D leadership brings a competitive advantage in thefields of multimedia convergence and power applications

P Magarshack, Group Vice-President, Technology R&D - General Manager, Central CAD

and Design Solutions, STMicroelectronics, FR

See you at DATE 12, 12-16 March 2012, ICC, Dresden, Germany


• EXHIBITION THEATRE • EXHIBITION THEATRE •exhibition theatre

1045 - 1115Organiser/Moderator:Juergen Haase, edacentrum, GermanySpeaker: Andreas Bruening, Silicon Saxony, GermanyAbstract: Each morning Juergen Haase (edacentrum,Germany) will open DATE11 Exhibition with an overviewabout the highlights of the Exhibition program and providebrand-new information on “What’s hot today” to allattendees .Andreas Brüning, in the Silicon Saxony Cluster (Germany)responsible for the work of the micro/nanoelectronicdevision, will invite all attendees to establish closecollaboration between clusters like Grenoble and Dresdenin his talk:Clustering: an Enabler for Micro and NanoelectronicsA short overview about Silicon Saxony will be followed bydescribing micro and nanoelectronics as an opportunity forEurope as well as clustering as an enabler for micro andnanoelectronics based on the example Grenoble andDresden. Presentation of Dresden & Genoble cluster as acooperation for Europe and the expectation to strengthenexchange in Design Automation experience.

1130 - 1300Organiser: B Kapoor, Mimasic, USModerator: K Just, Infineon, DEAbstract: Power management techniques that leveragevoltage as a handle are being extensively used in powersensitive designs. These techniques include power gating,power gating with retention, multiple supply voltages,dynamic voltage scaling, adaptive voltage scaling, multi-threshold CMOS, and active body bias. The use of thepower management techniques also imply new challengesin validation and testing of designs as new power statesare created. We look into verification issues along withthe solutions to these issues using a verification strategythat involves power-aware simulation, rule-basedstructural checking, formal tools, and methodologyrecommendations. We detail our varied experiences withvarious design teams in addressing these low powerverification issues for applications such as the wirelesshandset, low power microprocessors, and GPS.

1430 - 1600Organiser/ Moderator: B Pangrle, Mentor Graphics, USPanellists:J Biggs, ARM, UKC Clavel, ST-Ericsson, FRO Domerego, Texas Instruments, FRK Just, Infineon/Intel, DEB Moison, STMicroelectronics, FRAbstract: Two formats for specifying power intent arecurrently in wide use in industry today and as designerscontinue to strive for more power efficient designs newissues arise that certainly need new solutions to improveon today’s standards. This panel will discuss areas forimproving today’s power formats and the direction thatthese formats need to move in order to provide the mostefficient flows for design and verification and especiallywith regards to low-power. The scope of the formats andtheir suitability from early ESL design exploration to back-end sign-off checking will also be discussed along with anyissues that need to be addressed in order to make designand verification engineers more productive.

1615 - 1715Organiser:MagillemModerator:Mladen Berekovic, University of Jena, GermanySpeakers/Panellists:Cyril Spasevski, Magillem, CTO, FranceMichael McNamara, Cadence, VP and GM and SystemSoftware Group, USAJohn Goodenough, ARM, VP Design Technology and Automation, UKAntoine Perrin, ST, CAD Manager, FranceAbstract: The domains of RTL design, virtual platforms,high level synthesis, and IP assembly automation areconverging to enhance the productivity and reliability ofsystem level design methodology. A significant number ofcompanies are creating RTL IP catalogs and leveragingassembly automation to rapidly produce incrementallyinnovative SoCs. Virtual platforms are enabling a growingpractice pre-RTL software development. High levelsynthesis is increasing the productivity to create new RTLIP. The confluence of these forces is creating a plethora ofopportunities, and presenting several challenges. Thispanel will explore and debate the priorities and benefits ofthese emerging trends and discuss the followingquestions:

* How far along are customers in creating internalvirtual platform IP catalogs?

* What are the challenges of organizing virtualplatform and RTL IP catalogs?

* How do IP-XACT and assembly tools help with thisinternal management problem

* Are companies starting to organize 3rd party IPsuppliers to provide virtual platform and RTL IP, aswell as IP-XACT

* What are the challenges in defining IP catalogrequirements to 3rd parties?

* Are standards needed in addition to IP-XACT toenable freer IP creation and exchange?

1730 - 1750

Organiser:Satin Technologies, STMicroelectronics

Speaker:Indavong Vongsavady, ST CCDS

Abstract: The Central CAD and Design Solutions (CCDS)group at STMicroelectronics is in charge of developing anddeploying design libraries, kits, flows and methodologiesthroughout the different groups at ST and ST-Ericsson.They also offer internal design services for very complexchips.

In order to make design quality monitoring more timelyand accurate, ST CCDS has adopted VIP Lane to helpturning their design checklists into fully automateddashboards. These dashboards are becoming thefoundation for on-the-fly, fact-based communicationbetween all stakeholders of the same design project.

This presentation will show the benefits of this approach(sharing of more formal design practices, accuratecommunication between design teams, shorter designcycle) and illustrate these benefits with real life examples.

1750 - 1810

Organiser:Edxact, ST-Ericsson

Speaker:Jérôme Lescot, ST-Ericsson, France

Abstract: Impact of metal routing on 'rdson' parameter ofpower-MOS devices is increasing with more advancedprocess nodes (65n, 40n). Capacity of comanche tool toquickly extract thousands of pin to pin resistances enablesus to achieve layout optimization by analysing resistancesdistribution from pads to any individual transistor. Inaddition, jivaro reduction makes possible the spicesimulation of the structure including both parasiticresistors and functional devices to extract rdson parameter.

• TUESDAY •tuesday 15 march

ET01 Highlights of DATE11 Exhibition/Clustering – an Enabler for Micro andNanoelectronics

2.8 EMBEDDED TUTORIAL –Addressing Critical PowerManagement Verification Issues inLow Power Designs

3.8 PANEL SESSION – Power Formats:Beyond UPF and CPF

ET02 What is missing to enableglobal IP collection, assembly, andvirtual platform distribution?

ET03 STMicroelectronics automatesquality monitoring for improveddesign productivity

ET04 Optimization of Power-MOSStructures dedicated to EnergyManagement ICs

Exhibition Theatre Overview

Tuesday 15th March

1045 - 1115 ET01 Day 1 Opening Session: Highlights of Date11 Exhibition / Clustering – An Enabler for Micro and Nanoelectronics

1130 - 1300 2.8 Embedded Tutorial: Addressing Critical Power Management Verification Issues in Low Power Designs

1430 - 1600 3.8 Panel: Power Formats: Beyond UPF and CPF

1615 - 1715 ET02 Panel: What is Missing to Enable Global IP Collection, Assembly, and Virtual Platform Distribution?

1730 - 1830 ET03 Testimonial: STMicroelectronics Automates Quality Monitoring for Improved Design Productivity

ET04 Testimonial: Optimization of Power-Mos Structures Dedicated to Energy Management ICS

ET05 Testimonial: How Software Development Can Take Benefit of a Platform Power Model

Wednesday 16th March

1000 - 1030 ET06 Day 2 Opening Session: Highlights of Date11 Exhibition / More Than Moore Solutions for Automotive Products

1030 - 1050 ET07 Testimonial: Ball Grid Array Packages Electrical Optimization Using Apache Package Modeling Tools

1100 - 1230 6.8 Panel: Embedded Software Debug and Test

1315 - 1415 ET08 Panel: Process Variability: Challenges and Solutions

1430 - 1600 7.8 Embedded Tutorial: Predictable System Integration

1700 - 1830 8.8 Embedded Tutorial: Communication Networks in Next Generation Automobiles

Thursday 17th March

1000 - 1010 ET09 Day 3 Opening Session: Highlights of Date11 Exhibition / Testimonials

1010 - 1030 ET10 Testimonial: System Level Power Integrity Analysis and Supply Network Optimization of a Dual Core CPU

1030 - 1050 ET11 Testimonial: Co-Verification of an Interrupt Driven Firmware Subsystem using Cadence ISX and Coverage Driven Techniques

1100 - 1230 10.8 Panel: State of the Art Verification Methodologies in 2015

1245 - 1345 ET12 Panel: Early Timing and Power Information of Complex SoC Designs using Augmented Virtual Platforms

1400 - 1530 11.8 Hot Topic: Stochastic Circuit Reliability Analysis in Nanometer CMOS

1700 - 1830 12.8 Hot Topic: Synthesis Supported Increase of the Analog Design Efficiency

1810 - 1830Organiser:DOCEA Power, ST-EricssonSpeaker:Patrick Arnould, Senior System Architect, ST-Ericsson, FranceAbstract: The increasing complexity of applicationsrunning on multimedia mobile platforms is becoming moreand more critical for battery life, so software optimizationto take into account power consumption is crucial butcould become very painful without a dedicatedenvironment. A lot of power saving is possible at thesoftware level but the investigations are complex due tothe number of parameters involved in this optimization:clock gating, dynamic power switching, dynamic voltageand frequency scaling, traffic, CPU and IP load.In this testimonial, a validation environment will be usedas an example to show the benefit for software developersto have access to a combination of CPU load, traffic andpower figures phase per phase and power supply per powersupply. It also outlines the challenges for a powermodeling methodology to be able to target a wide range ofapplications, very low power and power hungry systemsoptimization. Taking the benefit of having a platformpower model and before starting any softwaredevelopment, key decisions can be taken to focus veryquickly on the best software option to gain power.The testimonial scope goes from power model constructionto fast software optimization on a real application showingthe benefit to speed up software development andplatform power optimization.

1000 - 1030Organiser/Moderator:Juergen Haase, edacentrum, GermanySpeaker:Andreas Bruening, ZMD, GermanyAbstract: Each morning Juergen Haase (edacentrum,Germany) will open DATE11 Exhibition with an overviewabout the highlights of the Exhibition program and providebrand-new information on “What’s hot today” to allattendees.Andreas Brüning, director technology office of ZMD(Germany), will review the productivity in designing Morethan Moore applications and discuss what is required foranalog-mixed signal automotive products in his talk:Trends, Challenges and Solution Statements for More thanMoore concerning Analog-Mixed Signal AutomotiveProductsAnalog Mixed Signal is a very healthy niche regardingmicro-/nanoelectronics. Unfortunately the designproductivity has not developed much during the lastdecade and is far behind the More Moore miniaturization.The talk is dealing with the increasing complexity andrelated productivity based on an analog-/mixed signalbenchmark. Demonstrating design challenges, optimizationareas and existing solutions. As a result the hot topics forproductivity increase are shown.

1030 - 1050Organiser:Apache / STSpeakers:Yvon Imbs, ST Corporate Packaging & Automation, FranceLaurent Marechal, ST Corporate Packaging & Automation, FranceAbstract: Today’s packages are facing many challengeslinked to cost pressure, Time to Market improvement,miniaturisation. These evolutions are not, for some ofthem, moving in the right direction to sustain the

performances expected by the end users. Cost pressure is leading to reduction of area for the Siliconand for the mass production packages will lead to alimitation to off-the-shelf technologies or development ofnew cost reduction processes and technologies.Time to market is requesting first design to be the finalproduct. This can only be achieved by an increase effort interm of modelling. Modelling in therefore mandatory in allfields, system level, component level, die level etc… Allphysical domains are contributing: electrical, thermal,mechanical & thermo-mechanical.Miniaturisation will request smaller package, thinner traces,thinner substrate. All these aspects have consequences onthe electrical behaviour of the package. From a “electricaltransparent” media in the end of 1999, there are nowbecoming the bottlenecks in many applications.In this talk we will first demonstrate the effects of theseconstraints on real package designs, in term of applicationspeed, bandwidth of signals, and impact on the margins.We will also explain why the counterpart of this increasingcomplexity in the package is requesting the help of newtools that can bridge the several part of the system toensure a full system optimisation.Preliminary package studies are necessary to define thepackaging technology that needs to be optimized versusthe die and the board. It consists in impedancecomputation, interfaces layout strategy and power deliverystrategy. The used tools and the results expected fromthese preliminary studies may differ depending theapplication and/or the interfaces.Digital consumer projects (TV, Computer, etc…) are usuallyusing quite big packages as they are not constrained by aform factor. This enables the use of power & ground planeson dedicated layers of the package. The package size andthe interface speed are thus requesting a control of theimpedance for both single and differential signals.We will show simulation results based mainly on digitalprojects (TV applications, Computer & Broad band signals). Several modelling tools have been used:

* 2D tools (Ansoft) are used to define the impedanceguideline derived from the selected technology

* Fast quasi-static modelling tools enables theextraction of the preliminary design databases models forboth signal nets and power delivery networkFirst order results will then permit to validate some earlychoices in term of technology and routing strategy. Theyare also used to start some preliminary simulation atsystem level to ensure time to market objectives.More accurate models will generated later on during thedesign phase to refine the simulations and get morequantitative results (Apache Sentinel PSI, Ansoft HFSS)Package and board resonances can also be studied oncethe design database are close to completion. Linking thepackage and board database leads to resonancefrequencies that need to be considered versus theapplication frequencies.Mobile platform system using multi-GHz CPU cores areneeding a proper methodology to handle the powerintegrity analysis and supply network.The optimization ofthe power delivery network (PDN) of a System on Chip(SoC) is becoming more and more complex with theincreasing operating frequency of its CPU cores.The defined methodology is mainly using Apache toolfeatures to generate the needed models and run therequired analysis. The capabilities of Apache RedHawk areto extract a power model from a SOC, that can be reused inpackage centric tools to optimise further the powerdelivery network at package (and board) level. On theother side the package modelling tool (Apache SentinelNPE) is able to extracted a model that can be imported inthe die voltage drop analysis tool (Apache RedHawk) toevaluate the impact of the package routing.

SPEAKERS' BIOGRAPHIESYvon Imbs joined STMicroelectronics in 2000 after beinggraduated as a Ph.D from University of Limoges. He workedfor 4 years as responsible of electrical package modeling.He started some activities on IC package co-design insidethe Telecom, Peripheral & Automotive Division of ST. Thenhe joined the Corporate Packaging & Automation team. Inaddition to the electrical package modeling, he started aPackage Design Kit activity linked to the ramp-up of theIC-Package co-design activity. Now he’s is charge of theelectrical driven co-design aimed to ensure the best trade-off between cost & performances for the BGA packages.

Laurent Marechal joined STMicroelectronics in 2006 afterbeing graduated as M.S. degree in electrical engineeringfrom Polytech’Lille. He joined the Corporate Packaging &Automation team to develop embedded passive devices. Inaddition he is now in charge of accurate package modelingusing 3D Electromagnetical tools and of the support of theelectrical driven co-design activity aimed to ensure thebest trade-off during BGA package design in close relationwith the product Divisions.

1100 - 1230Organiser/Moderator: M Winterholer, Cadence, DEPanellists: F Cerisier, EASii-IC, FRS Davidmann, Imperas, UKL Ducuosso, STMicroelectronics, FRJ Engblom, Simics Wind River, SEA Mayer, Infineon, DEAbstract: Today’s complexity of embedded software issteadily increasing. The growing number of processors in asystem and the increased communication andsynchronisation of all components requires scalable debugand test methods for each component as well as thesystem as a whole. Considering today’s cost and time tomarket sensitivity it is important to find and debug errorsas early as possible and to increase the degree of test anddebug automation to avoid quality losses. Thesechallenges are not only requiring new tools andmethodologies but also organisational changes sincehardware and software developer have to work closertogether to achieve the necessary productivity and qualitygain. The panel will discuss new strategies in hardwareand software development to make embedded softwaremore reliable and easy to debug.

1315 - 1415Organiser/Moderator:Stephane Fiorillo, Infiniscale, FranceSpeakers/Panelists:Trent McConaghy, Solido Design Automation, USAJean-Paul Morin, STMicroelectronics, FrancePhilippe Raynaud, Mentor Graphics, FranceVincent Fischer, Infiniscale, FranceAbstract: This panel will focus on the process variabilityaffecting analog, mixed-signal, and custom digital designs,the various challenges it raises and the solutions that canbe applied to handle those issues. A presentation of thevarious types of process variability (lot to lot or globalvariations, local variations such as mismatch, layouteffects…) will be done. The stakes of this variability willbe highlighted, in particular the effects on the yield. Thevarious approaches to handle this variability will bepresented. At simulation level, from PVT corner simulationsto statistical analysis (Monte Carlo and enhanced MonteCarlo), various approaches can help the designer toanalyze the effects of the process variability, and todetermine the yield. The model-based approach, whichuses simulation results to build a behavioural model,allows the designer to optimize the device sizes takinginto account the process variability in order to minimizeits effects and maximize the yield. Some concreteexamples will be presented, with the presentation of thedesign, the effects of process variability, the solutions thatwere implemented and the final results. Finally, the panelwill be concluded by on open discussion and questionsfrom the audience.

1430 - 1600Organiser/Moderator:W Kruijtzer, Synopsys, NLAbstract: Starting from the application side, we presentsystem functions and their implementations on CPUs andfunction-specific hardware using concrete examples fromthe video processing domain. This includes quantitativedata on bandwidth and latency requirements and anoverview of challenges developers face if the SoCinfrastructure lacks basic provisions for Quality-of-Service.We then present how these challenges can be addressed bya combination of architectural principles and associated

6.8 PANEL SESSION – EmbeddedSoftware Debug and Test

ET08 Process Variability: Challengesand Solutions

7.8 EMBEDDED TUTORIAL –Predictable System Integration

• WEDNESDAY •wednesday 16 march

ET06 Highlights of DATE11 Exhibition/More than Moore Solutions forAutomotive Products

ET07 Ball Grid Array Packageselectrical optimization using Apachepackage modeling tools

ET05 How Software development cantake benefit of a platform powermodel



analysis techniques, based on network calculus. Finally weshow how these techniques can be applied in buildingreal-life SoCs. Key benefits of the presented techniquesare predictable performance and improved time-to-market,while avoiding costly over-dimensioning to guarantee real-time behaviour.

1700 - 1830Organisers:T Kazmierski, Southampton U, UKC Grimm, TU Vienna, ATModerator:C Grimm, TU Vienna, ATAbstract: The tutorial addresses upcoming technologiesaimed at communication networks for automotiveapplications. The first presentation will discussapplications of networked or even autonomous sensors in acar. The second presentation will emphasize novel, cross-industry communication technologies that enhance thestandard IEEE 802.3 switched Ethernet. The third andfourth presentations will introduce applications andmethods for the design of wireless communication in a car,including methods for wireless energy supply of sensornodes in cars as well as design tools and methods fordesign of wireless sensor nodes.

1000 - 1010Organiser/Moderator:Juergen Haase, edacentrum, GermanyAbstract: Each morning Juergen Haase (edacentrum,Germany) will open DATE11 Exhibition with an overviewabout the highlights of the Exhibition program and providebrand-new information on “What’s hot today” to allattendees .This will be followed by testimonials providing attendeeswith experience gained in real-life projects: designerspresent how they were able to solve major designchallenges with state-of-the-art methodologies and tools.

1010 - 1030Organiser:Apache / ST-EricssonSpeakers/Panelists:Olivier Bayet, System in Package (SiP) design, ST-Ericsson, FranceAbstract: The optimization of the power delivery network(PDN) of a System on Chip (SoC) is becoming more andmore complex with the increasing operating frequency ofits CPU cores. Having a proper methodology to handle thepower integrity analysis and supply network optimizationis required to secure the integration of multi-GHz CPUcores in a mobile platform system.The approach used for ST-Ericsson U8500, the industry’sfirst dual core SMP platform integrating a HSPA+ modem,is based on a system level context available in thesimulation environments of each PDN contributor. For thisproject, the analysis goal was to reach an operatingfrequency of 1GHz by optimizing the power integrity of theARM Dual Cortex A9 embedded in the U8500 platform.In this paper, the first part is describing the methodologyand flow used to perform a CPU core power integrity checkin a core block level environment using a system levelcontext. The second part is explaining how to extend it toan analysis in package or platform environment still using asystem level context. For this methodology, Apache DesignSolutions tools provide useful features and extractedmodels to enable power supply analysis at system level.Taking into account the capabilities of Apache RedHawk toload a top level and package context even for a voltagedrop analysis at block level, a SoC partition is created andplugged into the tool with models of a package and aboard with its decoupling capacitors and a voltage

regulator. From this analysis, a Chip Power Model (CPM) isgenerated to enable, in Apache Sentinel-PI and othertools, both package and board level analyses taking intoaccount the complete system.For the U8500 project, this study resulted in a PDNimpedance reduction of about factor 6 in the criticalfrequency range and enabled an increase from a 600MHz toa 1GHz ARM Dual Cortex A9. This also provided an efficientplacement, number and value of decoupling capacitors.The benefit of this solution is the consistency of models andanalysis in the various environments, an access to a simplemodel (describing a CPU core power/ground grid and itscurrent activity) that could be used with different simulationsetups, and an enabler for correlation with measurements.This methodology also provides a first step to solve theforeseen challenges of the next generations of CPU cores.

SPEAKERS' BIOGRAPHYOlivier Bayet joined STMicroelectronics in 2000 aftergraduating as a microelectronics engineer from ENSEIRBengineering school. He has worked as a CAD design engineerin the area of IC/Package assembly checks and Voltage Dropanalysis, and is currently leading in ST-Ericsson anIC/Package co-design and Signal & Power integrity activityfor digital ICs embedded in mobile platforms.

1030 - 1050Organiser:EASii-IC, FranceSpeaker/Panellist:François Cerisier, Senior Verification Consultant and EDAActivities Manager, EASii-IC, FranceAbstract: As System-On-Chip complexity continues toincrease, complex state machines are being replaced byprocessor based sub-systems. The functionalities of suchsub-systems are partitioned between hardware blocks anddedicated interrupt based firmware.Verifying such sub-systems faces the challenge ofidentifying bugs not only in both the hardware and thesoftware parts, but also at the boundary of the twodisciplines.Co-Verification methodologies have proved to beinteresting approaches for critical software verification.Existing methodologies are however based on theassumption that the software provides APIs or softwareinterfaces. They therefore do not directly apply to interruptdriven firmware of these sub-systems.We present here an approach which enables interruptbased firmware verification for such partitionedhardware/firmware sub-systems at the early stages of theproject and before the silicon is available. Thismethodology has been applied on an industrial complexcontrol sub-system. Hardware event controllability andobservability is reached using extended hardware coveragedriven verification techniques and the required softwareobservability is achieved using the monitoring facilities ofCadence ISX tool (Incisiv Software Extension).

1100 - 1230Organiser:T Fitzpatrick, Mentor Graphics, USModerator:A Crone, Mentor Graphics, SEPanellists:C Chevallaz, STMicroelectronics, FRB Dickman, ARM, UKV Esen, Infineon Technologies, DEO Bringmann, FZI, DEM Rohleder, Freescale, DEAbstract: In the last few years, the industry has seenacceleration in the evolution of verificationmethodologies. While the industry focus has been onenabling a standard based approach to help today’schallenges, one can wonder what is needed to prepare usself for the further verification challenges. The expertpanellists will discuss the many aspects of verificationmethodologies, the requirements and predictions forverification methodologies needed 4-5 years from now on.

1245 - 1345Organiser:COMPLEX FP7 European integrated projectModerator:Kim Grüttner, OFFIS, GermanySpeakers/Panellists:Kim Grüttner (OFFIS)Bart Vanthournout (Synopsys)Franco Fummi (EDALab)Emmanuel Vaumorin (Magillem Design Services)Abstract: Consideration of an embedded system’s timingbehavior and power consumption at system-level is an ambitioustask. Sophisticated tools and techniques exist for power andtiming estimations of individual components such as customhard and software as well as IP components. But prediction ofthe composed system behavior can hardly be made.In this session we present the concept of an ESLframework for timing and power aware rapid virtual systemprototyping of embedded HW/SW systems. Our proposedflow combines system-level timing and power estimationtechniques available in commercial tools with platform-based rapid prototyping. Our proposal aims at thegeneration of executable virtual prototypes from afunctional C/C++ specification. These prototypes areenriched by static and dynamic power values as well asexecution times. They allow a trade-off between differentplatforms, mapping alternatives, and optimizationtechniques, based on domain-specific workload scenarios.The proposed flow will be implemented in the COMPLEXFP7 European integrated project (http://complex.offis.de).

1400 - 1530Organiser/Moderator:G Gielen, KU Leuven, BEAbstract: Process variability causes statistical spread onthe performance of ICs, eventually limiting circuit yield.In addition, aging effects in nanometer CMOS technologiescause a shift in transistor parameters over time, possiblycausing circuit malfunction within the lifetime of thecircuit. Some of these wear-out phenomena are stochasticin nature, introducing asymmetry in circuits. To guaranteea reliable product over the entire lifetime, fast andefficient design tools can help a designer to estimate theimpact of various reliability threats on his/her circuit, atdesign time. The stochastic nature of the phenomenarequires techniques well beyond current commercial tools.This hot topic session addresses both accurate stochastictransistor compact models that include reliability effects,as well as efficient stochastic CAD solutions to evaluatethe reliability of an IC at circuit level and at system level.In addition, alternative novel system approaches arepresented that exploit the stochasticity.

1600 - 1730Organiser:J Nowak, IMMS GmbH, DEModerator:R Sommer, TU Ilmenau, DEAbstract: Analogue design still is the bottleneck in thedevelopment of mixed-signal ICs. This is due to the factthat the three steps in analogue circuit design – topologygeneration or modification, sizing and layout generation –are mainly carried out by hand. In this special sessionfour methods will be presented which allow a semi-automated design process. These approaches include afully automated hierarchical topology generation foranalogue circuits, a generation of a compensation networkby automated topology modification, a methodology forsizing based on a combination of analytic and numericaltechniques and a method for modular layout generation.The methods and the resulting tools relieve the designerfrom routine tasks, allow more space for creativity andenable re-use.

10.8 PANEL SESSION –State of the ArtVerification Methodologies in 2015

11.8 HOT TOPIC – Stochastic CircuitReliability Analysis in NanometerCMOS

ET12 Early Timing and PowerInformation of Complex SoC Designsusing Augmented Virtual Platforms

12.8 HOT TOPIC – SynthesisSupported Increase of Efficiency inAnalogue Design

ET11 Co-Verification of an interruptdriven firmware sub-system usingCadence ISX and Coverage Driventechniques

8.8 EMBEDDED TUTORIAL –Communication Networks in NextGeneration Automobiles

• THURSDAY •thursday 17 march

ET09 Highlights of DATE11 Exhibition/Testimonials

ET10 System level power integrityanalysis and supply networkoptimization of a dual core CPU



The DATE 11 conference programme allows generousopportunities for delegates to visit the exhibition andattend the presentations in the exhibition theatre.

COFFEE & LUNCH BREAKSDelegates coffee will be served in the main exhibition halland the additional exhibition area. Lunch is available inRoom Ecrins on the lower ground floor and in theexhibition hall there is a cash bar for visitors andexhibitors.

Tuesday 15 MarchMorning Coffee Break 1030 – 1130

Lunch Break 1300 – 1430

Afternoon 1600 – 1700

Wednesday 16 MarchMorning Coffee Break 1000 – 1100



Thursday 17 MarchMorning Coffee Break 1000 – 1100



Evening Reception offered bythe City of Grenoble 1830-1930 - Tuesday 15 March

DATE PARTY1930 - Wednesday 16 March

This year the DATE party will take place in the World TradeCenter on Wednesday 16 March. The evening will feature abuffet style dinner with plenty of buffet points and drinksto accompany dinner. Musical entertainment with theopportunity to dance will be provided by the popular neo-folk band DJAL. In an enjoyable atmosphere participantswill have the opportunity to meet and mingle with theirfriends and colleagues. All conference attendees, users,vendors and their guests are encouraged to come to theparty. Additional tickets for the full Evening SocialProgramme may be obtained for 70 Euros each (please askat the registration desk). Entrance will be by ticket only,so please check that you receive the party ticket whenyou register.

A number of specialist interest groups will be holding their meetings at DATE. Currently, the following

meetings are scheduled but a full list of fringe meetings with description of content will be found on

the DATE web portal – www.date-conference.com

Time

Day Time Meeting & Contact Room Type

Mon 1900-2100 EDAA/ACM PhD Forum Salle de OpenPeter Marwedel <[email protected]> Reception

Tues 1830-1930 EDAA General Assembly 7 Laux 4 OpenNorbert Wehn <[email protected]>

Tues 1830-2030 ETTTC Meeting Bayard OpenMatteo Sonza Reorda <[email protected]>

Tues 1830-2130 European SystemC Users Group Meeting Meije OpenAxel Braun <[email protected]>

Thu 1730-2030 DIAMOND Tutorial: Handling the Challenges of Debug and Reliability Les Bans OpenMaksim Jenihhin <[email protected]>

• SOCIAL NETWORKING • SOCIAL NETWORKING •social networking

The event is sponsored by:

the European Design and Automation Association

the EDA Consortium

IEEE Council on EDA

ECSI

ACM - SIGDA

RAS

and is organised in cooperation with:

ACM - SIGBED

IEEE Computer Society

IEEE Solid-State Circuits Society (SSCS)

IFIP

IET

SAME

Event sponsors


Commercial sponsor

• MEDIA PARTNERS • MEDIA PARTNERS •media partners

The DATE organisation and sponsors would like to extend their warmest gratitude to all press journalists who give DATE coverage intheir editorial pages. Listed below are the media houses and publications who generously agree to media partnership with DATE,and whose publications can be found at distribution points around the exhibition.

If you would like to arrange a Media Partnership with DATE for future events, please contact: Claire Cartwright, Event Manager, European Conferences, tel: +44 (0) 203 052 8065 email: [email protected]

CHIP DESIGN MAGAZINE

Chip Design covers all of the technical challenges and implementationoptions engineers face in the development and manufacture of today'scomplex integrated circuits. Chip Design is the only media networkdedicated to the advanced IC Design market. Visitwww.chipdesignmag.com to stay informed about the latestdevelopments in chip modeling, architecture, design, test andmanufacture, from EDA tools to digital and analog hardware issues. TheSystem Level Design and Low Power Engineering Portals offer focusededitorial content you won’t want to miss. And, be sure to visitwww.http://eecatalog.com/ for valuable information about all ofExtension Media's outstanding technology resources.

EDA CONFIDENTIAL

EDA is a commercial-free publication providing a quiet place forconversation about the Electronic Design Automation industry and itscompanion technologies. The coverage does not intend to becomprehensive, but does intend to provide some food for thought. Tothat end, EDA Confidential includes "Recipes", Freddy Santamaria's"Gourmet Corner", as well as "Voices" of other contributing authors,"Off the Record" op-ed pieces, and "Conference" coverage.

ELECTRONIQUES

ElectroniqueS the reference monthly for decision makers and engineersin the electronics sector

Circulation of 10,000 copies

www.electroniques.biz, the electronic professional’s web site

Daily Newsletter, the day’s essential news about our industry’s majorsectors

Sent to more than 26,000 free subscribers

Weekly newsletter, the newsletter that summarizes the previous 5 dailynewsletters main topic

Sent to more than 23,000 free subscribers

Vertical newsletter, 3 subjects: Automotive / Mil-Aero / Medical

5 mailings a year (each 2 in 3 months)

ELEKTRONIK I NORDEN

Elektronik i Norden, an important tool for the Nordic electronicindustry. We want Elektronik i Norden to be the most important sourceof information for the Nordic electronic industry (Sweden, Finland,Norway and Denmark). A circulation of 25 800 personally addressedcopies proves we are the major electronics paper in this area. Wepublish news, comments and in-depth technical articles.

MICRONEWS

Beginning in 1998 with Yole Développement, we have grown tobecome a group of companies providing market research, technologyanalysis, strategy consulting, media in addition to finance services.With a solid focus on emerging applications using silicon and/or micromanufacturing Yole Développement group has expanded to includemore than 40 associates worldwide covering MEMS and microfluidics,Advanced Packaging, Compound Semiconductors, Power Electronics,LED, and Photovoltaic. The group supports companies, investors andR&D organizations worldwide to help them understand markets andfollow technology trends to develop their business.

Micronews Media includes our website, www.i-micronews.com, our bi-weekly magazine Micronews, and the four Technology Magazines: MEMSTrends, 3D Packaging, PV Manufacturing and Efficen'Si.

TECH DESIGN FORUM

Today’s electronic design engineers face broader challenges than everbefore. Software is becoming as important as hardware. And in the ICsupply chain, former competitors are now collaborating to achievesuccess.

Tech Design Forum publication (formerly called the EDA Tech Forum) isthe premier guide for success in this complex environment. Focused onthe design automation market, this publication and its rich websiteoffer a wealth of practical advice on how to successfully negotiate theday-to-day problems designers face.

The IET

The IET is europe's largest professional body for engineers andtechnologists, we offer a wide range of products, services andprofessional qualifications to keep you ahead of the game. With150,000 members based in 127 countries networking is key to theirand your success - find out how to join and be part of the KnowledgeNetwork by visiting us www.theiet.org

THE NEXT SILICON VALLEY

The Next Silicon Valley is an independent media website that publishesglobal news and information about the world of innovation,entrepreneurship, technology development, regional economicdevelopment, venture capital, and investment promotion across globalmarkets. The Next Silicon Valley reaches readers in more than 90countries and 400 cities worldwide.



What’s new in the EuropracticeCadence portfolio for 2011 –Technical Update

Tuesday 15 March, 1330-1730

Today 386 institutes across Europe are usingCadence tools via Europractice in theireducation and research. The portfolio iscontinuously evolving as new tools becomeavailable from Cadence. This seminar givesan update on the latest functionality from atechnical viewpoint with special emphasison digital, mixed signal and low powerdesign including chip planning. The seminaralso gives an opportunity for academicinstitutions to ask Cadence technical andR&D staff questions.

Unifying IP-XACT platformassembly with virtual platformmodeling

Wednesday 16 March, 1330-1630

The goals for IP-XACT have expanded fromRTL IP warehousing and easier SoC assembly.As virtual platform adoption has grown, thenatural need arises to assemble TLM IP intoa virtual platform, and refine it into theresulting RTL SoC. This tutorial will highlightthe creation and assembly of SoCs startingfrom virtual platforms, key decisions to betaken, and potential issues to avoid.

Presenter:Jean-Michel Fernandez ([email protected]),Cadence; Cyril Spasevski, Magillem

ADVANCES AT CMPThursday 17 March, 0900-1230

CMP is a broker in ICs and MEMS forprototyping and low volume production.Advanced industrial processes are availablein CMOS, BiCMOS, SiGe BiCMOS, SOI, GaAs,MEMS and 3DIC. CMP distributes andsupports Design Kits and several CAD tools.

The Seminar will review available processesas well as recently introduced processes like3DIC from Tezzaron, 20nm FDSOI from LETI,pHEMT GaAs from TRIQUINT.

New processes will also be introduced like amagnetic-CMOS process.

Presenter: Bernard Courtois, Kholdoun Torki

A significant number of European EDAvendors will join forces and providethe semiconductor industry withdedicated innovation for chip andsystem development. In addition totheir booths in the European EDAvillage, presentations providingoverviews and testimonials shall betaking place in the Exhibition Theatre,along with workshops in conjunctionwith client companies.

Please see the current list of EDAVillage participants below:

DATE 2011 presents the Tool Seminar Track.The seminars listed below are FREE & OPEN TO ALL, however places are restricted.All seminars are held in Salle Berlioz on the Ground Floor, adjacent to the registration desk.Please collect a voucher from the registration desk.

COMPANY NAME STAND NUMBER

CISC Semiconductor Design +Consulting GmbH 43

Concept Engineering GmbH 42

Docea 39

INFINISCALE 40

MunEDA 31

Nano-Tera.ch 45

Satin Technologies 41

XYALIS 34

• TOOL SEMINARS • TOOL SEMINARS •tool seminars

• EUROPEAN EDAeuropean EDA villageINTERACTIVE

PRESENTATIONSInteractive presentations allow

presenters to interactively discussnovel ideas and work in progress thatmay require additional research workand discussion, with other researchersworking in the same area. Interestedattendees can wal karound freely andtalk to any author they want in a vividface-to-face format. The author mayillustrate his work with a slide show

on a laptop computer, ademonstration, etc. IP presentationswill also be accompanied by a poster.Each IP will additionally be introducedin a relevant regular session prior tothe IP Session in a one-minute, one-

slide presentation.To give an overview, there will be onecentral projection displaying a list ofall the presentations going on at thesame time in the IP area. InteractiveSessions will be held in the Salle deReception area in 30-minute timeslots during coffee and exhibition

UNIVERSITY BOOTHDATE 11 will feature the University

Booth where system and VLSICADtools developed in Universities

and Research Institutes aredemonstrated as well as circuits intheir working environment. Thisprovides an alternative and moredirect way of communicating CADresearch results and displayingworking silicon to the interested

specialists.The University Booth willbe located in the Exhibition Hall and

will be furnished with popularworkstations. A rotating schedule willoperate throughout the three days.


• VENUE PLAN • VENUE PLAN • VENUE PLAN •venue plan

• EXHIBITION FLOOR PLAN •exhibition floor plan


• EXHIBITOR LIST • EXHIBITOR LIST • exhibitor list

2PARMA (PARallel PAradigms and Run-timeMAnagement techniques for Many-coreArchitectures) FP7-ICT-248716 EP15

ACCELONIX 12

ADACSYS 8

ADICSYS 7

AgO Inc 10

ANSYS / Ansoft 6

ApS Brno Ltd., Codasip Division 37

Arteris, Inc. 54

Asygn 53

Atrenta Inc. 27

BLUE PEARL SOFTWARE 28

Chipright 15

CISC Semiconductor Design + Consulting GmbH 43

CMP 32

COCONUT EU project EP10

Compaan Design BV 44

COMPLEX - COdesing and powerManagement in PLatform-based design space EXploration EP16

Concept Engineering GmbH 42

Cortus S.A. 10

CréVinn 15

CST - Computer Simulation TechnologyAG 56

DEFACTO TECHNOLOGIES 25

DELTA 47

Design Automation Conference (DAC) 16

DOCEA Power 39

Duolog Technologies Ltd 15

EASii-IC 29

EDA Confidential 20

EDALab 48

edXact 23

ElectroniqueS 26

Enterprise Ireland 15

EUROPRACTICE 14

Fractal Technologies 11

GLOBALFOUNDRIES 1 & 2

Gold Standard Simulations Ltd. 30

HiPEAC NoE EP11

INFINISCALE 40

Infotech 57

IP SOC 11 21

MADNESS - Methods for predictAble Designof heterogeneous Embedded Systems withadaptivity and reliability Support EP12

Magillem Design Services 33

MICROLOGIC Design Automation 51

Midas 15

MINALOGIC GRENOBLE ISERE 9

MOSIS 35

MunEDA 31

Nano-Tera.ch 45

nSilition 36

N. S. Mangat & Co. 55

Presto Engineering, Inc. 5

ProximusDA 49

R3LOGIC 52

SAME 18

Satin Technologies 41

SELEX Galileo 58

Silansys Semi 15

SPRINGER 3

Tanner EDA 35

Target Compiler Technologies 4

Tech Design Forum 19

The Next Silicon Valley 17

TinnoTek Inc. 50

TowerJazz 13

TRAMS (Terascale Reliable Adaptive Memory Systems) EC FET-IST 248789 EP9

Tyndall’s Design Technology Evaluation Group 15

University Booth 46

University of Southampton 22

Veriest Venture 24

XYALIS 34

Company Stand Company Stand Company Stand


• EXHIBITORS • EXHIBITORS • EXHIBITORS •exhibitors


The 2PARMA project focuses on the definitionof a parallel programming model combiningcomponent-based and single-instructionmultiple-thread approaches, instruction setvirtualisation based on portable bytecode,run-time resource management policies andmechanisms as well as design spaceexploration methodologies for Many-coreComputing Fabrics.The 2PARMA project will demonstrate

methodologies, techniques and tools by usinginnovative hardware platforms provided anddeveloped by the partners, including the“Platform 2012”, an early implementation ofMany-core Computing Fabric provided bySTMicroelectronics.To ensure a wide range of application

scenarios comprising the typicalcomputation-intensive workload of a general-purpose computing system, a set of industrialhigh performance demanding applications willbe used and customized by using thetechniques and methodologies developed in2PARMA project. Applications’ architecture,development and integration will leverage inparticular from the acknowledged experienceof three partners from the Consortium: HHIfor Scalable Video Coding application, RWTHfor Cognitive Radio, and IMEC for Multi View.

ACCELONIX, société indépendante etfournisseur de solutions équipements etlogiciels pour l’assemblage et le test descartes électroniques et microélectronique estreconnue par ses CLIENTS pour son savoir-faire, son expérience et son sens du service.Dans ce cadre, ACCELONIX travaille avec desfournisseurs offrant des solutions originalesdans le domaine du test et de la validation decomposants.

Start verifying your FPGA IP blocs anddesigns from the very begining of yourproject... and on your final hardware target.ADACSYS provides innovative hardwareaccelerated functional verification solutionsenabling designers and developers to easily andseamlessly shift from RTL software simulationverification test benches to any FPGA board.Our patented software compilation andruntime flow automatically maps your designsand test benches on any FPGA board. Itenables you to quickly verify and certify yourFPGA IP blocs and designs on your selectedFPGA target.Our solutions are easy to use and thus havefast learning curves. They reduce yourproducts time to market as well as the risks

associated with functional errors and enablesyou to deliver more robust products.Today our offer consists of:A-Soft: the software only solutionFor customers who already have their ownFPGA board.A-Full: the complete integrated solutionThis turn-key hardware and software productincludes A-Soft and an FPGA board, bothpreconfigured.A-OD: the platform as a service version of A-FullThis dematerialized and secure product is forcustomers who want the immediate flexibilityof on-demand access in terms of capacity andadded performance.

ADICSYS introduces a tool-set enabling aneasy and transparent insertion ofprogrammable logic for ASICs, SOCs andsilicon IPs in general. The great incentive toimplement this flexibility lies in the reductionof risks associated with errors, specificationchanges and early adopters' challenges. Thedevelopment and verification time for criticalblocks can be minimized while bring-up anddebugging capabilities are enhanced.In today's complex systems, customizablelogic can reveal itself as a key element forend user applications.ADICSYS solutions seamlessly integrate intoexisting design flows, making them simpleand highly cost effective for customers

stand EP15

2PARMA Contact: Prof. Cristina SilvanoPolitecnico di MilanoDipartimento di Elettronica e Informazionevia Ponzio 34/5, I-20133 Milano ItalyTel: +39 02 2399 3692Fax: +39 02 2399 3411E-Mail: [email protected]: www.2parma.eu

PRODUCT FINDERASIC and SOC Design:Behavioural Modelling & SimulationPower & Optimisation System-Level Design:Behavioural Modelling & AnalysisHardware/Software Co-Design Services:Design ConsultancyPrototypingTraining Embedded Software Development:CompilersSoftware/Modelling Semiconductor IP:Processor Platforms Application-Specific IP:Multimedia GraphicsWireless Communication

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ACCELONIX Contact: Patrick LegenrePA du Long Buisson, 260 rue Clément Ader27000 EvreuxFRANCETel: +33 2 32 35 64 80Fax: +33 2 32 35 00 66E-Mail: [email protected]: www.accelonix.fr

PRODUCT FINDERTest:Design for TestDesign for Manufacture and YieldTest Automation (ATPG, BIST)Boundary ScanMixed-Signal TestSystem Test Hardware:FPGA & Reconfigurable PlatformsDevelopment Boards

stand 8

ADACSYS Contact: Erik Hochapfel7 rue de la Croix Martre91120 PALAISEAUFRANCETel: +33 0 1 69 19 72 72Fax: +33 0 1 69 19 72 72E-Mail: [email protected]: www.adacsys.com

PRODUCT FINDERASIC and SOC Design:Verification System-Level Design:Acceleration & Emulation Test:Design for TestSystem Test Services:PrototypingTraining

stand 7

ADICSYS Contact: Philippe DIEHL44 rue Cauchy94110 ARCUEILFRANCETel: +33 1 55 01 04 35E-Mail: [email protected]: www.adicsys.com

PRODUCT FINDERTest:ASIC and SOC Design:Synthesis Services:Design Consultancy Semiconductor IP:Configurable Logic IP



AgO is an EDA company, specialising inanalog, RF and mixed-signal design tools. TheAnXplorer tool provides feasibility analysis,global optimisation and centering. It isapplicable to the design of circuits forwireless communications, automotive,industrial and medical applications.The feasibility analysis – using DC operatingpoint simulations – identifies the part of thedesign space where the circuit is stable. ThenAnXplorer's multi-algorithm strategy rigorouslysearches this space, and can find a globaloptimum in the presence of local optima.Circuit designers can use AnXplorer to rapidlyexplore the design space to evaluate differentcircuit topologies. It can also be used to finda robust design solution over a range process,temperature and supply voltage corners. Thishelps improve yield and enhances theprobability of first time silicon success.When using simulation-based optimisationAnXplorer can work with Eldo, HSpice, MSimand Spectre simulators. It also offersequation-based optimisation.

ANSYS is a leading developer of high-performance electronic design automationsoftware. The products are designed tosimulate high performance electronics designsfound in mobile communication and internetdevices, broadband networking componentsand systems, integrated circuits, printedcircuit boards, and electromechanical systems.Siwave™ analyzes entire printed circuit

boards and IC packages including packagesmerged onto boards for complete channelanalysis. SIwave extracts frequencydependent circuit models of signal nets andpower distribution networks directly fromlayout databases.HFSS™ is the industry-standard software forS-parameter extraction and 3-Delectromagnetic field simulation of high-frequency and high-speed components. Signalintegrity engineers use HFSS software toevaluate signal quality, includingtransmission path losses, reflection loss dueto impedance mismatches, parasitic couplingand radiation.DesignerSI™This easy to use design platform integratesrigorous EM analysis with circuit and systemsimulation in a highly accurate design flow.Engineers using DesignerSI can leveragemultiple signal integrity simulation methodssuch as traditional transient, fastconvolution, statistical, and IBIS-AMIanalyses in a single user interface.

The Codasip® team is dedicated helping thecustomers to develop SoC’s using ASIP coresmore efficiently while reducing time-to-market significantly. Codasip® was founded in2005. Codasip® is venture funded by Ministryof Industry of the Czech Republic.

Arteris provides Network-on-Chipinterconnect IP to SoC makers so they canreduce cycle time, increase margins, andeasily add functionality. Unlike traditionalsolutions, Arteris plug-and-play technology isflexible and efficient, allowing designers tooptimize for throughput, power, latency andfloorplan. Arteris products reduce wirerouting congestion and ease timing closure.

Asygn specialises in difficult analog/mixed-signal and RF designs, providing specificationand verification solutions in the form of toolsand consulting.If you have issues simulating very large A/MSor RF systems or in dealing with high-Qcircuits, then come and see us. If you are fedup with huge simulation runtimes, caused bysignals with extremely different timeconstants, then we may have a solution foryou. If you are tackling systems withrepeated analog content (such as imagers),

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AgO Inc Contact: Dr Roddy UrquhartAlpha Star Ltd10 Pitts LaneAndoverSP10 2HYUKTel: +44 1264 369483Fax: +44 1264 369483E-Mail: [email protected]: www.ago-inc.com

PRODUCT FINDERASIC and SOC Design:Analogue and Mixed-Signal DesignRF Design

stand 6

ANSYS / Ansoft Contact: Xavier Le GoaerImmeuble Central Gare1 Place Charles de Gaulle78180 Montigny-le-BretonneuxTel: +33 1 30 64 89 90Fax: +33 1 30 64 89 91E-Mail: [email protected]: www.ansys.com

PRODUCT FINDERASIC and SOC Design:Behavioural Modelling & SimulationPower & OptimisationPhysical Analysis (Timing, Themal, Signal)VerificationAnalogue and Mixed-Signal DesignMEMS DesignRF Design System-Level Design:Behavioural Modelling & AnalysisPhysical AnalysisPackage DesignPCB & MCM Design Services:Training

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ApS Brno Ltd., CodasipDivision Contact: Karel MasarikBozetechova 2612 66 BrnoCzech RepublicTel: +42 0608132875Fax: +42 0541 211 479E-Mail: [email protected]: www.codasip.com/

PRODUCT FINDERASIC and SOC Design:Design Entry System-Level Design:Acceleration & EmulationHardware/Software Co-Design Services:Design ConsultancyTraining Embedded Software Development:CompilersDebuggersSoftware/Modelling

stand 54

Arteris, Inc. Contact: Kurt Shuler111 W. Evelyn Avenue, Suite 101,Sunnyvale, CA 94086, USATel: +1 408 470-7300Fax: +1 408 470-7301E-Mail: [email protected]: www.arteris.com

PRODUCT FINDERSemiconductor IP:Encryption IPOn-Chip Bus InterconnectOn-Chip Debug

stand 53

Asygn Contact: Andrew Betts445 rue Lavoisier - F38330 Montbonnot,FranceTel: +33 4 76 89 80 27E-Mail: [email protected]: www.asygn.com



then you should look at our latest software.Asygn software products have been proven todramatically accelerate simulations oncomplex analog systems such as mobilephone radios, advanced MEMs sensors andcomplex imaging arrays. The productsintegrate seamlessly into standard IC designflows, ensuring design database consistencyfrom system-level down to circuitimplementation.Asygn also offers design services in the aboveareas. Its extensive track record of successfulconsulting projects includes custom tooldevelopment – a very interesting solution forcompanies with special challenges.

Atrenta is the leading provider of Early DesignClosure® solutions to radically improve designefficiency throughout the IC design flow.Customers benefit from Atrenta tools andmethodologies to capture design intent, exploreimplementation alternatives, validate RTL andoptimize designs early, before expensive andtime-consuming detailed implementation. Withover 150 customers, including the world’s top10 semiconductor companies, Atrenta providesthe most comprehensive solution in theindustry for Early Design Closure. Atrenta, Rightfrom the Start!

Blue Pearl Software provides tools whichlower design risk, improve the quality ofresults, save time and reduce the cost of theirchip design process.Blue Pearl Software's RTL Analysis technologyautomatically checks HDL for compliance withuser-selected and user-defined properties,including netlist checks and advancedproperty checks for CDC. Blue Pearl's Timing Constraint Generation andManagement reads RTL and statically identifiescomplex false and multicycle paths that occurdue to complex control logic. Blue Pearl writesSDC, and writes assertions for testing pathswith formal analysis tools. Blue Pearl alsomerges and compares SDC and migratesconstraints up and down the design hierarchy.Blue Pearl's Timing Constraint Validationreads SDC files and validates them using BluePearl's powerful state space searchtechnology. If paths are found invalid BluePearl outputs a testbench and patterns thatshow how invalid paths can be sensitized. These three technologies have beenintegrated into a single executable program(The Blue Pearl Software Suite) for fast designanalysis, CDC checking, and timing constraintgeneration, management, and validation.

Accelerate your SystemVerilog migration by50% with Chipright. Chipright providesproducts and services for migration fromlegacy verification languages andenvironments to the more widely supportedIEEE SystemVerilog language. Our productsand services can be utilised to speed up thetransition timeframe's associated withmigration services. • Automation to jumpstartthe creation of SystemVerilog test benchesand transactors. • Training platform toeducate engineers on SystemVerilogverification methods. • Targeted mechanismfor migrating legacy verification technologyinto an advanced SystemVerilog solution.Chipright can convert legacy test benchesand BFM’s to SystemVerilog test environmentsand transactors by utilising our extensiveverification know-how. Visit our stand todayto find out how we can migrate your existingtest case libraries and infrastructure tomaximise the benefits on offer through usingSystemVerilog. We support VMM, OVM andUVM. Visit www.chipright.com or [email protected]

CISC Semiconductor Design+Consulting GmbHis a design and consulting service companyfor industries developing embeddedmicroelectronic systems with extremely short

PRODUCT FINDERASIC and SOC Design:Behavioural Modelling & SimulationVerificationAnalogue and Mixed-Signal DesignMEMS DesignRF Design System-Level Design:Behavioural Modelling & Analysis Services:Design ConsultancyPrototypingTraining Hardware:FPGA & Reconfigurable PlatformsDevelopment Boards

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Atrenta Inc. Contact: Charu Puri2077 Gateway Place, Suite 300San JoseCA 95110USATel: +1 408 453 3333Fax: +1 408 453 3322E-Mail: [email protected]: www.atrenta.com

PRODUCT FINDERASIC and SOC Design:SynthesisPower & OptimisationPhysical Analysis (Timing, Themal, Signal)Verification System-Level Design:Physical Analysis Test:Design for Test Services:Prototyping

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BLUE PEARL SOFTWARE Contact: Nichole Fox4677 Old Ironsides DriveSuite 430Santa Clara, CA 95054 USATel: +1 408 9610121Fax: +1 408 9610125E-Mail: [email protected]: www.bluepearlsoftware.com

PRODUCT FINDERASIC and SOC Design:Design Entry

stand 15

Chipright Contact: James O'ReillyIIBCGMITDublin RoadGalwayIrelandTel: +353 91 444168Fax: +353 91 444210E-Mail: [email protected]: www.chipright.com

PRODUCT FINDERASIC and SOC Design:Verification Services:Design ConsultancyTraining

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CISC SemiconductorDesign + Consulting GmbH Contact: Dr. Markus PistauerLakeside B079020 KlagenfurtAUSTRIATel: +43 463 508 808Fax: +43 463 508 808-18E-Mail: [email protected]: www.cisc.atSPECIAL FOCUS DAY

Wireless Innovations forSmartphones

WEDNESDAY 16 MARCH

1400 KEYNOTE

Hannu Kauppinen, Director, Head of Radio Systems Laboratory, Nokia Research Center, Finland



Time-To-Market cycles. Our core competencesare: System design, modeling, simulation,verification and optimization ofheterogeneous embedded microelectronicsystems with a particular focus onAutomotive and RFID systems.Our customers are represented in theSemiconductor, Automotive and RFID industry.CISC Semiconductor was founded in 1999 and is100% privately owned. The company is managedby an international team of highest skilledexperts. Our main office is situated inKlagenfurt, Austria (close to well knownWörthersee) right in the heart of the Alpen-Adria-Region. We are proud to be able toconduct our international business from this partof the world and also enjoy our life with ourfamilies and friends within this beautiful nature.Being an independent company, CISCfurthermore is able to provide non CAD/CAEmarket driven technology for individualcustomer solutions. CISC offers commercial toolsand techniques for simulation based systemdevelopment of embedded microelectronicsystems including RFID systems.

CMP is a manufacturing broker for ICs and MEMS,for prototyping and low volume production. Since 1981, more than 1000 Institutions from60 countries have been served, more than5300 projects have been prototyped through600 manufacturing runs, and more than 55different technologies have been interfaced. Integrated Circuits are available on CMOS,SiGe BiCMOS, CMOS-Opto fromSTMicroelectronics and Austriamicrosystems,20 nm FDSOI from CEA-LETI, 3D-IC from

TEZZARON/GLOBALFOUNDRIES, and 150nmpHEMT GaAs from TRIQUINT. ARM IP cores areavailable on 130nm µ and 65 nm CMOS.MEMS are available on various processes:specific MEMS technologies (PolyMUMPS,SOIMUMPS, MetalMUMPS from MEMSCAP,SUMMIT from SANDIA).Design kits for most IC CAD tools andEngineering kits for MEMS are available.Assembling is provided in a wide range ofplastic and ceramic packages.CAD software (tools for PCs, ARM suite oftools, ...) are also proposed.

The COCONUT project is intended to propose amodelling and verification flow to enhanceand speed-up embedded platform’s designand configuration of mixedcontinuous/discrete models. In this context,the scientific and technological objective ofthe COCONUT project consists of developing asystematic methodology and a set of tools tointegrate correct-by-constructionrefinement/abstraction and post-refinementverification methods into a platform-baseddesign flow.At the booth, COCONUT partners present theproject main flow, demo of tools, andrelevant results.

Compaan Design develops technology forhotspot parallelization of legacy/certified ISOC applications. It offers innovative productsthat reliably compile and scale to state-of-the-art silicon with billions of transistors suchas x86 multicore, MPSoC and FPGA.The Compaan Design workflow guides step-by-step parallelization towards improved energyefficiency and computational throughput.Parallelism is exploited for streaming dataand increased architecture utilization. Exactdataflow analysis guarantees correctness androbustness of application execution. Codegeneration is heterogeneous and supportsflexible HW/SW codesign.It is a perfect solution for today's MPSoCscomposed of DSPs, FPGAs andmicroprocessors. It easily retargets tocustomized processors and IP blocks.

PRODUCT FINDERASIC and SOC Design:Design EntryBehavioural Modelling & Simulation System-Level Design:Behavioural Modelling & AnalysisHardware/Software Co-Design Test:System Test Services:Design ConsultancyPrototyping Embedded Software Development:Software/Modelling Hardware:Development Boards

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CMPContact: Bernard Courtois46 avenue Felix Viallet38031 GrenobleFranceTel: +33 476574617Fax: +33 476473814E-Mail: [email protected]: http://cmp.imag.fr

PRODUCT FINDERServices:PrototypingFoundry & Manufacturing

stand EP10

COCONUT EU project Contact: Graziano PravadelliDipartimento di Informatica - Università di VeronaStrada le Grazie 15, 37134 Verona, ItalyTel: +39 045 8027081Fax: +39 045 8027068E-Mail: [email protected]: www.coconut-project.eu

PRODUCT FINDERASIC and SOC Design:Behavioural Modelling & SimulationVerification System-Level Design:Behavioural Modelling & AnalysisHardware/Software Co-Design

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Compaan Design BV Contact: John van Brummen De Ruyterkade 1131011 AB AmsterdamThe NetherlandsTel: +31 20 5216686Fax: +31 20 6750389 E-Mail: [email protected] Website: www.compaandesign.com

PRODUCT FINDERSystem-Level Design:Acceleration & EmulationHardware/Software Co-Design Embedded Software Development:CompilersSoftware/Modelling Hardware:FPGA & Reconfigurable Platforms Semiconductor IP:Embedded FPGA Application-Specific IP:Data CommunicationDigital Signal ProcessingTelecommunication

OPENING PLENARYBiologically-inspired massively-

parallel architectures – computingbeyond a million processors

S Furber, ICL Professor of Computer Engineering,

School of Computer Science, Manchester U, UK

How technology R&D leadership brings a competitive advantage in

the fields of multimedia convergenceand power applications

Philippe Magarshack, Group Vice-President, Technology R&D - General Manager, Central CAD and DesignSolutions, STMicroelectronics, France



The primary objective of the COMPLEX (COdesingand power Management in PLatform-based designspace EXploration) European Integrated Project isto develop an innovative, highly efficient andproductive design methodology and a holisticframework for iteratively exploring the designspace of embedded HW/SW systems. COMPLEX willfocus on early, fast yet accurate platform-baseddesign space exploration at the system level.The COMPLEX consortium develops a new designenvironment for platform-based design-spaceexploration offering developers of next-generationmobile embedded systems a highly efficient designmethodology and tool chain. The integratedenvironment allows iterative exploration andrefinement of advanced applications to meetmarket requirements. The design technology inparticular enables fast simulation and assessmentof the platform at Electronic System Level (ESL)with up to bus-cycle accuracy at the earliestinstant in the design cycle.Partners: OFFIS (DE), STMicroelectronics (IT),STMicroelectronics (CN), ThalesCommunications (FR), GMV (ES), Synopsys(BE), ChipVision (DE), EDALab (IT), MagillemDesign Services (FR), Politecnico di Milano(IT), Universidad de Cantabria (ES), Politecnicodi Torino (IT), IMEC (BE), ECSI (FR)

Concept Engineering develops and marketsinnovative visualization and debuggingtechnology for commercial EDA vendors, in-house CAD tool developers, FPGA and IC designers.Nlview WidgetsTM – a family of schematicgeneration and visualization engines (Tcl/TK,MFC, Qt, Java, Perl/Tk, wxWidgets) that canbe easily integrated into EDA tools.RTLVisionTM PRO – a graphical debugger forSystemsVerilog, Verilog and VHDL based designs.GateVision® PRO – a customizable debuggerfor Verilog, LEF/DEF andEDIF based designs.SpiceVision® PRO – a customizable debuggerfor SPICE based designs.SGvisionTM PRO – a customizable mixed-modedebugger (SPICE and Verilog).

Cortus is the technology leader in ultra lowpower, compact 32-bit microcontroller IPcores. The APS3 combines a powerconsumption of 22 µW/DMIPS (TSMC 130 nm)with processing power similar to an ARM9.Yet the core itself is no larger than the 8051– making it a natural upgrade choice for 8-bit/16-bit core users – and is the smallestavailable core capable of running µCLinux.Microprocessor Report crowned the APS3 the“King of Lilliput”.Software development with C/C++ issupported by a complete toolchain and

Eclipse-based IDE. A rich ecosystem ofdevelopment tools and RTOS is available.A building block approach ensures that theAPS3 is an ideal processor for a very widerange of requirements spanning low end, ultralow cost applications to high end, multi-coresystems with multiple coherent caches.The core is well proven in many high volumeapplications in technologies ranging from32nm to 180nm.

CréVinn is a leading Silicon System DesignConsultancy company, with Design Centres inGalway and Dublin, Ireland. We work with keypartners to develop innovative technology inthe networking, computing, automotive andindustrial markets. In addition, we are engagedin Silicon IP Core and Product Development inthe networking and storage fields.

PRODUCT FINDERASIC and SOC Design:Design EntryBehavioural Modelling & SimulationPower & Optimisation System-Level Design:Behavioural Modelling & AnalysisHardware/Software Co-Design Embedded Software Development:CompilersReal Time Operating SystemsSoftware/Modelling

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Concept Engineering GmbH Contact: Gerhard AngstBoetzinger Str. 2979111 FreiburgGermanyTel: +49 761 470940Fax: +49 761 4709429E-Mail: [email protected]: www.concept.de

PRODUCT FINDERASIC and SOC Design:VerificationAnalogue and Mixed-Signal Design Test:Mixed-Signal Test

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Cortus S.AContact: [email protected] S.A.Le Génésis97 rue de Freyr34000 MontpellierFranceTel: +44 1264 369483Fax: +44 1264 369483E-Mail: [email protected]: www.cortus.com

Contact: Adam MorawiecECSI, Electronic Chips & Systems designInitiativeParc Equation2 avenue de Vignate38610 GièresFranceOFFIS e.V.Escherweg 2Oldenburg26131GermanyTelephone:+49 441 97 22 0Tel: ECSI +33 476 63 4934Fax: ECSI +33 958 08 2413E-Mail: [email protected]: http://complex.offis.de/

PRODUCT FINDERServices:PrototypingTraining Embedded Software Development:CompilersDebuggersSoftware/Modelling Semiconductor IP:Analogue & Mixed Signal IPCPUs & ControllersEncryption IPPhysical LibrariesProcessor Platforms Application-Specific IP:Analogue & Mixed Signal IPDigital Signal ProcessingSecurityWireless Communication

stand EP16

COMPLEX - COdesing andpower Management inPLatform-based designspace EXploration

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CréVinn Contact: Tadhg CreedonCréVinn TeorantaManor HouseBaile an tSagairtAn SpidealIrelandTel: +353 91-558090Fax: +353-91-558060E-Mail: [email protected] Website: www.crevinn.com



CST develops and markets high performancesoftware for the simulation ofelectromagnetic fields in all frequency bands.Its products allow you to characterize, designand optimize electromagnetic devices allbefore going into the lab or measurementchamber. This can help save substantial costsespecially for new or cutting edge products,and also reduces design risk and improvesoverall performance and profitability.Its success is based on the implementation ofleading edge technology in a user-friendlyinterface. Furthermore, CST’s “completetechnology” complements its market andtechnology leading time domain solver (CSTMICROWAVE STUDIO®), thus offeringunparalleled speed, accuracy and versatilityfor all applications.CST’s customers operate in industries asdiverse as Telecommunications, Defense,Automotive, Electronics, and MedicalEquipment, and include market leaders suchas IBM, Intel, Mitsubishi, Samsung, andSiemens. CST markets its products worldwidethrough a network of distribution and supportcenters which also provide comprehensivecustomer support and training.More information at http://www.cst.com.

DeFacTo enables designers to completeplanning, analysis and implementation ofintegrated circuit test logic before synthesisby delivering a high quality suite of DFT toolsworking at the register transfer level (RTL).

Are you looking for a complete ASIC supplychain solution? DELTA Microelectronics is the European leaderin providing the semiconductor industry. We

give our customers a competitive edge inbringing products to market quickly andenabling a predictable path from ICdevelopment via testing and mass production. We offer supply chain management consisting ofASIC development, fabrication, packaging,testing, storage and shipping of ICs - to helpaddress the key challenges fabless IC vendors’face today, from prototypes to mass production. Semiconductor vendors achieve faster time-to-market of smaller, more robust, more profitablesemiconductor products by utilising DELTA’sturn-key solutions and professional services.DELTA’s experienced ASIC design team isspecialised in payment systems, RFID, sensorinterfaces and opto chips.Flexibility, quality and competitiveness –DELTA offers solutions at any part of the ASICdevelopment and production process to allowthe customer to get the most cost effectivecombination of services. Get access to European and Far Eastern waferand packaging facilities via DELTA’s volumepurchasing power to obtain the best possible prices.DELTA is established 70 years ago and isheadquartered in Copenhagen, Denmark.

DEFACTO TECHNOLOGIES Contact: Chouki Aktouf167 Rue De Mayoussard38430 MoiransFranceTel: +33 476 668330Fax: +33 476 910067E-Mail: [email protected]: www.defactotech.com

PRODUCT FINDERTest:Design for TestTest Automation (ATPG, BIST) Services:IP e-commerce & Exchange Semiconductor IP:Test IP

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DELTAContact: Mette Brunbjerg OlesenVenlighedsvej 42970 HoersholmDenmarkTel: +45 721 94000Fax: +45 721 94001E-Mail: [email protected]: www.asic.madebydelta.com

PRODUCT FINDERASIC and SOC Design:Behavioural Modelling & SimulationVerification System-Level Design:Behavioural Modelling & Analysis Services:Design ConsultancyPrototyping Application-Specific IP:Data CommunicationDigital Signal ProcessingNetworkingSecurityTelecommunicationWireless Communication

stand 25

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CST Computer SimulationTechnology AGContact: Jerome MolletBad Nauheimer Str. 1964289 DarmstadtGermanyTel: +49 6151 7303 0Fax: +49 6151 7303 100E-Mail: [email protected]: www.cst.com

PRODUCT FINDERASIC and SOC Design:Design EntryBehavioural Modelling & SimulationSynthesisPhysical Analysis (Timing, Themal, Signal)VerificationAnalogue and Mixed-Signal DesignMEMS DesignRF Design System-Level Design:Behavioural Modelling & AnalysisPhysical AnalysisPackage DesignPCB & MCM Design Test:Design for Test Embedded Software Development:Software/Modelling

PRODUCT FINDERASIC and SOC Design:Design EntryBehavioural Modelling & SimulationSynthesisPower & OptimisationPhysical Analysis (Timing, Themal, Signal)VerificationAnalogue and Mixed-Signal Design System-Level Design:Behavioural Modelling & AnalysisPackage Design Test:Design for TestDesign for Manufacture and YieldLogic AnalysisTest Automation (ATPG, BIST)Boundary ScanSilicon ValidationMixed-Signal TestSystem Test Services:Design ConsultancyPrototypingFoundry & Manufacturing Hardware:FPGA & Reconfigurable Platforms Application-Specific IP:Analogue & Mixed Signal IPData CommunicationDigital Signal ProcessingSecurityTelecommunicationWireless Communication



The Design Automation Conference (DAC) isthe world’s leading technical conference andtradeshow on electronic design and designautomation. DAC is where the IC Design andEDA ecosystem learns, networks, andconducts business. DAC features hundredstechnical sessions, panels, keynotes,tutorials, workshops and events covering thelatest in design methodologies, embeddedsoftware and systems and EDA tooldevelopments. The exhibition offers boothsand suites from over 200 of the leading EDA,silicon, IP, embedded and design servicesproviders. 48th Design AutomationConference, June 5-10, 2011 in San Diego, CA

DOCEA Power develops and markets system-level tools for modeling and optimizingpower/thermal behavior of whole electronicssystems. DOCEA's Aceplorer softwareintegrates a consistent power datamanagement methodology for capturing andsimulating power behavior. The "separation ofconcerns" approach makes power modelsusable across the teams and the design flowfrom system level to silicon measurements.The Aceplorer innovative platform is thesolution for early power estimation,architecture exploration, use case profiling,package selection and other technologychoices that impact specification. Dealing withpower and/or thermal issues with Aceplorer atsystem level is fast, secure and efficient.As a service, DOCEA Power generates SPICE-compliant compact thermal models of ICs,SoCs, SiPs or on-board systems. Dynamicthermal simulations get ultra-fast, whileaccuracy is kept under control.

DOCEA technology has been adopted byworld's largest semiconductor companies.

Duolog Technologies is a pioneeringdeveloper of EDA tools that enable the rapidintegration of today's increasingly complexSoC, ASIC and FPGA designs. Duolog’sSocrates platform is a hub for chipintegration from IP register to Chip pin. Itallows the capture of standardized views ofIP-level and chip-level designs, validates thedata to ensure correctness and generatessource views for different teams, includinghardware and software views, design andverification views, ESL and implementationviews. Socrates supports current andemerging standards such as IP-XACT, RAL,OVM and UVM. Socrates is deliveringsignificant productivity improvements toDuolog’s customers including enhanced inter-team communication, extensive bugelimination and major design cyclereductions. Founded in 1999, DuologTechnologies is headquartered in Dublin,Ireland with development centres in Galway,Ireland and Budapest, Hungary. Duolog alsohas sales and support offices across Europe,US and Asia.

Strong of our experience in IC, electronicsand software services, we develop solutionsfor radiation tests (ASER) and validation(EASii-Board).We also deliver EDA expert services and EDA solutions.ASER:Soft Error Test service is a complete solutionto radiation effects characterization of space,automotive or consumer products around the world.EASii-Board:A low cost logical pattern generator andanalyzer bridging the gap between design andvalidation, allowing you to build easy andefficient validation platforms.EDA Solutions: - Be-Spice: Your browser and visualizer forspice netlists and backannotated simulationresults.- IDesignSpec (Agnisys): Register Automationand Management allowing easy design andverification automation of register features.- IVerifySpec (Agnisys): Presents a completestatus of the verification project. It alsoprovides a collaborative tool for distributedverification teams that improves productivityand quality. EDA Services:State of the art methodology consulting, IPand VIP development on partner tools:Agnisys, Breker, Jasper, Mentor.On-Demand EDA support.

Contact: Fearghal HannawayConcourse Building (5th Floor)Beacon CourtSandyfordDublin 18IrelandTel: +353 1 2178425E-Mail: [email protected]: www.duolog.com

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DOCEA Power Contact: Ridha HAMZA, Marketing and Sales Director166 B Rue du Rocher de Lorzier38430 MoiransFRANCETel: +33 0 427 85 82 62Fax: +33 0 488 68 11 22E-Mail: [email protected]: www.doceapower.com

PRODUCT FINDERASIC and SOC Design:Power & Optimisation System-Level Design:Behavioural Modelling & Analysis Test:System Test Services:Training Embedded Software Development:Software/Modelling

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Duolog Technologies Ltd

Design AutomationConference (DAC) Contact: Susie HornMP Associates1721 Boxelder Street, #107Louisville, CO 80027Tel: +1 303 530-4333Fax: +1 303 530-4334E-Mail: [email protected]: www.dac.com

PRODUCT FINDERASIC and SOC Design:Design EntrySynthesisVerification System-Level Design:Hardware/Software Co-Design Test:Design for TestBoundary Scan Services:Design ConsultancyData Management and Collaboration Semiconductor IP:Test IPVerification IO

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EASii-IC Contact: Francois CERISIER90, avenue Léon BlumBP 261238036 Grenoble Cedex 2FRANCETel: +33 4 56 580 580Fax: +33 4 56 580 599E-Mail: [email protected]: www.easii-ic.com

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SPECIAL FOCUSDAY

SMART ENERGY AT STKEYNOTE – Thursday, March 17th, 13.30

Carmelo Papa, Executive VP Industrial andMultisegment, STMicroelectronics, IT



EDA is a commercial-free publicationproviding a quiet place for conversationabout the Electronic Design Automationindustry and its companion technologies. Thecoverage does not intend to becomprehensive, but does intend to providesome food for thought. To that end, EDAConfidential includes "Recipes", FreddySantamaria's "Gourmet Corner", as well as"Voices" of other contributing authors, "Offthe Record" op-ed pieces, and "Conference"coverage.

EDALab is a business reality located inVerona, in the north of Italy, which addressesissues of technological innovation in thefield of networked embedded systems.

It has a workforce of about 15 peopleincluding partners, employees and externalcollaborators, united by a common passionfor IT and emerging technologies.The young age and the personal motivationare at the base of the company's success inbeing proactive and flexible.Our activity is focused on embedded systemdesign both from the research point ofview and from a production standpoint. Thecoexistence of these two souls is part of theEDALab mission, which serves as innovationdriver for its customers. Related links: HIFSuite Tools ->http://hifsuite.edalab.it

EDXACT proposes software that helps tosubstantially raise the efficiency of postlayoutsimulation and analysis flows.Current offerings include:JIVARO - netlist reduction platform,integrated into any design flow, severalinterfaces, many references.Used in production for memory, mixed-signal,analog, RF flows. Timing. Speeding upsimulation time, increasing accuracy, reducingmemory footprint. Industry-leading netlistreduction.COMANCHE - parasitics analysis platform.Allows to quickly analyze interconnectparasitics in order to pinpoint problems.Allows to estimate timing, accurately

compare different extracted netlists.Several interfaces.

ElectroniqueS the reference monthly fordecision makers and engineers in theelectronics sectorCirculation of 10,000 copieswww.electroniques.biz, the electronicprofessional’s web siteDaily Newsletter, the day’s essential newsabout our industry’s major sectorsSent to more than 26,000 free subscribersWeekly newsletter, the newsletter thatsummarizes the previous 5 daily newslettersmain topicSent to more than 23,000 free subscribersVertical newsletter, 3 subjects: Automotive /Mil-Aero / Medical5 mailings a year (each 2 in 3 months)

Chipright, Crevinn Teoranta, Duolog , Silansysand Tyndall are all members MIDAS Ireland.Enterprise Ireland is the governmentorganisation responsible for the developmentand growth of Irish enterprises in worldmarkets. It works in partnership with Irishenterprises to help them start, grow, innovateand win export sales on global markets.MIDAS Ireland (Microelectronic IndustryDesign Association) is a national clusterconsisting of microelectronics designcompanies and third level institutions inIreland. The membership currently consists of7 multinational companies, 18 indigenouscompanies and 17 academic membersrepresenting all the courses in Ireland thatproduce electronic engineering graduates. Itsaim is to promote the growth of

PRODUCT FINDERASIC and SOC Design:Behavioural Modelling & SimulationVerification System-Level Design:Behavioural Modelling & AnalysisHardware/Software Co-Design Test:Logic AnalysisTest Automation (ATPG, BIST)System Test Services:Prototyping Embedded Software Development:CompilersReal Time Operating SystemsSoftware/Modelling Application-Specific IP:Data CommunicationNetworkingTelecommunicationWireless Communication

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PRODUCT FINDERASIC and SOC Design:Physical Analysis (Timing, Themal, Signal)VerificationAnalogue and Mixed-Signal DesignRF Design

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edXact Contact: Delphine BillonParc Work Center - Bât ARoute des Bois38500 Voiron – FranceTel: +33 0 4 76 66 89 80Fax: +33 0 4 76 67 36 99E-Mail: [email protected]: www.edxact.com

ElectroniqueS Contact: Daniel HaussmanTel: +33 01 71 18 54 40 Fax: +33 01 71 18 53 01E-Mail: [email protected]: www.electroniques.biz

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EDALab Contact: Walter VendraminettoStrada Le Grazie, 1537134 - Verona (VR)ITALYTel: +39 045 8027062Fax: +39 045 8027062E-Mail: [email protected]: www.edalab.it

PRODUCT FINDERASIC and SOC Design:Design EntryVerificationAnalogue and Mixed-Signal Design System-Level Design:Physical Analysis Test:Silicon ValidationSystem Test Services:Design ConsultancyPrototypingData Management and CollaborationTraining Hardware:FPGA & Reconfigurable PlatformsDevelopment Boards Semiconductor IP:Analogue & Mixed Signal IP Application-Specific IP:Analogue & Mixed Signal IP

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EDA Confidential Contact: Peggy AycinenaSan Mateo, CA94402-2241U.S.A.Tel: +1 650 579 7952Fax: +1 650 579 7952E-Mail: [email protected]: www.aycinena.com

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Enterprise Ireland Contact: Paul McCloskeyEnterprise Ireland, Industry House, RossaAvenue, Bishopstown, CorkTel: +353 21 4800227Fax: +353 21 4800271 E-Mail: [email protected] Website: www.enterprise-ireland.com



microelectronics in Ireland throughcollaboration in research, training andeducation. Enterprise Ireland is an associatemember of MIDAS.

The EUROPRACTICE IC service offers low costand easy access to ASIC prototype and smallvolume fabrication.The service is offered by IMEC (B) andFhG/IIS (D).Low cost prototyping is achieved by offeringfabrication through regularly scheduled MPW(Multi Project Wafer) runs whereby manydesigns from different customers are mergedonto the same fabrication run. These runs arefabricated in industrial CMOS, BiCMOS andSiGe processes from 0.7µ to 40nm at well-known foundries (ONSemi,austriamicrosystems, IHP, LFoundry, TSMC,UMC). A total integrated design andmanufacturing flow is offered including celllibrary and design kit access and support,deep submicron netlist-to-layout, ASICprototyping on MPW or dedicated singleproject prototype runs, volume fabrication,qualification, assembly and test. Volumefabrication starts with wafer batches as lowas 12 wafers but can go up to more than5000 wafers per year per ASIC.

The scope of Fractal Technologies is to checkconsistency and validate all differentdataformats used in your design andsubsequently improve the Quality of yourStandard Cell Libraries, IO’s and IP’sFRACTAL TECHNOLOGIES Your partner to: check consistency andvalidate all different dataformats andsubsequently improve the Quality of yourStandard Cell Libraries, IO’s and IP’s

GLOBALFOUNDRIES is the world's first full-service semiconductor foundry with a trulyglobal manufacturing and technologyfootprint. Launched in March 2009 through apartnership between AMD [NYSE: AMD] andthe Advanced Technology InvestmentCompany (ATIC), GLOBALFOUNDRIES providesa unique combination of advancedtechnology, manufacturing excellence andglobal operations. With the integration ofChartered in January 2010, GLOBALFOUNDRIESsignificantly expanded its capacity and abilityto provide best-in-class foundry services frommainstream to the leading edge.GLOBALFOUNDRIES is headquartered in SiliconValley with manufacturing operations inSingapore, Germany, and a new leading-edgefab under construction in Saratoga County,New York. These sites are supported by aglobal network of R&D, design enablement,and customer support in Singapore, China,Taiwan, Japan, the United States, Germany,and the United Kingdom.For more information on GLOBALFOUNDRIES,visit http://www.globalfoundries.com.

Gold Standard Simulations (GSS) is the worldleader in the simulation of statistical variabilityin nano-CMOS devices. The services we offerinclude the physical simulation of statisticalvariability, statistical compact model extractionand statistical circuit simulation using ‘pushbutton’ cluster-based technology.

HiPEAC is a Network of Excellence on HighPerformance and Embedded Architecture andCompilation. It gathers over 150 leadingEuropean academic and industrial computing-system researchers in one virtual center ofexcellence with the aim of coordinating theirresearch, improving their mobility andcollaborations, increasing their visibility. Thenetwork consists of nine research clustersthat look into on-chip multi-cores technologyand customisation, leading to heterogeneousmulti-core systems. HiPEAC organizes severallarge networking events in Europe: theACACES Summer school, Computing SystemsWeeks (those are co-located with industrialworkshops), the HiPEAC conference.Additionally HiPEAC journals, newsletters androadmaps are published on the regular basis.

PRODUCT FINDERASIC and SOC Design:SynthesisPower & OptimisationPhysical Analysis (Timing, Themal, Signal)VerificationTest:Design for TestTest Automation (ATPG, BIST)Boundary ScanMixed-Signal TestSystem Test Services:PrototypingFoundry & ManufacturingSemiconductor IP:Physical Libraries

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Fractal Technologies Contact: Rene DonkersUS office, San Carlos, California, USAEurope Office, Eindhoven, the NetherlandsTel: +31 641539004Fax: +31 847503816E-Mail: [email protected]: www.fract-tech.com

PRODUCT FINDERASIC and SOC Design:Design EntryVerification Services:Design Consultancy

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Gold Standard Simulations Ltd

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GLOBALFOUNDRIES Contact: Simone WurmDresden GermanyTel: +49 - 351 - 277 1018Fax: +49 - 351 - 277 91018E-Mail: [email protected]: www.globalfoundries.com

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EUROPRACTICE Contact: Carl DasKapeldreef 75B-3001 HeverleeBelgiumTel: +32 16 281 248Fax: +32 16 281 584E-Mail: [email protected]: www.europractice-ic.com

Contact: Campbell MillarThe Rankine Building,Oakfield Avenue,Glasgow,G12 8LTUKTel: +44 141 330 4790Fax: +44 141 330 4907E-Mail: [email protected]: www.goldstandardsimulations.com

PRODUCT FINDERASIC and SOC Design:Power & OptimisationPhysical Analysis (Timing, Themal, Signal) Services:TrainingEmbedded Software Development:Software/Modelling

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HiPEAC NoE Contact: Koen De BosschereUniversiteit GENT - ELIS,9000 GENT, BELGIUMTel: +32 9 264 42 58Fax: +32 9 264 35 94E-Mail: [email protected]: www.hipeac.net



About InfiniscaleVariation-aware risk management solutionsInfiniscale provides a unique variation-awarecustom IC design solutions dedicated toanalysis and optimization of performancesand parametric yield for analog and mixed-signal designs. Infiniscale Lysis flow enablesvariation-aware design methods that canaccurately and promptly estimate the risksinto variation sensitive devices. Then Lysiscan help the designer reducing or possiblyremoving these risks.With Lysis, the designer is able to run amillion MC in seconds, to visualize PVTinfluence on performances in real-time, andto optimize parametric yield in an hour.Lysis innovative approach to variation-awaredesign is compatible with all the existingdesign flows, and fully integrated with theindustry-leading EDA tools. Infiniscale workswith several major semiconductor companies

in the area of power management, memoriesand mixed-signal designs.Infiniscale’s solutions enable designersdelivering products on time, while maximizingrobustness and yield.

Infotech Enterprises provides leading-edgeengineering solutions to major organizationsworldwide. With Global Headquarters inHyderabad, India, Infotech has 8,000+engineers across 30 global locations and hasgenerated consolidated revenues of US $201Million for the fiscal year ending March 2010.Infotech provides concept to silicon andsystem prototype solutions forASIC/FPGA Engineering and EmbeddedSoftware Development. With over 12 yearsimpeccable track record of "first-pass siliconsuccess" and "on-timedelivery" across 200+ ASIC tapeouts, we notonly help our customers meettheir current design requirements, but alsoprovide technology road maps andinnovative solutions for future design trends.Primary Service Offerings:•ASIC and SOC Design•Embedded Software Design•FPGA & Board DesignKey Highlights:•12 years track record of “first pass siliconsuccess” across 200+ ASICtapeouts•Delivery center based out of San Jose, U.S. :Access to high-endelectronics talent from the Silicon Valley•Expertise in technology nodes down to28nm and as many as 100 million gates•Deep understanding of ARM/MIPS/PowerPC-based SOCs with a strong grasp ofmemory and connectivity technologies•Extensive background in multimedia (audio,video, speech and image) codecsstandards and frameworks

IP - SoC 2011 will be the 20th edition of theworking conference on hot topics in thedesign world, focusing for the past 9 years onIP-based SoC design and held inGrenoble,organized by Design And Reuse .Over the years, IPs have become Subsystemsor Platforms and thus as a natural applicativeextension.IP-SoC will definitively include astrong Embedded Systems track addressing acontinuous technical spectrum from IP to SoCto Embedded System.

The main goal of the project is to defineinnovative methodologies for system-leveldesign, able to guide designers andresearchers to the optimal composition ofembedded MPSoC architecture, according tothe requirements and the features of a giventarget application field. The proposedapproach will tackle the new challenges,

PRODUCT FINDERASIC and SOC Design:Behavioural Modelling & Simulation

Contact: Stephane FIORILLO186 chemin de l'étoile38330 MontbonnotFrance Tel: +33 04 76 51 25 27Fax: +33 04 76 51 20 46E-Mail: [email protected]: www.infiniscale.com

PRODUCT FINDERASIC and SOC Design:Behavioural Modelling & SimulationPower & OptimisationPhysical Analysis (Timing, Themal, Signal)Verification System-Level Design:Behavioural Modelling & AnalysisPhysical AnalysisAcceleration & EmulationHardware/Software Co-Design Test:Test Automation (ATPG, BIST) Services:Data Management and Collaboration Embedded Software Development:CompilersReal Time Operating SystemsDebuggersSoftware/Modelling Hardware:FPGA & Reconfigurable Platforms Semiconductor IP:Embedded FPGAEmbedded Software IPOn-Chip Bus Interconnect Application-Specific IP:Digital Signal ProcessingMultimedia GraphicsNetworkingTelecommunicationWireless Communication

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INFINISCALE

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Infotech Contact: Abilash Reddy GaddamInfotech Enterprises GmbHMollenbachstraße 3771229 LeonbergGermanyTel: +49 (0) 7152 9452-0Fax: +49 (0) 7152 9452-90 E-Mail: [email protected]: www.infotech-enterprises.com

PRODUCT FINDERASIC and SOC Design:Design EntryBehavioural Modelling & SimulationSynthesisPower & OptimisationPhysical Analysis (Timing, Themal, Signal)VerificationAnalogue and Mixed-Signal Design Services:Design Consultancy Embedded Software Development:Real Time Operating Systems Hardware:FPGA & Reconfigurable PlatformsDevelopment Boards

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IP SOC 11 Contact: Gabriele SaucierIP SOC 11Design And Reuse SA12 rue Ampere38016 GrenobleFRANCETel: +33 476 21 31 02Fax: +33 476 49 00 52E-Mail: [email protected]: www.design-reuse.com

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MADNESS Contact: Prof. Luigi RaffoDIEE - Department of Electric and ElectronicEngineeringUniversity of CagliariPiazza d'Armi - 09123 CAGLIARI (Italy)Tel: +390706755765Fax: +390706755782 E-Mail: [email protected]: www.madnessproject.org



related to both architecture and designmethodologies, arising with the technologyscaling, the system reliability and the ever-growing computational needs of modernapplications.The proposed methodologies will extend theclassic concept of design space explorationto:* Improve design predictability, bridging theso called "implementation gap", i.e. the gapbetween the results that can be predictedduring the system-level design phase andthose eventually obtained after the on-siliconimplementation.* Consider, in addition to traditional metrics(such as cost, performance and powerconsumption), continued availability ofservice, taking into account fault resilience asone of the optimization factors to be satisfied.* Support adaptive runtime management ofthe architecture, considering, while tailoringthe architecture, new metrics posed by noveldynamic strategies and advanced support forcommunication issues that will be defined.

Magillem provides to customers in theelectronic industry tools and services thatdrastically reduce the global cost of complexdesign.Magillem has developed an easy to use, stateof the art platform solution to coverelectronic systems design flow challenges in acontext where complexity, interoperabilityand design re-use are becoming critical issuesto manage design cycle time of SOC. Mainbenefits include:* Maximizing Design and IP Re-use* Using a virtual platform to configure theirsystem and IPs* Controlling the Design Flow* Exploring their Design Flow architectureand optimizing it* Improving their independence from CADtools vendors* Improving interoperability, communication* Benefiting from better user interfaces toraise productivity* Relying on worldwide adopted standardsOur Motto:Methodology tools should adapt to the trendsin SoC design and help streamline the designflows without disrupting existing processes

Micrologic interactive nanoToolBox solutionsaccelerate the signoff of complex deepnanometer designs with:· Faster time to market· Improved performance· Enhanced reliability· Lower costsMicrologic's nanoToolBox is a plugin suite oftools for Virtuoso™, consisting ofcomplementary Design Rule Verification(DRC), Reliability Verification (RV) and LayoutVersus Schematic (LVS) checkers. Permanentlyon watch, these programs check, inform andguide the layout process, allowing you toconverge to a signoff-ready layout in theminimum possible time.

MIDAS Ireland (Microelectronic IndustryDesign Association) is a national clusterconsisting of microelectronics designcompanies and third level institutions inIreland. The membership currently consists of7 multinational companies, 18 indigenouscompanies and 17 academic membersrepresenting all the courses in Ireland thatproduce electronic engineering graduates. Itsaim is to promote the growth ofmicroelectronics in Ireland throughcollaboration in research, training andeducation. Enterprise Ireland is an associatemember of MIDAS.

AEPI is the economic development agency forGrenoble-Isere/France, and providescomplimentary information and services tocompanies exploring business opportunities.The Grenoble area, smart valley insoutheastern France, is Europe’s top center inmicro-nanotechnologies and derivedapplications, with the whole food chain ofthe Industry being represented in the area,from EDA to design, component makers,equipment suppliers and end users. AEPI isalso a member of the local board of the newSemi Europe Grenoble office, located on theMinatec Campus.Global competitive cluster Minalogic fostersresearch-led innovation in intelligentminiaturized products and solutions forindustry. Located in Grenoble, France, thecluster channels in a single physical locationa range of highly-specialized skills andresources from knowledge creation to thedevelopment and production of intelligent

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Magillem Design Services Contact: Lamia Lakehal4, rue de la Pierre Levée75011Paris FranceTel: +33 0 1 40 21 35 50 Fax: +33 0 1 53 36 75 08E-Mail: [email protected]: www.magillem.com

PRODUCT FINDERASIC and SOC Design:Design EntryPower & OptimisationPhysical Analysis (Timing, Themal, Signal)VerificationAnalogue and Mixed-Signal Design System-Level Design:Hardware/Software Co-DesignPackage Design Services:Design ConsultancyData Management and CollaborationTraining Semiconductor IP:Memory IP

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MICROLOGIC DesignAutomation Contact: Christophe Bianchi157 Yaffo StreetAMOT BuildingHaifa 35251IsraelTel: +972-4-8538835Fax: +972-4-8527785E-Mail: [email protected]: www.micrologic-da.com

PRODUCT FINDERASIC and SOC Design:Physical Analysis (Timing, Themal, Signal)Verification

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MIDASContact: Paul McCloskeyEnterprise Ireland, Industry House, RossaAvenue, Bishopstown, CorkTel: +353 21 4800227Fax: +353 21 4800271 E-Mail: [email protected] Website: www.enterprise-ireland.com

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MINALOGIC GRENOBLEISERE Contact: Véronique PequignatGrenoble Isere - AEPI, 1 Place FirminGautier 38027 GrenobleMinalogic: Maison des Micro etNanotechnologies,3 Parvis Louis Néel 38054GrenobleFranceTel: +33 04 76 70 97 04Fax: +33 04 76 70 97 19E-Mail: [email protected]: www.grenoble-isere.com/www.minalogic.com



miniaturized services for industry. Thetechnologies developed at the cluster areapplicable to all business sectors :healthcare, energy efficiency, mobility,imagery, including more traditional industries.Minalogic brings together major corporations,small and mid-sized businesses, governmentagencies, and organizations from the publicand private sectors.

MOSIS offer low cost and low volume accessto a wide range of IC technologies from1.5um down to the latest 65nm processes.Our services include wafer fabrication andplastic assembly services, via the foundiresAMIS, austriamicrosystems, IBM and TSMC,and assembly house I2A.You can chose between low cost sharedaccess multi project wafer (MPW) runs,yielding up to hundreds of samples, ordedicated mask and wafer runs where highervolumes are required.With MOSIS there are no die size constraints,so you receive exactly what you need.MOSIS are represented in Europe by EDASolutions, who will be happy to explain moreto you about our services, and answer anyquestions you may have. Why not come toStand 35 or visit the EDA Solutions websitewww.eda-solutions.com for more details.

MunEDA provides leading EDA software

technology for analysis, modelling andoptimization of yield and performance ofanalog, mixed-signal and digital designs.MunEDA´s products and solutions enablecustomers to reduce the design times of theircircuits and to maximize robustness,reliability and yield. MunEDA´s solutions arein industrial use by leading semiconductorcompanies in the areas of communication,computer, memories, automotive, andconsumer electronics.

The Nano-Tera.ch program is a broadengineering program in Switzerland for healthand security of humans and the environment,currently funded by the Swiss government.The program rationale is rooted in advancesin engineering nano-scale materials and theirexploitation in a variety of systems, requiringextreme integration and coordinated controlof diverse micro/nano-scale components.Embodiments of such systems can be found inlightweight, mobile and personalized productsembedded in the environment and on/in thebody. These products will enable us, forexample, to detect in real time differenthealth risks and conditions throughintegrated bio probing, to reveal securityrisks through smart buildings andenvironments, to save energy throughambient sensing, and to detect and monitorenvironmental hazards such as floods andavalanches from space and/or inaccessiblepositions on earth. The outstanding noveltyand power of these systems stem from theirconnectedness and the integration ofheterogeneous components.

nSilition is a leader in the development andthe qualification of industrial quality, veryhigh performance, low power A/D and D/A

converter IP cores with resolutions of up to16 bits. These converters are available asready-to-use semiconductor hard macros formost popular silicon processes.Our design team has many years of hands-onindustrial Analog and Mixed-Signal IC designexperience. We will support you through thewhole integration and product validation phase. nSilition also provides all other requiredAnalog and Mixed-Signal IP and IC designservices: from financial and technicalfeasibility studies up to characterizationtests, production validation and yieldimprovement.nSilition services several main customersactive in applications area like wirelinecommunication, industrial, medical andaerospace.We invite you to visit our booth for moredetails.

N.S. Mangat & Company, is the leadingtechnical conference and Exhibition ofSystem design, modeling and designautomation in worldwide. And N.S.M isinstitute of Tasting Quality & Maintenanacewas founded in 1993 and is 100% privatelyowned. The company is managed by an

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MOSIS Contact: Lynne WrightEDA Solutions LimitedUnit A5, Segengworth Business CentreSegensworth RoadFarehamHants PO15 5RQUnited KingdomTel: +44 1489 564 253Fax: +44 01489 557 367E-Mail: [email protected]: www.eda-solutions.com

PRODUCT FINDERServices:PrototypingFoundry & Manufacturing Semiconductor IP:Physical Libraries

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MunEDA Contact: Jin QiuStefan-George-Ring 2981929 MunichTel: +49 89 930 86 330Fax: +49 89 930 86 407E-Mail: [email protected]: www.muneda.com

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Nano-Tera.ch Contact: Patrick MayorNano-Tera.chEPFL / AAINF 332 Station 14CH-1015 LausanneTel: +41 21 693 81 66Fax: +41 21 693 81 60E-Mail: [email protected]: www.nano-tera.ch

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nSilition Contact: Thierry DelmotBoulevard Dolez, 317000 MonsBelgiumTel: +32-65-37.42.40Fax: +32-65-37.42.41E-Mail: [email protected]: www.nsilition.com

PRODUCT FINDERASIC and SOC Design:Design EntryBehavioural Modelling & SimulationVerificationAnalogue and Mixed-Signal Design System-Level Design:Behavioural Modelling & AnalysisPCB & MCM Design Test:Design for TestDesign for Manufacture and YieldSilicon ValidationMixed-Signal Test Services:Design ConsultancyPrototyping Hardware:Development Boards Semiconductor IP:Analogue & Mixed Signal IP Application-Specific IP:Analogue & Mixed Signal IPTelecommunication

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N S Mangat & CoContact: Mr. Ajit SinghN.S. Mangat & CompanyC 86 Hari NagarClock TowerNew Delhi 110064IndiaTel: +91 11 65175357Fax: +91 11 41694370E-Mail: [email protected]: www.nsmangat.com



international team of highest skilled expertsand is promoted by a group of qualified andexperienced professional that has wideexposure to various traits.

The NSM company has built up a reputationproviding prompt services and qualityassurance and in the same connection thecompany is always on a look out forinnovations in the domestic as well asinternational market.

Presto Engineering, an ISO 9001 company,delivers Design Success Analysis, integratedtest and product engineering solutions to IDMand fabless companies, helping to improvethe speed and predictability of new productreleases. Presto combines unique technicalexpertise, extensive industry experience andstate-of-the-art ATE for SoC and RF,reliability, failure analysis and fault isolationcapabilities to offer a complete productengineering solution designed to complementthe internal resources of its customers. Presto now offers it's product engineeringservices from two sites -- the Silicon Valleyhub in San Jose and the newly establishedlab in Normandy, France, after transfer fromNXP to Presto in 2010.Presto’s product-engineering services fromfirst silicon characterization to productionrelease include:• New product debug and failure analysis• ATE for digital and RF designs• e-Testing and characterization• Sample preparation• Reliability testingEngineering staff at Presto have extensiveindustry experience with:• In-silicon analysis docked with ATE• Backside silicon FIB and electrical failureanalysis for CSP and flip-chip packages• Dynamic analysis of leakage. interconnect,and timing• Scan-chain analysis and debug

ProximusDA provides solutions for System LevelDesign using a new computing paradigm toenable efficient development and use of today'smulti-processing compute capabilities. Thecompany’s "Proximus" development frameworkimplements transaction level based methodologyto specify, design, simulate and execute targetedparallel systems consisting of hardware andsoftware. ProximusDA delivers products forsystem architects, system validation engineersand embedded software developers. By providingan alternative to traditional serial hardware andsoftware design flows, Proximus shortens theembedded system development cycle andenables true system level optimization.

R3Logic, Inc. is a privately-held company,founded in 2000, specializing in the design of3D integrated circuits. Since 2001, workingwith DARPA-sponsored research programs, wehave developed a unique set of EDA tools for3D integrated circuit design and analysis,especially tools for true 3D integration andcustom design.R3Logic-France, sister-company to R3LogicInc. and located in Grenoble, France, wasestablished in 2008 following an invitation tojoin a European Consortium with STM andCEA-LETI. In the following year, R3LogicFrance created a common lab with CEA-LETIto research and develop new solutions for 3DIntegration and participate as one of themain players in the Grenoble 3D EDAecosystem.

• SAME’s Mission:Valorize, promote and develop excellence inthe microelectronics sector covering thedesign technology for advanced electroniccircuits in the South of France.• SAME Objective:- To organize the SAME Forum to promote themicroelectronic industry within the region.

PRODUCT FINDERASIC and SOC Design:RF Design System-Level Design:Package DesignPCB & MCM Design Test:Design for TestDesign for Manufacture and YieldBoundary ScanSilicon ValidationMixed-Signal TestSystem Test Services:Design ConsultancyPrototypingFoundry & Manufacturing

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Presto Engineering, Inc. Contact: Richard Curtin3907 North First StreetSan Jose, CA 95134Tel: - +1 408 434 1808Fax: - +1 408 434 6842E-Mail: [email protected]: www.presto-eng.com

PRODUCT FINDERASIC and SOC Design:Design Entry System-Level Design:Package Design Test:Design for Manufacture and Yield

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ProximusDA Contact: Philippe MetsuProximusDA GmbH Tuerkenstr. 71, Munich,80799, GermanyTel: +49 89 38157177-0Fax: +49 89 38157177-3E-Mail: [email protected]: www.proximusda.com

PRODUCT FINDERASIC and SOC Design:Design EntryBehavioural Modelling & SimulationVerification System-Level Design:Behavioural Modelling & AnalysisAcceleration & EmulationHardware/Software Co-Design Test:System Test Services:Design Consultancy Embedded Software Development:Real Time Operating SystemsDebuggersSoftware/Modelling Semiconductor IP:Embedded Software IP

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R3LOGICContact: Patrick BOTTIR3Logic FranceBHT-Minatec7 Parvis Louis Néel38000 GrenobleFranceR3Logic, Inc.19A Crosby DriveSuite 150Bedford, MA 01730USATel: +33 (0)9 77 72 10 22Fax: +1 781 276 7818E-Mail: [email protected]: www.r3logic.com

PRODUCT FINDERASIC and SOC Design:Design EntryMEMS DesignRF Design

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SAME Contact: Anne Claire DESNEULINC/o SKEMA60 Rue Dostoïevski -BP 08506902 Sophia Antipolis - FranceTel: +33 492 294 825Fax: +33 492 294 321E-Mail: [email protected]: www.same-conference.org



SPECIAL FOCUSDAY

WIRELESS INNOVATIONS FORSMARTPHONES

KEYNOTE – Wednesday, March 16th, 1400

Hannu Kauppinen, Director, Head of RadioSystems Laboratory,

Nokia Research Center, Finland

• SAME in Action:- SAME 2011 Forum: October 12 & 13, 2011and SAFA Workshops - Sophia Antipolis,France.Main Topic: Digital MobilityMore information on www.same-conference.org- "SAME goes back to School": Presentsinformation on careers in microelectronicsengineering to regional high school studentswith the aim of encouraging them to takeengineering degrees.- Promoting microelectronic start-ups:individualised analysis and assistance oneverything from defining market strategy toclient/partner prospecting.- CIM PACA provides academic and industrialentities with leading-edge tools to design ICsfor the next generation of secure mobilecommunication devices.- Sophia Academy: is an initiative of leaders’company. They want to propose to theiremployees a local access to high leveltrainings. They want to share theirexperiences and mutualize their needs.

Satin Technologies delivers software solutionsfor fact-based design quality monitoring andclosure.Working within customers' design flows, thecompany’s VIP Lane® turns customers' designpractices (for IP blocks, SoCs, embeddedsystems) into a robust and reliable set ofquality criteria and metrics. These customer-based parameters are used to createautomated, sharable dashboards and qualitycompliance reports.By providing an alternative to manually filled,time-consuming checklists and documents,VIP Lane® delivers effective flow integrationand on-the-fly quality monitoring at zerooverhead to design teams.

SELEX Galileo, a Finmeccanica Company,develops integrated capability solutionswhich deliver enhanced situation awareness,security, and safety across land, sea and air.Solutions from surveillance, imaging,tracking, targeting to protection andnavigation control systems for military andgovernment missions. Customers across 5continents have already selected SELEXGalileo as their partner of choice to providetotal awareness, total protection solutions fortheir present and future needs.

Silansys develops and supplies innovativeturnkey ASIC products and provides a fullrange of Design Services to industry-leadingcompanies worldwide. Silansys is a qualifiedproduct and services supplier to a wide rangeof blue-chip OEM and top-5 semiconductorcompanies worldwide in markets ranging fromconsumer communications to hi-rel industrialsensors. Silansys has a world-class track-record in architecting and deliveringsuccessful commercial products that integrateinnovative RF, Mixed-Signal and Digitaltechnology into single-chip SoC products.

Springer is one of the world-leaders in bookpublishing, boasting a broad range of subjectmatter, and a history of working with themost prestigious scholars in the field.Additionally, Springer publishes an astutecollection of Journals, with a track record ofgenerating the latest sought after content.For additional information about all ourengineering publications, please stop by ourbooth, or visit us at springer.com

PRODUCT FINDERServices:Data Management and Collaboration

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SELEX Galileo Contact: Sergio PellegriniVia A. Einstein 35,50013 Campi Bisenzio (FI)ITALYTel: +39 055 89501Fax: +39 055 8950600E-Mail: [email protected]: www.selexgalileo.com

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Satin Technologies Contact: Michel TabusseCap Omega, Rond-Point Benjamin FranklinCS 3952134960 Montpellier Cedex 2, FranceTel: +33 467 13 00 86Fax: +33 467 13 00 10E-Mail: [email protected]: www.satin-tech.com

Silansys Semi Contact: Niall O’HearcainAdelaide ChambersPeter StreetDublin 8IrelandTel: +353 1 4830840E-Mail: [email protected] Website: www.silansys.com

PRODUCT FINDERASIC and SOC Design:Design EntryBehavioural Modelling & SimulationSynthesisPower & OptimisationPhysical Analysis (Timing, Themal, Signal)VerificationAnalogue and Mixed-Signal DesignRF Design System-Level Design:Behavioural Modelling & AnalysisPhysical AnalysisHardware/Software Co-DesignPackage DesignPCB & MCM Design Test:Design for TestDesign for Manufacture and YieldLogic AnalysisTest Automation (ATPG, BIST)Boundary ScanSilicon ValidationMixed-Signal TestSystem Test Services:Design ConsultancyPrototypingData Management and CollaborationIP e-commerce & ExchangeFoundry & Manufacturing Hardware:FPGA & Reconfigurable PlatformsDevelopment BoardsWorkstations & IT Infrastructure Semiconductor IP:Analogue & Mixed Signal IP Application-Specific IP:Analogue & Mixed Signal IPData CommunicationDigital Signal ProcessingNetworkingWireless Communication

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SPRINGER Contact: Lothar MinickaTiergartenstr. 1769121 HeidelbergGermanyTel: +49 6221 4870Fax: +49 6221 4878366E-Mail: [email protected]: www.springer.com



Tanner EDA develops and markets electronicdesign automation software for designers ofmixed-signal and analog ICs, and MEMScircuits. Our L-Edit Pro layout and verificationsoftware and T-Spice Pro design entry andsimulation software provide a complete,productive and cost-effective design solution.Tanner Tools are easy-to-use and trulyaffordable, with a powerful range of featuresand industry-standard file formats. With over25,000 licenses sold worldwide these are thebest and most reliable products for IC Designfor Windows PC.We are represented in Europe by EDASolutions (www.eda-solutions.com). Come andmeet us and see for yourself the PowerBehind the Tool!

Target Compiler Technologies is the leadingprovider of software tools to automate andoptimize the design and programming ofapplication-specific processor cores (ASIPs).

The "IP Designer" tool suite has been appliedby customers worldwide for diverseapplication domains, includingGSM/WCDMA/HSDPA handsets, VoIP,audio/video/image codec/processing,automotive, ADSL/VDSL modems, wirelessLAN, hearing instruments, and mobile/low-power applications.URL: www.retarget.com

Today’s electronic design engineers facebroader challenges than ever before. Softwareis becoming as important as hardware. And inthe IC supply chain, former competitors arenow collaborating to achieve success. Tech Design Forum publication (formerlycalled the EDA Tech Forum) is the premierguide for success in this complexenvironment. Focused on the designautomation market, this publication and itsrich website offer a wealth of practical adviceon how to successfully negotiate the day-to-day problems designers face.

The Next Silicon Valley is an independentmedia website that publishes global news andinformation about the world of innovation,entrepreneurship, technology development,regional economic development, venturecapital, and investment promotion acrossglobal markets. The Next Silicon Valleyreaches readers in more than 90 countriesand 400 cities worldwide.

TowerJazz is recognized for our industryleading models and tools which give ourcustomers a significant competitive marketadvantage with first time design success,optimal performance, and the shortest time-to-market at reduced cost. Our extensivedesign enablement infrastructure provides anenvironment optimized for analog and RFdesigns. This includes silicon verified andhighly scalable device models and robustphysical design tools for up front designoptimization. Unique tools such as MonteCarlo statistical and PCM based models allowthe user to maximize the performance-yieldtradeoff. In addition, MOSVAR model librariesimprove simulation accuracy reducing productdevelopment time. The Jazz Inductor Toolbox(JIT) provides advanced modeling capabilityfor octagonal and square inductors to providedesigners flexibility in choosing the rightinductors when designing their products. Ourpowerful and efficient tools enableunprecedented accuracy in device models andour unparalleled customer support at everystage of the design flow ensures confidencein designs at near zero risk.

PRODUCT FINDERASIC and SOC Design:Design Entry System-Level Design:Acceleration & EmulationHardware/Software Co-Design Services:Design Consultancy Embedded Software Development:CompilersDebuggersSoftware/Modelling

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Tech Design Forum Contact: Sandra SillionTel: +1 949 226 2011E-Mail: [email protected]: www.edatechforum.com

PRODUCT FINDERASIC and SOC Design:Design EntryBehavioural Modelling & SimulationVerificationAnalogue and Mixed-Signal DesignMEMS DesignRF Design Services:Design Consultancy Semiconductor IP:Analogue & Mixed Signal IPPhysical Libraries Application-Specific IP:Analogue & Mixed Signal IP

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Target CompilerTechnologies Contact: Jeroen De LilleTechnologielaan 11-0002,3001 Leuven,BelgiumTel: +32 16 38 1030Fax: +32 16 38 1049E-Mail: [email protected]: www.retarget.com

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Tanner EDA Contact: Lynne WrightEDA Solutions LiimitedUnit A5, Segensworth Business Centre,Segenswoth Road,FarehamHants PO15 5RQUnited KingdomTel: +44 1489 564 253Fax: +44 1489 557 367E-Mail: [email protected]: www.eda-solutions.com

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The Next Silicon Valley Contact: Richard WallaceTel: +1 631 907-2559E-Mail: [email protected]: www.thenextsiliconvalley.com

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TinnoTek Inc. Contact: Shan-Chien Fang121R, Innovation Incubator, National TsingHua University, 101, Sec. 2, Kuang-FuRd.,Hsinchu 300, Taiwan, R.O.C.Tel: +886 3 5741082Fax: +886 3 5741084E-Mail: [email protected]: www.tinnotek.com.tw

PRODUCT FINDERASIC and SOC Design:Power & OptimisationPhysical Analysis (Timing, Themal, Signal) Services:IP e-commerce & Exchange Semiconductor IP:Configurable Logic IP

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TowerJazz Contact: Melinda Jarrell4321 Jamboree RoadNewport Beach, CA 92660USATel: 001 9494358181Fax: 001 949-435-8757E-Mail: [email protected]: www.towerjazz.com



Technology projections indicate that futureelectronic devices will keep shrinking, beingfaster and consuming less energy peroperation. In the next decade, a single chipwill be able to perform trillions of operationsper second and provide trillions of bytes persecond in off-chip bandwidth. This is the socalled Terascale Computing era, whereterascale performance will be mainstream,available in personal computer, and being thebuilding block of large data centers withpetascale computing capabilities. However,these smaller devices will be much moresusceptible to faults and its performance willexhibit a significant degree of variability. Asa consequence, to unleash these impressivecomputing capabilities, a major hurdle interms of reliability has to be overcome. TheTRAMS project is the bridge for reliable,energy efficient and cost effective computingin the era of nanoscale challenges andteraflop opportunities.

Tyndall's Design Technology Evaluation (DTE)group performs Intellectual Property patentinfringement investigation for key Europeanand US companies. This group implements acomplete 'tear down' of an IC's design, itstechnology, its assembly and system; thencompare with a portfolio of patents in orderto ascertain if infringement has occurred. Areport is then generated providing clearevidence in relation to specific patents.Where necessary, staff will also support itsfindings as a 'facts expert witness' in a courtof law. In support of our IP investigationwork is an extensive infrastructure of analysisequipment in excess of €35 Million. Thisgroup also performs extensive electricalcharacterisation of 'mixed signal' designs.

The University Booth is part of the DATEprogram and is sponsored by the DATE SponsorSociety. The University Booth will be organizedfor EDA software and hardware demonstrations.Universities and public research institutes arepresenting innovative hardware and softwaredemonstrations. All demonstrations will takeplace during the exhibition within a dedicatedtime slot. The University Booth is organized byLorena Anghel (TIMA Laboratory) and VolkerSchöber (edacentrum).

PRODUCT FINDERASIC and SOC Design:Design EntryBehavioural Modelling & SimulationSynthesisPhysical Analysis (Timing, Themal, Signal)Verification System-Level Design:Behavioural Modelling & AnalysisPhysical Analysis Semiconductor IP:CPUs & ControllersMemory IPOn-Chip Bus InterconnectPhysical Libraries

PRODUCT FINDERASIC and SOC Design:VerificationMEMS DesignRF Design Services:Foundry & Manufacturing Semiconductor IP:Analogue & Mixed Signal IP Application-Specific IP:Analogue & Mixed Signal IPWireless Communication

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TRAMS Contact: Antonio Rubioc/ Jordi Girona 31, 08034 Barcelona, SpainTel: +34934017485Fax: +34934016756E-Mail: [email protected]: www.trams-project.eu

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Tyndall’s Design TechnologyEvaluation Group Contact: Ted O’SheaUniversity College CorkDyke ParadeCorkIrelandTel: +353 21 4904159E-Mail: [email protected] Website: www.tyndall.ie/DTE

PRODUCT FINDERASIC and SOC Design:Physical Analysis (Timing, Themal, Signal) System-Level Design:Acceleration & EmulationHardware/Software Co-Design Test:Design for TestDesign for Manufacture and YieldLogic AnalysisTest Automation (ATPG, BIST)Boundary ScanSilicon ValidationSystem TestServices:Design ConsultancyIP e-commerce & ExchangeFoundry & ManufacturingTraining Hardware:FPGA & Reconfigurable PlatformsDevelopment Boards Semiconductor IP:Analogue & Mixed Signal IPMemory IPOn-Chip DebugTest IPVerification IOApplication-Specific IP:Analogue & Mixed Signal IPSecurity

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University Booth Contacts: Volker Schöber (Germany), Lorena Anghel (France)edacentrum GmbH, Schneiderberg 32, 30167Hannover, GermanyTIMA Laboratory, 46 avenue Felix Viallet,38031 Grenoble, FranceTel: +49 (511) 762 19688 (Germany), +33 (4) 7657 4696 (France)Fax: +49 (511) 762 19695 (Germany), +33 (4) 7657 4981 (France)E-Mail: [email protected]: date-conference.com/group/exhibition/u-booth

PRODUCT FINDERASIC and SOC Design:Design EntryBehavioural Modelling & SimulationSynthesisPower & OptimisationPhysical Analysis (Timing, Themal, Signal)VerificationAnalogue and Mixed-Signal DesignMEMS DesignRF Design System-Level Design:Behavioural Modelling & AnalysisPhysical AnalysisAcceleration & EmulationHardware/Software Co-DesignPackage Design Test:Design for Manufacture and YieldLogic AnalysisTest Automation (ATPG, BIST)Boundary ScanSilicon ValidationMixed-Signal TestSystem Test Services:Design ConsultancyPrototypingData Management and CollaborationIP e-commerce & ExchangeTraining Embedded Software Development:CompilersSoftware/Modelling Hardware:FPGA & Reconfigurable PlatformsDevelopment Boards



The School of Electronics and Computer Science(ECS) is at the forefront of electronics systemsdesign for energy harvesting applications. ECShas a strong international reputation in the fieldof energy harvesting and is at the forefront ofresearch activities in this area. ECS is leading theEPSRC funded project 'Next Generation EnergyHarvesting Electronics: Holistic Approach' and isalso managing on behalf of the community theEPSRC funded Network on Energy Harvesting. ECSalso a partner on two ongoing EU Framework 7projects on energy harvesting, TRIADE andTIBUCON, and togther these research activitiescombine state of the art development of flexibleenergy harvesting systems with practicalapplications in aeronautics and buildingmanagement. The energy harvesting networkprovides an important focus for the communitywith the objective of raising the profile ofresearch in this area and identifying futureopportunities. In 2004, ECS formed PerpetuumLtd, a University spin-out based upon vibrationenergy harvesting research.

Veriest Venture is a novel IC and EDS designhouse providing forefront ASIC and FPGAdesign services and Electronic Design complexSystem engineering services. Our family ofcustomers includes leading companies acrossthe networking, data, communication,consumer electronics and wireless industries.Our skilled and creative team can effectivelypromote architecture design, implementation,system integration and advanced verification.Veriest's scope of expertise extends formsilicon to system specification, and is adesign leader in system and microarchitecture, frontend VSLI, functional andformal verification and FPGA emulation.Owing to our productive partnerships withmajor EDA companies, such as Cadence,Synopsys and Mentor Graphics, Veriest hasbecome one of the early adopters of thelatest in chip design and EDA technologies.Our highly trained design quality engineersand process analysts ensure we continue toprovide leading applications and ASIC, SoC,FPGA design and verification services.From specification to first-time-right silicon,our expertise in architecture, high speed andlow power design and methodology enablesour customers to achieve enhancedperformance and faster time-to-market.

PRODUCT FINDERASIC and SOC Design:Design EntryBehavioural Modelling & SimulationSynthesisPower & OptimisationVerification System-Level Design:Behavioural Modelling & AnalysisAcceleration & EmulationHardware/Software Co-DesignPCB & MCM Design Services:Design ConsultancyPrototypingData Management and CollaborationIP e-commerce & ExchangeTraining Embedded Software Development:Software/Modelling Hardware:FPGA & Reconfigurable PlatformsDevelopment Boards Semiconductor IP:Configurable Logic IPCPUs & ControllersEmbedded FPGAMemory IPOn-Chip Bus InterconnectProcessor PlatformsVerification IO Application-Specific IP:Data CommunicationDigital Signal ProcessingMultimedia GraphicsNetworkingTelecommunicationWireless Communication

PRODUCT FINDERASIC and SOC Design:Behavioural Modelling & SimulationSynthesisPower & OptimisationAnalogue and Mixed-Signal DesignMEMS Design System-Level Design:Behavioural Modelling & AnalysisAcceleration & EmulationHardware/Software Co-DesignPCB & MCM DesignTest:Design for TestDesign for Manufacture and YieldMixed-Signal TestSystem Test Services:Design ConsultancyPrototypingData Management and CollaborationIP e-commerce & Exchange Embedded Software Development:Software/Modelling Semiconductor IP:Analogue & Mixed Signal IPEmbedded FPGAEmbedded Software IP Application-Specific IP:Analogue & Mixed Signal IPDigital Signal Processing

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Veriest Venture Contact: Berg Tara22A Raul Walenberg St. Beit Zamir, RamatHachayal, Tel Aviv, IsraelTel: +972.73.705.2530Fax: +972.3.644.0737E-Mail: [email protected]: www.veriest-v.com

University of Southampton Contact: Dr Steve BeeyUniversity of SouthamptonSchool of Electronics and Computer ScienceHighfield, Southampton, SO17 1BJUKTel: +44 2380 596663Fax: +44 2380 592901E-Mail: [email protected]: www.ecs.soton.ac.uk

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XYALIS is an EDA company offering a fullyintegrated Mask Data Preparation solution toeliminate the risk of error, reduce time tomanufacturing, and increase manufacturing

yield by automating frame generation, Multi-Project Wafers assembly, intuitive mask setcreation, and wafer map optimization, and bystreamlining the mask order process. XYALIS'solutions have been developed in cooperationwith major semiconductor industry leaders andhave been used in production for years.

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XYALIS Contact: Rene DonkersUS office, San Carlos, California, USAEurope Office, Eindhoven, the NetherlandsTel: +31 641539004Fax: +31 847503816E-Mail: [email protected]: www.fract-tech.com

PRODUCT FINDERTest:Design for Manufacture and Yield Services:Data Management and Collaboration Embedded Software Development:Software/Modelling


March 12-16, 2012, ICC, Dresden, Germany

Scope of the EventThe 15th DATE conference and exhibitionis the main European event bringingtogether designers and designautomation users, researchers andvendors, as well as specialists in thehardware and software design, test andmanufacturing of electronic circuits andsystems. It puts strong emphasis onboth ICs/SoCs, reconfigurable hardwareand embedded systems, includingembedded software.

Submission of PapersAll papers have to be submittedelectronically by September 11th, 2011via: http://www.date-conference.com/submit.htmlPapers can be submitted either forstandard oral presentation or forinteractive presentation

DATE SecretariatEuropean Conferences3 Coates Place, Edinburgh, EH3 7AA, UK

Tel: +44-131-225-2892 Fax: +44-131-225-2925Email: [email protected]

ChairsGeneral Chair: Wolfgang Rosenstiel,University of Tuebingen, Germany,[email protected]

Program Chair: Lothar Thiele, ETH Zurich, Switzerland,[email protected]

Structure of the EventThe five-day event consists of a conference with plenary invited papers, regularpapers, panels, hot-topic sessions, tutorials, workshops, two special focus days and atrack for executives. The scientific conference is complemented by a commercialexhibition showing the state-of-the-art in design and test tools, methodologies, IPand design services, reconfigurable and other hardware platforms, embedded software,and (industrial) design experiences from different application domains, such asautomotive, wireless, telecom and multimedia applications. The organisation of usergroup meetings, fringe meetings, a university booth, a PhD forum, vendorpresentations and social events offers a wide variety of extra opportunities to meetand exchange information on relevant issues for the design and test community.Special space will also be allocated for EU-funded projects to show their results. More details are given on the DATE website (www.date-conference.com).

Areas of InterestWithin the scope of the conference, the main areas of interest are: embedded systems, design methodologies, CADlanguages, algorithms and tools, testing of electronic circuits and systems, embedded software, applications design andindustrial design experiences. Topics of interest include, but are not restricted to:• System Specification and Modeling• System Design, Synthesis and Optimization• Simulation and Validation• Design of Low Power Systems• Power Estimation and Optimization• Emerging Technologies, Systems and Applications• Formal Methods and Verification• Network on Chip• Architectural and Microarchitectural Design• Architectural and High-Level Synthesis• Reconfigurable Computing• Logic and Technology Dependent Synthesis for

Deep-Submicron Circuits• Physical Design and Verification• Analogue and Mixed-Signal Circuits and Systems• Interconnect, EMC, EMD and Packaging Modeling• Computing Systems

• Communication, Consumer and Multimedia Systems• Transportation Systems• Medical and Healthcare Systems• Energy Generation, Recovery and Management Systems• Secure, Dependable and Adaptive Systems• Test for Defects, Variability, and Reliability• Test Generation, Simulation and Diagnosis• Test for Mixed-Signal, Analog, RF, MEMS• Test Access, Design-for-Test, Test Compression, System Test• On-Line Testing and Fault Tolerance• Real-time, Networked and Dependable Systems• Compilers and Code Generation for Embedded Systems; Software-

centric System Design Exploration• Model-based Design and Verification for Embedded Systems• Embedded Software Architectures and Principles; Software for MPSoC,

Multi/many-core and GPU-based Systems

the european system design show · 2011. 3. 11. · power formats: beyond upf and cpf room –...

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