the cpu and memory - york university · itec 1000 introduction to information technologies...

ITEC 1000 Introduction to Information Technologies

The CPU and Memory

How does a computer work?

How does a computer interact with data?

How are instructions performed?

Recall schematic diagram:

1

Sunday, November 1, 2009


Registers

A register is a permanent storage location within the CPU.

Registers may contain:

• a memory address for communication with memory

• an input or output address

• data is stored for an arithmetic or logic operation

• an instruction in process of execution

• codes for special purposes - e.g. keeping track of status

• conditions for conditional branch instructions

The Little Man Computer had a single register - the accumulator

2



Register Characteristics:

• directly wired within CPU• not addressed as memory locations for which access time is slow• manipulated by CPU during execution• may be of different sizes depending on function

Register names and functions:

• program counter register (PC) - holds address of current instruction• instruction register (IR) - holds actual instruction being executed together with parameters• memory address register (MAR) - holds address of a memory location• memory data register (MDR) - holds data being stored or retrieved from memory location addressed by MAR• status registers - indicate such as: arithmetic/logic conditions, memory overflow, power failure, internal error, etc.

3



Memory- operation - capacity - implementations

Operations on memory - role of the MAR and MDR

MAR holds an address of a sequence of adjacent bytes - usually 8A decoder interprets address - opens up circuits (lines) to location

Each bit of MDR may be connected to each bit of memory - sowhen MAR opens circuits to addressed location : • a connection is made from each of the data bits at addressed location

to corresponding bit in MDR• condition of memory bit is transfered to corresponding MDR bit• conversely condition of MDR bit can be transfered to corresponding memory bit

4



Relation between MAR and MDR

For the case when addresses are expressed in 32 bits and memory locationsare addressed as large 8 byte chunks = 64 bits ---

A given 32 bit memory address is “decoded” by Address Decoderto effectively open circuits (lines) between bits of the memory data register and bits of the 8 byte addressed memory location.

Data in memory location can be transferred to MDR by turning on bits in MDR that correspond to bits turned on in memory.

Conversely data can be transfered from MDR to an addressed memory location.

5



Memory capacity

The addressable capacity of a computer is related to the size ofthe Memory Address Register.

• A 32 bit registrar allows 232 = 4,294,967,296 addresses • Each address indicates position of a byte • A 32 bit register allows possibility of addressing 4 GB (gigabytes) - 4 billion bytes.• Notice we round to the nearest billion• For full capacity to be realized computer must contain at least 4GB of physical memory

6



• network of electrically-charged points• quickly accessible• any portion can be directly accessed - thus “random access”• charge must be renewed every few milliseconds - thus volatile• inexpensive

Memory implementations

Magnetic core memory - small bit of magnetic material for each bit of memory.Small wires connect to magnetic bits that allow to electrical current that will change polarity. Expensive - but non-volatile - military & space applications

RAM (random access memory)

dynamic RAM = DRAM

7



ROM - read only memory

• fixed part of computer circuits - called mask ROM used in older computers

• more recent types allow for in frequent and slow re-writing - EEPROM or Flash Rom - used in electronic devices - cameras, cell- phones, automobiles, ....

static RAM = SRAM

faster, more expensive, most computers have small amount for high speed access - also called cache memory - also volatile

8



Fetch-Execute Instruction Cycle

Step 1: address of instruction moved from PC to MAR - this automatically transfers content of addressed location to MDR - thus MDR contains the instruction and its parametersStep 2: contents of MDR is transfered to instruction register (IR)

Computer designed to execute instructions sequentially. The program counter register (PC) contains the address in memory of location containing next instruction to execute.Program counter was set by previous instruction

Following steps occur automatically - hardwired - part of control unit

Step 4: the instruction in IR is executed

Step 5: the program counter register is updated to address of next instruction

Step 3: address part of instruction (if there is one) moved to MAR

9



Example: (Little Man Computer syntax)

PC contains number 65 - the address of 65th boxBox 65 contains the instruction 590 - that is: load contents of box 90 to accumulator (A).Box 90 contains number 111

Step 1: address 65 transfers to MAR - the contents of box 65 transfered automatically to MDR - thus MDR contains 590Step 2: contents of MDR transfered to IR - thus IR contains 590

Step 3: the address part of the instruction - that is 90 - is transfered to MAR and the contents of address 90 automatically transfered to MDRStep 4: contents of 90 added to accumulator (A) - thus A contains 111

Given information:

The cycle:

Step 5: PC updated

10



Fetch-Execute Example: Load AccumulatorAssume: Simple Eight bit system.• Thirty-two memory locations (0 to 31).• “Load” instruction is 0101 binary or 5 decimal.• Value in location 15 is ten (ie: binary 00001010)• PC (program counter) is at 5 and is about to be incremented.• The instruction, 101 01111, is in location 6 - instructions are considered to consists of 2 parts - 3 bits at high end for operation code followed to right by 5 bits for

addressThen ...

11



PC: 00101

IR: (previous)

A: (previous)

MAR: (previous)

MDR: (previous)

CPU Before PC increments

Location 31

15: 00001010

06: 101 01111= 5 15

Location 0

12

= 05



PC: 00110

IR: (previous)

A: (previous)

MAR: (previous)

MDR: (previous)

Increment PC: PC = PC + 1Location 31

15: 00001010

06: 101 01111

Location 0

13

Using instruction in location 6 load contents of location 15 to accumulator

= 5 15

= 06



PC: 00110

IR: (previous)

A: (previous)

MAR: 00110

MDR: (previous)

MAR loaded with PC: PC -> MAR

Location 31

15: 00001010

06: 101 01111= 5 15

Location 0

14

= 06

= 06



PC: 00110

IR: (previous)

A: (previous)

MAR: 00110

MDR: (previous)

Memory Location 00110 Accessedand Contents to be Placed in MDR:

Location 31

15: 00001010

06: 101 01111= 5 15

15

= 06

= 06



PC: 00110

IR: (previous)

A: (previous)

MAR: 00110

MDR: 101 01111

Memory Location 00110 Accessedand Contents Placed in MDR:

Location 31

15: 00001010

06: 101 01111

Location 0

16

= 06

= 06

= 5 15



PC: 00110

IR: 101 01111

A: (previous)

MAR: 00110

MDR: 101 01111

MDR copied to IR: MDR -> IR

Location 31

15: 00001010

06: 101 01111

Location 0

17

= 06

= 06

= 05 15

= 05 15



PC: 00110

IR: 101 01111

A: (previous)

MAR: 1111

MDR: 101 01111

IR [ address part ] -> MAR

Location 31

15: 00001010

06: 101 01111

Location 0

18

= 06

= 5 15

=15

= 5 15

Address portion transfered to MAR



PC: 00110

IR: 101 01111

A: (previous)

MAR: 1111

MDR: 101 01111

Location in MAR (01111) Accessed

Location 31

15: 00001010

06: 101 01111

Location 0

19

= 06

=15connection to memory established

= 05 15



PC: 00110

IR: 101 01111

A: (previous)

MAR: 1111

MDR: 00001010

Contents of 01111 loaded into MDR

Location 31

15: 00001010

06: 101 01111

Location 0

20

= 06

data in memory transfered



PC: 00110

IR: 101 01111

A: 00001010

MAR: 1111

MDR: 00001010

IR [op code] executed: MDR -> A

Location 31

15: 00001010

06: 101 01111

Location 0

21

= 06

op code 5 loads contents of MDR



PC: 00110

IR: 101 01111

A: 00001010

MAR: 1111

MDR: 00001010

Finished !

Location 31

15: 00001010

06: 101 01111

Location 0

22

= 06



Then ...

23

Now the next instruction:Assume: • Value in location 7 is 001 10010.• “Add” instruction is 001.• Value in location 18 is seventy-one (i.e.: binary 01000111)• Everything else is as we left it!



PC: 00111

IR: 101 01111

A: 00001010

MAR: 01111

MDR: 00001010

PC = PC + 1

Location 31

18: 01000111

15: 00001010

07: 001 10010 06: 101 01111

Location 0

24

= 7



PC: 00111

IR: 101 01111

A: 00001010

MAR: 00111

MDR: 00001010

PC -> MAR

Location 31

18: 01000111

15: 00001010

07: 001 10010 06: 101 01111

Location 0

25



PC: 00111

IR: 101 01111

A: 00001010

MAR: 00111

MDR: 00001010

MAR Accesses Location 00111 = 7

Location 31

18: 01000111

15: 00001010

07: 001 10010 06: 101 01111

Location 0

26



PC: 00111

IR: 01001111

A: 00001010

MAR: 00111

MDR: 001 10010

Contents of 00111 -> MDR

Location 31

18: 01000111

15: 00001010

07: 001 10010 06: 101 01111

Location 0

27



PC: 00111

IR: 001 10010

A: 00001010

MAR: 00111

MDR: 001 10010

MDR -> IR

Location 31

18: 01000111

15: 00001010

07: 001 10010 06: 101 01111

Location 0

28



PC: 00111

IR: 001 10010

A: 00001010

MAR: 10010

MDR: 001 10010

IR [address] -> MAR

Location 31

18: 01000111

15: 00001010

07: 001 10010 06: 101 01111

Location 0

29



PC: 00111

IR: 001 10010

A: 00001010

MAR: 10010

MDR: 10110010

Location 10010 =18 [MAR] Accessed

Location 31

18: 01000111

15: 00001010

07: 001 10010 06: 101 01111

Location 0

30



PC: 00111

IR: 001 10010

A: 00001010

MAR: 10010

MDR: 01000111

Contents of [10010] -> MDR

Location 31

18: 01000111

15: 00001010

07: 001 10010 06: 101 01111

Location 0

31



PC: 00111

IR: 001 10010

A: 01010001

MAR: 10010

MDR: 01000111

IR [opcode] executed: A = A + MDR

Location 31

18: 01000111

15: 00001010

07: 001 10010 06: 10101111

Location 0

32



To Continue:

The process continues in the same fashion, more or less, until a stop or halt instruction is encountered.

33



Instructions

34

General Format:

Op code 8 bits address fields

How address fields are used varies with CPU design

Sometimes - • an address implicit in operation definition - Little Man load and store operations

• always explicitly stated - fixed length instruction sets

Explicit addresses: memory addresses or register codes


ITEC 1000 Introduction to Information Technologies 35

Example: Assume: an amount x in location with address X an amount y in location with address Y R pointer to location of a register

Add R | X | Y

adds contents of address X to contents of address Y and places result in register R



Instruction types:

Data movement -

• one memory location to another• memory location to register• register to memory location • register to register

Arithmetic operations -

• different operations for various expressions of integers - signed or unsigned and various byte lengths

8 byte char16 short short32 int int64 long lomg

bits signed name

• different operations for: add, subtract, multiply, divide for integers and for floating point

unsigned name



Boolean Operations

Given a bit stream - a sequence of zeros and ones

1 means the bit is “on” or “true”0 means the bit is “off” or “false”

The operation not - indicated as ¬ or !

every 0 becomes 1 and every 1 becomes 0

! (010010010110) = (101101101001)

1

For pair of bit streams p and q

AND, OR and XOR operations -



Boolean Operations

Given a bit stream - a sequence of zeros and ones

1 means the bit is “on” or “true”0 means the bit is “off” or “false”

The operation not - indicated as ¬ or !

every 0 becomes 1 and every 1 becomes 0

! (010010010110) = (101101101001)

1

For pair of bit streams p and q

AND, OR and XOR operations - p q p ANDq p OR q p xor q

1 1 1 1 01 0 0 1 10 1 0 1 10 0 0 0 0



Single operand instructions

Add one or subtract one from register or memory location

Bit manipulation instructions

Shift and rotate instructions

Various conventions

Program controljump and call/return instructions

Stack instructions• address values of locations of data (e.g. intermediate calculations) stored sequentially in memory.• 32 bit stack - sequential blocks of 32 bits - lower order block called bottom - high order block called top• push adds to top - pop removes from top

Multiple data instructionsoperations on blocks of data e.g. in graphics, multiplication of 4x4 matrices


the cpu and memory - york university · itec 1000 introduction to information technologies...

Documents