The challenge for memory test

2011. 11. 04

이대희

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Contents 1. DRAM Memory Trend

2. Test Challenges -. High speed test -. Fine pitch device test -. TCR (Test Cost Reduction) 3. Summary

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Main Memory Speed Trend

2010 2005 2015 2020 2000

25

50

100

125

150

Band w

idth

(G

B/s

ec)

Year

1Channel 2Ch

3Ch

4Ch

SDR DDR DDR2 DDR3 DDR4 DDR5 ?

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Graphics System Trend (Bus and Bandwidth)

2010 2005 2015 2020 2000

100

200

300

400

500

Ba

nd

wid

th (

GB

/se

c)

Year

600

128bit 256bit

384bit

~ 2K bit

DDR2

GDDR3

GDDR5

~ 2.4Gbps

Wide IO TSV

4/18

2010 2005 2015 2020 2000

6.4

51.2

Ba

nd

wid

th (

GB

/se

c)

Year

Mobile Memory Usage Trend (Bandwidth)

1.6GBps

DDR X32

DDR2 X32

Wide I/O

DDR2 X16

Serial I/O

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The challenge for memory test

High speed test Mobile KGD test Package high speed channel sharing

Fine pitch device test PCB Technical limit Fine pitch socket

TCR ( Test Cost Reduction ) Probe 1-T/D Solution Low Cost Tester Legacy tester life cycle extension

6/18

Mobile Device Demand Growth

for Various Entertainment Product

Low Power, High Performance Memory

Small foot print Product

MCP, Embedded Product

→ High Speed KGD Test will be needed

1-1. Mobile KGD Test

Over 500Mhz to 1Ghz probe test is possible

Present System 280 ~ 400Mhz ..Too Slow !!!

Probe Card is possible in speed. But Parallel is Too small !!!

KGD Test Challenges

High speed test (1/5)

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High speed test (2/5)

1-2. High Speed Probe CARD

High Speed probe CARD

-. Low parallelism

-. crosstalk, noise minimize

-. PCB size (space) limit

m6f req=200.0MHzFar_end_Cross_Talk=-27.557

50 100 150 200 250 300 350 400 4500 500

-50

-40

-30

-20

-10

-60

0

freq, MHz

Fa

r_e

nd

_C

ross_T

alk

m6

Fa

r_e

nd

_C

ross_T

alk

1

m4f req=200.0MHzNear_end_Cross_Talk=-29.501

50 100 150 200 250 300 350 400 4500 500

-50

-40

-30

-20

-10

-60

0

freq, MHz

Ne

ar_

en

d_

Cro

ss_T

alk

m4

Ne

ar_

en

d_

Cro

ss_T

alk

2

Simulated Cross Talk Comparison

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.90.0 1.0

-5

-4

-3

-2

-1

-6

0

freq, GHz

dB

($U

12_A

12_S

21_747C

..S

(2,1

))dB

(U12_A

12_S

21_747D

..S

(2,1

))

m1time=56.23nsecU43_A04_V..CHANNEL2=0.191

m2time=56.48nsecU43_A04_V..CHANNEL2=0.271

m3time=56.37nsec$C_U43_A04_V..CHANNEL2=0.216

m4time=56.63nsec$C_U43_A04_V..CHANNEL2=0.280

54 5652 58

0.2

0.3

0.1

0.4

time, nsec

U43_A

04_V

..C

HA

NN

EL2

m1

m2

$C

_U

43_A

04_V

..C

HA

NN

EL2

m3

m4

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2-1. Package high speed channel sharing

Parallel 64 128 256 512 512

Data Rate 1Gbps < 1Gbps < 1 ~ 2Gbps 2 ~ 4Gbps

Sharing - 2 4 4 or 8 4 or 8

Method

T-Branch Daisy-Chain Daisy-Chain

Timing Error ? Tr / Tf ?

DDR4 Data rate 2.4~4.0Gbps

Package test system speed Max 8Gbps

Test Parallel & DR Channel Sharing ?

High speed test (3/5)

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2-2. Signal integrity for sharing high speed channel

Technical development needed for efficient TR/TF performance

High speed test (4/5)

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2-3. Timing Error : RC time delay

High speed test (5/5)

time delayed

High frequency affects on timing error growth Test hardware limit Timing training solution needed to reduce Skew & Timing error

△t1 △t2 △t3

Timing error according to capacitance change Channel Skew

DUT 1

DUT 4

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1-1. Fine pitch device test

Main Memory Mobile(PoP)

0.8 pitch 0.5

pitch 0.4 pitch

0.35

pitch

Fine pitch device test challenges 0.4mm

0.25mm

contact pin count Chip

Substrate

Au Wire

[ Ball Pitch ]

[ Solder Ball Height ]

Ball pitch 0.8 >> 0.5 >> 0.4 >> 0.35

PCB limit & Yield Down

Expensive Interface Cost (socket price increased )

- PCR 0.4pitch : X, POGO 0.3pitch : OK but expensive

Contact Faulty ( open , short , leakage fail , low yield, ball damage , retest …)

Fine pitch device test (1/3)

12/18

Pitch - 0.5mm 0.4mm 0.3mm

Drill A 0.25mm 0.15mm 0.15mm

Drill to Pattern B 0.1mm 0.1mm 0.05mm

Inner Layer

Pattern C 0.05mm 0.05mm 0.05mm

Drill Spec 0.15mm , Tolerance 0.05

Normal Tolerance Drill+D/F+layer Up Tolerance 0.1mm

Special Tolerance Drill+D/F+layer Up Tolerance 0.020mm

1-2. Fine pitch PCB Limitation

Drill process of fine pitch PCB causes yield drop

0.3 pitch , Drill Tolerance < 20um

Current technology is impossible

→ New technology needed ( Pitch Convertor ?)

Fine pitch device test (2/3)

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1-3. Fine pitch Socket

Interposer

Interposer

Convert PCB

Base cover

Housing

Probe

Center guide

0.4Pitch 0.3Pitch

Floating

Flo

ating

Socket Socket

Contact accuracy

-. Ball vs socket pin price goes down, on the other hand short fail increase

-. Managing device size tolerance needed

-. Thin diameter causes socket pin damage

Solution

-. Floating guide (Direct contact) : 0.3 pitch PCB limit

-. Pitch convert technology is very complicated and weak on Si

-. Wireless (Inductive Coupling)

Floating guide

Pitch convert

Fine pitch device test (3/3)

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Test Cost Reduction (1/4)

Net die growth according to tech shrink

High density product demand increase with IT trend

1 Die FAB Cost down : Tech Shrink (refer to the left graph above)

1 Die TEST Cost up : Density / Net Die growth (refer to the right graph above)

Test COM portion

TTR, DFT, parallelism, low cost tester, reduction of test process, optimum batch size, selective test by grade, etc..

TCR (Test Cost Reduction)

80nm 70nm 60nm 50nm 40nm 30nm 20nm

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1-1. Probe test Parallelism Up

Test Cost Reduction (2/4)

How to increase the parallel on Probe?

Target could be 1Wafer 1TD Testing

Probe Card Tester

High signal sharing, Worst input margin

Smaller mount space, complex circuit

design

High probe count, Mechanical deflection

Platform expansion, system cost up

Partition architecture,

more flexible DUT mode

Internal relay sharing

Poor S.I & power dividing

16/18

1-2. PKT Low Cost Tester

Test Cost Reduction (3/4)

ATE Limitation

More IO Channel needed for Test

-. x4, 8, 16, 32 → x64, 512, 1024 ~

Package test Parallel extension limit

-. IO Channel shortage

-. High test interface cost

( Handler, Interface Board, Socket )

Channel sharing limit

-. x2 / x4 / x8 x16 sharing?

-. Signal integrity weakness

-. Yield drop, dc test accuracy weakness

Low Cost Tester

Product optimized function

Low frequency for core test

Low cost per 1 Channel

FPGA use, Easy upgrade

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1-3. Legacy tester Life cycle extension

Test Cost Reduction (4/4)

Package BOST System

Current BOST system limitation

DC test X (FPGA/ASIC use)

Cooling problem for BOST Chip heating

Constraint on test process

DR 960ch

IO 576ch

PPS 64ch

VTH

VIH

BOST CORE

Current Booster

60

36

4

288

256

16

ATE BOST DSA

4096 DR

4608 I/O

288 PPS

New BOST system needed

DC test function on BOST

Water cooling system

DC Test Unit

BOST Chip

DRAM

BOST

BOST

BOST Chip

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SUMMARY

High Speed Interface Technology

-. High Speed Probe CARD parallel extension

-. High Speed Channel Sharing Technology

Fine pitch device contact

-. Contact problem according to pitch downsize

-. PCB, socket accuracy improvement and cost reduction

TCR (Test Cost Reduction)

-. Probe 1-T/D test solution

-. Low cost tester

-. New BOST system for DC Test