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DO NOT OPEN THIS TEST BOOKLET UNTIL YOU ARE ASKED TO DO SO

Test Booklet Series

TEST BOOKLET

Electronics & Communication – Paper

Topic Test – Digital & Microprocessor

Time Allowed: One Hour

Maximum Marks: 100

INSTRUCTIONS

1. IMMEDIATELY AFTER THE COMMENCEMENT OF THE EXAMINATION YOU SHOULD

CHECK THAT THIS TEST BOOKLET DOES NOT HAVE ANY UNPRINTED OR TORN OR

MISSING PAGES OR ITEMS ETC. IF SO, GET IT REPLACED BY A COMPLETE TEST

BOOKLET.

2. ENCODE CLEARLY THE TEST BOOKLET SERIES A, B, C, OR D AS THE CASE MAY BE IN

THE APPROPRIATE PLACE IN THE ANSWER SHEET.

3. You have to enter your Roll Number on the

Test Booklet in the Box provided alongside.

DO NOT write anything else on the Test Booklet.

4. This Test Booklet contains 60 items (questions). Each item comprises four responses (answers). You

will select the response which you want to mark on the Answer Sheet. In case you feel that there is

more than one correct response, mark the response which you consider the best. In any case, choose

ONLY ONE response for each item.

5. You have to mark all you responses ONLY on the separate Answer Sheet provided. See directions in

the Answer Sheet.

6. All items carry equal marks.

7. Before you proceed to mark in the Answer Sheet the response to various items in the Test Booklet,

you have to fill in some particulars in the Answer Sheet as per instructions sent to you with your

Admission Certificate.

8. After you have completed filling in all your responses on the Answer Sheet and the examination has

concluded, you should hand over to the Invigilator only the Answer Sheet. You are permitted to take

away with you the Test Booklet.

9. Sheets for rough work are appended in the Test Booklet at the end.

10. Penalty for wrong answers:

THERE WILL BE PENALTY FOR WRONG ANSWERS MARKED BY A CANDIDATE IN THE

OBJECTIVE TYPE QUESTION PAPERS.

(i) There are four alternatives for the answer to every question. For each question for which a

wrong answer has been given by the candidate, one-third (0.33) of the marks assigned to that

question will be deducted as penalty.

(ii) If a candidate gives more than one answer, it will be treated as a wrong answer even if one

of the given answers happens to be correct and there will be same penalty as above to that

question.

(iii) If a question is left blank, i.e., no answer is given by the candidate, there will be no penalty

for that question

DO NOT OPEN THIS TEST BOOKLET UNTIL YOU ARE ASKED TO DO SO


1. If A and B are Boolean variables then which one of the following is equivalent to

A B AB:

(A) A + B (B) A+B (C) A+B (D) A+B

2. How many 1’s are present in binary representation of the expression

4 4096 9 257 7 17 4 9 1

(A) 7 (B) 8 (C) 9 (D) 10

3. Consider bX (54) where b is the base of the number system. If X 7 then value of base ‘b’ is?

(A) 7 (B) 8 (C) 9 (D) Can’t be calculated

4. Consider the following data in respect of a certain digital gate:

IOH = 0.2 mA, IIH = 40 A

IOL = 16 mA, IIL = 1.6 mA

Symbols have their usual meaning, what is the value of its fan-out

(A) 5 (B) 10 (C) 40 (D) 80

5. If f(w, x, y, z) = (0, 4, 5, 7, 8, 9, 13, 15) then which of the following expressions are not equivalent

to f ??

' ' ' ' ' ' ' ' ' ' '

' ' ' ' ' ' ' ' ' ' ' '

(A) x y z w xy wy z xz (B) w y z wx y xz

(C) w y z wx y xyz xy z (D) x y z wx y w y

6. What is the value of 1 2 3f (A,B,C) (f .f ) f if Min-terms of expressions are given as follows?

1

2

3

f (A,B,C) (0,2,3,4)

f (A,B,C) (1,2,3)

f (A,B,C) (4,5,6)

(A) (0,2,3,4) (B) (2,3,4,5,6) (C) (0,1,2,3,4,5,6) (D) (2,3)

7. In a 8 variable K-Map if 32 number of 1’s are forming a group then number of literals in that group

after minimization will be?

(A) 3 (B) 4 (C) 5 (D) 6

8. Which of the following statement is not correct?

(A) XS-64 represents numbers from -64 to +63& XS-32 represents numbers from -32 to +31

(B) XS-64 represents numbers from -64 to +64& XS-32 represents numbers from -32 to +32

(C) XS-64 representation uses 7 bits while XS-32 representation uses 6 bits

(D) XS-3 code is self complementary and un weighted code

9. Consider the logic function in Min terms form as f (A,B,C,D) (1,3,5,8,9,11,15) d(2,13) what

are the numbers of complemented literals in the expression of SOP form for f (A, B,C,D)?

(A) 3 (B) 4 (C) 5 (D) 6

10. For a Boolean function Y AB AC the POS form will be:

(A) (0,2,4) (B) (1,2,5,7) (C) (2,3,5,7) (D) (0,2,4,5)

11. Which of the following identity is not correct:

(A) A B C A (B C) (A B) C (B) A B C A (B C) (A B) C

(C) A B AB A B AB A B (D) A B C A (B C) (A B) C


X

Y

Q

Q

12. How many essential prime implicates are available in expression of f (A,B,C) (0,2,3,4,5,7)

(A) 0 (B) 3 (C) 5 (D) 6

13. Among the following logic Families the one having the lowest power dissipation and highest noise

Margin is

(A) Schottky TTL (B) TTL (C) ECL (D) CMOS

14. For the circuit shown in figure, which statements are correct, initially it is assumed that Q0Q1 = 00

1. It is a Mod-3, counter 2. It is a Mod-4 counter

3. After 334 clock pulses output will be zero 4. After 339 clock pulses output will be zero

(A) 1, 3, 4 (B) 1, 4 (C) 2, 3 (D) 1, 3

15. What is the Minimum number of gates required to implement the Boolean function (AB+C) if we

have to use only 2-input NOR, gat

(A) 2 (B) 4 (C) 3 (D) 5

16. Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean

function of n-variables. What is the Minimum size of Multiplexer needed??

(A) 2n-2

line to 1 line (B) 2n line to 1 line

(C) 2n+1

line to 1 line (D) 2n-1

line to 1 line

16. Consider the following statements. A 4 × 16 decoder can be constructed with enable inputs by

1. Using 4, 2 × 4 decoders (each with enable input)



4. Using 2, 3 × 8 decoders (each with enable i/p & inverter)

Which statements are correct?

(A) Only 1 & 4 (B) Only 2 & 4 (C) Only 1 & 3 (D) Only 2 & 3

17. For a Flip-Flop formed from two NOR gate as shown in figure, the unstable state corresponds to

(A) X = 0, Y = 0

(B) X = 0, Y = 1

(C) X = 1, Y = 0

(D) X = 1, Y = 1

18. Let A = 11111010 and B = 0000 1010 be two 8, bit 2’s complement numbers, then their product in

2’s complement is

(A) 11000100 (B) 10011100 (C) 10100101 (D) 11010101


D Q D Q D Q

Q

A

O/P

100 n sec

100 n sec

10-bitRing Counter

4-bit

Parallelcounter

MOD-25

RippleCounter

4-bit

JohnsonCounter160KHz

I.C.

A

B

C

D

x

y

z

19. A shift register is shown in figure, if it counts 000 again, then no. of clock pulses required will be

(A) 3 (B) 4 (C) 5 (D) 6

20. If input - A at the AND gate is shown in figure and propagation delay of each NOT gate is 25 n sec

then what is the value of O/P of gate.

(A) Logic - 1 (B) Logic - 0

(C) (D) Same as given input

21. Which of the following statements are true about interrupt in 8085

1. There are 6, interrupts in 8085

2. Call-location of TRAP is 0024 H

(A) 1 - T, 2 - F (B) 1 - F, 2 - T (C) 1 - T, 2 - T (D) 1 - F, 2 - F

22. An 8-bit successive approximation ADC has full scale reading of 2.55 volt and its conversion time

for an analog input of 1 volt is 20 sec, what is the conversion time for 2v, input

(A) 10 sec (B) 20 sec (C) 40 sec (D) 50 sec

23. What is the freqn of pulse z, in the network shown in figure:

(A) 5 Hz (B) 10 Hz (C) 40 Hz (D) 160 Hz

24. A certain JK FF has tpd = 12 n sec the largest MOD ripple counter that can be constructed from these

FFS and still operate upto 10 MHz is

(A) 8 (B) 10 (C) 256 (D) Any No. of FFS

25. For implement of above expressions by given chip:

A = x y z

B = ' 'x yz xy z

C = ' ( ' ')xyz x y z

D = xyz

Given I.C can be implemented by:

(A) By 2 half adders & 1 full adder only. (B) By 3 half adders only

(C) By 3 Full adders only (D) By 3 half adders 1 OR gate.


26. The Boolean expression f(P, Q, R) = (0, 5) is to be realized using two 2 – input gates which are

these gates.

(A) AND & OR (B) NAND & OR

(C) AND & EX-OR (D) OR & EX-OR

27. Which of the following statement is not correct about ADC conversion time?

(A) Flash type ADC is the fastest ADC but conversion time depends upon no. of bits

(B) Counter type ADC has conversion time equal to N

c2 T where Tc is period of clock

(C) Successive approximation type ADC has conversion time equal to cN T where Tc is period of

clock

(D) Dual slope ADC is the slowest ADC and has the highest accuracy

28. A combinational circuit accepts a 2 bit binary number and output is square in binary. To design this

circuit using a ROM the minimum size of ROM required is:

(A) 2 2 (B) 4 2 (C) 4 4 (D) 2 4

29. A 6 bit R – 2R ladder DAC has reference voltage of 6.5 volt. It meets standard linearity then

calculate the range in output for input 011100.

(A) 2.79 – 2.89 volt (B) 2.74 – 2.94 volt (C) 2.70 – 2.80 volt (D) 2.75 – 2.85 volt

30. In a dual slope integrating type digital voltmeter the 1st integration is carried at for 10 periods of

supply frequency of 50Hz. If reference voltage used is 2 volt then total conversion time for an output

of 1 volt is:

(A) 0.1 sec (B) 0.2 sec (C) 0.3 sec (D) 0.4 sec

31. Consider the following statement about Cache memory:

1. Cache memory is based upon concept of locality of reference

2. Cache memory is slow but less expensive memory

3. Size of cache memory is very small

Which of the followings are correct:

(A) 1 & 2 (B) 2 & 3 (C) 1 & 3 (D) 1, 2 & 3

32. Which of the following statements are correct about various registers?

1. The register which contains the instruction to be executed is called as Index register

2. The register which keeps track of execution of a program and which contains the memory

address of instruction currently being executed is called as Program counter

3. The register which hold address of location to or from which data are to be transferred is known

as Memory Address Register (MAR)

4. The register which contains the data to be written into or readout of location is known as

Memory Buffer Register (MBR)

(A) 1, 2 & 3 (B) 2, 3 & 4 (C) 1, 3 & 4 (D) 1, 2, 3 & 4

33. Given that main memory access time is 1200 ns and cache access time is 100 ns if the average

memory access time is not to exceed 120 ns. The hit ratio for the Cache must be at least:

(A) 90% (B) 98% (C) 80% (D) 75%


34. Which of the following are included in the architecture of computer?

1. Addressing modes, design of CPU

2. Instruction set, data formats

3. Secondary memory, operating system

Select the correct answer using the codes given below:

Codes: (A) 1 and 2 (B) 2 and 3 (C) 1 and 3 (D) 1, 2 and 3

35. How many distinct binary trees can be constructed with three nodes?

(A) 1 (B) 2 (C) 3 (D) 5

36. Which one of the following statements are true about interrupts:

1. RST 7.5 is Edge sensitive

2. RST 5.5 is Level sensitive

3. INTR is non vectored interrupt

4. TRAP is Non maskable interrupt

(A) 1, 2, 3 (B) 2, 3, 4 (C) 1, 3, 4 (D) 1, 2, 3, 4

37. Which one of the following instruction is a 3 byte instruction:

(A) MVI A (B) LDAXB (C) JMP2050 (D) MOV A, M

38. A good assembly language programmer should use general purpose register rather than memory in

maximum possible ways for data processing. This is because

(A) Data processing with registers is easier than with memory

(B) Data processing with memory requires more instructions in the program than that with registers.

(C) Of limited set of instruction for data processing with memory

(D) Data processing with registers takes fewer cycles than that with memory.

39. Consider the following 8085 instructions:

ANA A, ORA A, XRA A, SUB A, CMP A Now consider the following statements:

1. All are arithmetic and logic instructions

2. All cause the accumulator to be cleared irrespective of its original number

3. All reset the carry flag

4. All of them are 1 byte instructions.

Which statements are correct?

(A) 1, 2, 3, 4 (B) 2 only (C) 1, 2, 4 (D) 1, 3, 4

40. INR instruction does not affect carry flag which one of the following is correct about INR

instructions:

(A) Overflow can’t be detected (B) Over flow can be detected

(C) If program requires overflow to be detected ADD instruction should be used instead of INR

(D) It can be used to increase the contents of the BC register pair.

41. Which of the following statements are correct:

1. Bus a group of wires

2. Bootstrap is a technique or device for loading first instruction

3. An instruction is a set of bits that defines a computer operation

4. An interrupt signal is required at the start of every program

(A) 1, 2, 3 (B) 1, 3, 4 (C) 1, 2, 4 (D) 1, 2, 3, 4


42. The interrupt vector table IVT of 8086 contains:

(A) The contents of CS and IP of the main program address at which interrupts has to be occurred

(B) The contents of CS and IP of the main program address to which to control has to come after

after the service routine

(C) The starting CS and IP value of Interrupt service routine

(D) The starting address of the IVT.

43. Which of the following statements are true about interrupt in 8085 microprocessor:

1. There are five interrupts in 8085 microprocessor

2. TRAP has the highest priority followed by RST 7.5, RST 6.5, RST 5.5 and INTR

3. All three RST and TRAP don’t require any external hardware i.e. they are automatically

transferred to specific locations without any hardware.

(A) 1 & 2 (B) 2 & 3 (C) 1 & 3 (D) 1, 2 & 3

44. Which of the following statement is not correct about interrupt in 8085 Microprocessor

(A) TRAP is edge as well as level triggered interrupt

(B) RST 7.5 is positive edge triggered interrupt

(C) RST 6.5&RST 5.5 are level triggered interrupts

(D) RST 6.5&RST 5.5 are negative edge triggered interrupts

45. Which of the following is not true about DMA transfer in microprocessor?

(A) It is direct transfer of data between memory and I/O devices without the use of microprocessor

(B) It is faster scheme for transfer of data from mass storage device & is also used for high speed

printers

(C) In burst mode DMA transfer I/O device withdraws request only after data bytes have been

transferred

(D) Cycle stealing scheme is same as burst mode transfer in DMA controller

46. Which of the following statements are correct?

1. READY signal in 8085 is useful when the CPU communicates with a slow peripheral device

2. In a microprocessor wait states are used for interface of slow peripherals to the processor

3. READY signal is used to delay the microprocessor read or write cycles

4. READY pin is an output pin

(A) 1, 2 & 3 (B) 2, 3 & 4 (C) 1, 3 & 4 (D) 1, 2, 3 & 4

47. Which of the followings are correct about INR and DCR instructions in 8085?

1. It affects contents of specified registers 2. It affects all flags except CY flag

3. Both INR and DCR are 2 byte instructions

(A) 1 & 2 only (B) 2 & 3 only (C) 1 & 3 only (D) 1, 2 & 3 only

48. Which of the following is not true about registers in 8085 Microprocessor?

(A) Both SP and PC are 16 bit registers used in 8085 Microprocessor

(B) PC always holds address of the next instruction to be fetched

(C) SP always holds the address of the top of the stack

(D) Accumulator is also 16 bit register in 8085 Microprocessor which is used to perform arithmetic

and logical operations.


49. A small code of 8085 as given below, is executed

MVI A, 7FH

ORA A

CPI A2H

The contents of the accumulator and flags after execution are

(A) A DD, S = 1, Z = 0, CY = 0 (B) A 7F, S = 1, Z = 0, CY = 1

(C) A DD, S = 0, Z = 1, CY = 0 (D) A 7F, S = 0, Z = 1, CY = 1

50. Which of the following statement is not correct about status of flag register in 8085 Microprocessor?

(A) The value of MSB of result following the execution of any arithmetic or Boolean instruction is

stored in the sign status flag

(B) In execution of XRA A instruction zero flag is set

(C) In execution of instruction SUB B sign flag must not be affected

(D) In execution of instruction SUB B zero flag may be affected

51. Which of the following pair is not correctly matched with regard to addressing mode?

(A) STA 2400H--------------- Direct addressing mode

(B) LXI H, 2500H------------Immediate addressing mode

(C) MVI A, 05-----------------Immediate addressing mode

(D) MOV A, B----------------- Register addressing mode

52. The following sequences of instructions are executed by an 8085 microprocessor:

1000 LXI SP, 27 FF

1003 CALL 1006

1006 POP H

The contents of the stack pointer (SP) and the HL, register pair on completion of execution of these

Instructions are:

(A) SP = 27 FF, HL = 1003 (B) SP = 27 FD, HL = 1003

(C) SP = 27 FF, HL = 1006 (D) SP = 27 FD, HL = 1006

53. Consider the sequence of 8085 instruction given below:

LXI H, 9258

MOV A, M

CMA

MOV M, A

Which one of the following is performed by this sequence?

(A) Contents of location 9258 are moved to the accumulator

(B) Contents of location 9258 are compared with the contents of the accumulator

(C) Contents of location 9258 are complemented and stored in location 9258

(D) Contents of location 5892 are complemented and stored in location 5892

54. In the following 8085 program how many times (decimal) is the DCRC executed?

MVIC, 78 H

LOOP DCRC

JNZ LOOP

HLT

(A) 119 (B) 120 (C) 78 (D) 77


55. Match List-I with List-II and select the correct answer using the code given below the Lists:

List-I List-II

A. 8255A 1. Programmable Peripheral Interface

B. 8279 2. Programmable Interval Timer

C. 8254/8253 3. DMA Controller

D. 8237/8257 4. Programmable Keyboard/Display Interface

Code: A B C D A B C D

(A) 2 4 1 3 (B) 1 3 2 4

(C) 2 3 1 4 (D) 1 4 2 3

56. Which one of the following is used as the interface chip for data transmission between 8086 and a

16-bit ADC?

(A) 8259 (B) 8255 (C) 8253 (D) 8251

57. x:=1; y:=0;

while y < k do

begin

x:=2 * x;

y:=y+1

end;

For the above Pascal program fragment involving integers x, y, and k, which one of the following is

a loop invariant; i.e. true at the beginning of each execution of the loop and at the completion of the

loop ?

(A) x = 2y (B) x = y +1 (C) x = (y+1)

2 (D) x = (y+1)

2y

58. Consider the following ‘C’ program:

main ( )

{

pri ( ); pri( ); pri ();

}

Pri ( )

{

Static int k;

print (“%d”, ++k);

}

Which one of the following is correct in respect of the program given above?

(A) It prints 012 (B) It prints 123

(C) It prints 111 (D) It prints 3 consecutive but unpredictable numbers

59. Consider a complete graph with n vertices. What is the total number of spanning trees?

(A) ( 1)

2

n n (B) 2n-1 (C) !n (D) 2nn

60. Which block replacement algorithm is not generally used in cache operation?

(A) LIFO (B) FIFO (C) LRU (D) Random


Engineering Service Examination -2014

SI No.

Electronics & Telecommunication Engineering

PAPER – Digital Electronics & Microprocessor

(Conventional)

Time allotted: 90 Minute Maximum marks: 100

INSTRUCTIONS

Candidates should attempt Question No. 1 which is compulsory and remaining FOUR from questions taking

two each from section-A and Section-B. The number of marks carried by each question is indicated at the

end of the question. Answers must be written only in English. Assume suitable data if found necessary and

indicate the same clearly. Values of the following constants may be used wherever necessary:

Electronic charge = –1.6 × 10–9

Coulomb

Free space permeability = 4 × 10–7

Henry /m.

Free space permittivity = 9110

36

Farad/m.

Velocity of light in free space = 3 × 108 m/ sec.

Boltzmann constant = 1.38 × 10–23

joule /K.

Planck constant = 6.626 × 10–34

joule-sec.

Important: Candidates are to note that all parts and sub parts of a question are to be attempted

continuously in answer book. That is all parts and sub parts of a question being attempted must be

completed before attempting the next question.

Any page left blank in answer book must be clearly struck out. Answers that follow pages left blank

may not be given credit.


CS

8255

A7

A6

A5

A4

A3

IO/M

A1

A0

I.C.

A

B

C

D

x

y

z

1. (a) An 8255 chip is interfaced to an 8085 microprocessor as an I/O mapped I/O as shown in figure

the address line A0 and A1 of 8085 are used by the 8255 chip to decode internally its three ports

and control register. The address lines A3 to A7 as well as the IO/M signals are used for address

decoding. The range of addresses for which the 8255 chip would get selected is (5)

(b) What are the function of the following pins of 8085 microprocessor (5)

(i) READY (ii) ALE (iii) HOLD (iv) TRAP (v) HLDA

(c) Design Mod-5 Ripple Down counter by use of JK-FFS and OR gates (5)

(d) Implement of given expressions by given chip in terms of adders and gate (if required) (5)

A = x y z

B = ' 'x yz xy z

C = ' ( ' ')xyz x y z

D = xyz

SECTION-A

2. (a) Compare weighted type and R-2R ladder by mentioning advantages and disadvantages (10)

(b) Design NAND and NOR gate by use of diode and transistors (10)

3. (a) Design a counter that has a repeated sequence of six states as given in the table below (10)

Count Sequence

A

0

0

0

1

1

1

B

0

0

1

0

0

1

C

0

1

0

0

1

0

(b) Design a combinational circuit that accepts a 3-bit number as input and generates an output

binary number equal to square of the input number (10)

4. (a) Reduce the expression

f(A, B, C, D) = m (2, 8, 9, 10, 11, 12, 14,) and implement the using NOR gates.

(b) Explain various parameters of logic family (2 × 5 = 10)


SECTION-B

5. (a) Write an 8085 ALP to find largest number in an Array. (10)

(b) Distinguish between (2 × 5 = 10)

(i) High Level Language and Low Level Language

(ii) Macro Programming and Micro-Programming

(iii) Machine Cycle and Instruction Cycle

(iv) Hardware Interrupts and Software Interrupts

(v) Memory mapped I/O and I/O mapped I/O.

6. (a) (i) Explain with the help of a flow- chart “cycle stealing” and “burst mode” data transfer

schemes used in computing systems. (5)

(ii) What is the significance of the term “memory – hierarchy pyramid” with respect to a

computer system? Justify the term in terms of cost, speed and space with respect to its

components by using the diagram. (5)

(b) How many interrupt lines are there in Intel 8085 ? Name them in order of priority. Give their

restart location also. (10)

7. (a) Write a ‘C’ program (with comments wherever suitable) to convert a line of lowercase letters to

uppercase letters. (10)

(b) An assembly language program is given below : (10)

MVI A, B5H

MVI B, 0EH

XRI 69 H

ADD B

ANI 9BH

CPI 9FH

STA 3010H

HLT

What is the status of ‘carry’ and ‘zero’ flags after the execution of the program?


1 1

1 1

1 1

00 01 11 10

00

01

11

10

1 1

IES-2014 Test-5 : Solution:

1.(A) Z = A B AB

By truth – table, Z = (A + B)

2. (A)

3 2 1 1

3 2 1

16 2

4 4096 9 257 7 17 4 9 1

4 16 9 (16 1) 7 (16 1) 16 2 4 1

4 16 9 16 10 16 5

(49A5) (0100100110100101)

So No of 1’s will be 7 .So No of 0’s will be 16-7=9

3. (C) 1 0

bX 54 5.b 4.b 5b 4

x 7 x 49 5b 4 49

5b 45 b 9

4.(A) Fan-out = 0.2

50.04

Fan-in = 16

101.6

Smaller of both Fan-in & Fan-out will be required Fan-out

5.(D) Just solve by K-Map all 4 options then compare.

6. (B)

AND operation means Intersection of Min terms and OR operation means Union of Min terms

7. (A)

Rule: Let n = variable of K-Map

2m

= 8 m = 3.

number of terms in minimised group = n–m

m no of bits for pairing.

mn 8 2 32 & m 5

n m 8 5 3

8. (B) XS 64 Addition of 64 used for 7 bits.


1 1 ×

1

× 1

1 11

00 01 11 10CD

AB

00

01

10

11

1 1

00 01 11 10BC

A

1 1

A

BC

Minm

no will be 0 Maxm

no = 27 –1 = 127

Range willbe 0 to 127

0 64 to 127 64 & 64 to 63

Similarly XS 32 Range 32 to 31

Bit = 6& Range 0 63

6i

i

i 0

XS 64 e 64 2 e

&5

i

i

i 0

XS 32 e 32 2 e

9. (B)

Y ABC AD BD CD

10. (D)

A AB AC

POS will be 0,2,4,5

11. (D) 3Input EX OR

If in i/p even no of ‘1’s are present then o/p = 0

If in i/p odd no of ‘1’s are present then o/p will be 1.

Truth table

A B C A B C A B C A B C

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 0

1 0 0 1 1

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1


ABC

A

BC

AB

C

A

BC

(1)

(2) (3)

AB

C

A

BC

1

1 1

1

00 01 11 10CD

AB

00

01

11

10

1

1

1

00 01 11 10

0

1

1

1 1

11

1

A B C A B C A B C A B C A B C

0 0 1 1 1

1 1 0 0 0

1 1 0 0 0

0 0 1 1 1

1 1 0 0 0

0 0 1 1 1

0 0 1 1 1

1 1 0 0 0

A B C A B C

A B C

Conclusion for 3 input XOR:

Conclusion for 3 input XNOR:

12. (A)

f A,B,C,D 4,5,8,12,13,14,15

It has ‘3’ prime Implicates

A prime implicate is said to be EPI if it covers at least one minterm which is not covered by other prime

implicates. f A,B,C,D 0,2,3,4,5,7

This prime impeccant is also known as cyclic prime implicates

13. D CMOS has most of the advantage except speed .Highest Noise margin is in HTL but after that it is

CMOS. CMOS has the lowest power dissipation.


xyz

ABCD

I.C

HA

HA

HAx y z

(xy +yx )z

xy z

xyz

c=xy

S=x yx

y

14.( B)

Q1 Q0

0 0

J0 = 1, K0 = 1, J1 = 0, K1 = 1 Q0 = 1, Q1 = 0

J0 = 1, K0 = 1, J1 = 1, K1 = 0 Q0 = 0, Q1 = 1

J0 = 0, K0 = 1, J1 = 0, K1 = 1 Q0 = 0, Q1 = 0

So 00 01 10 00 (MOD – 3)

339/3=113 so after 339 clock cycles it will be reset to zero.

15.(C) f(A, B, C) = (A+C) (B+C)

16.(D)

17. (D)

For both values of X=1 and Y=1 Q and complement have same values so these

state will be unstable.

18. (D) For both values of X=1 and Y=1 Q and complement have same values so these

state will be unstable.

19. (D) It is a MOD-6 counter as it is Johnson counter.

20. (B) In 50 n-sec delay 1 will become zero and zero will become 1 so in AND operation zero will

always will be available and hence output will be zero only.

21 . (B)

22. (B) Conversion time is independent of input voltage . So it will not be changed when it is changed from

1 V to 2V.

23. (A) 10 bit ring counter means Mod-10 counter.

4 bit parallel counter means Mod-16 counter

4 bit Johnson counter means Mod-8 counter

24. (C)

25.( B) A = x y z

B = z(x y)


PQR

00 01 11 10

0

1

0

0

ROM

if ‘P’ add. lines‘N’ is the no of O/P bit

b3 b2 b1 b0

2 ×4

= 4×4 should be

2

A B

26.( D) f (P, Q, R) = (0, 5)

f(P, Q, R) = (P+Q+R)

( )P Q R

f = Q + P R

27. (A) Conversion time never depends upon no of bits in case of Flash type ADC

28. (B) Size of ROM = M×N

PM 2 : P Address Lines

3 2 1 0A B b b b b

0 0 0 0 0 0

0 1 0 0 0 1

1 0 0 1 0 0

1 1 1 0 0 1

Size of ROM = PM N 2 N

size of ROM = 4 2

For 3 bit Square ROM Size of ROM must be = 8 × 4

For 4 bit Square ROM

29. (A) 1

0 1 0.22

NRN

VV b b

N

= 4 3 2

6

6.52 2 2 2.84

2volt

m 1Max deviation is 0.05

2LSB volt

6.50.1

2 64

R

n

VLSB V

2.84 0.05Range of out put voltagewill be

30.(C) In a dual slope integrating type digital voltmeter

1

in ref

Tv v

T where T1 is first integration time


I/OProcessor

m/m

Cachem/mCPU

1

12

110 0.2sec

50

1 , 2

1 0.20.1sec

2

in ref

in

ref

T

v v v v

v TT

v

31. (C)

32. (D)

33. (B) Average memory access time = H C 1 H M C

120 H 100 1 H 1300

1200H=1180

118H 98%

120

34. (A)

Visible thing Architecture

Non visible things organisation

The thing which changes with time is called as organization

The thing which remains same with time is called as Architecture

35.(D)

No of distinct binary tree nc2n

n 1

For n = 3

3C6 6

4 3 3 4

6 5 4

3 2

5

1 4

36. (D)

37. (C)

38. (D)

39. (D)

40. (C)

41. (A)

42. (C)


43. (D)

8085 interrupts:

TRAP, RST 7.5, RST 6.5, RST 5.5, INTR are the 5 interrupts:

All three RST & TRAP don’t require any external hardware i.e. they are automatically transfer to specific

location. In case of INTR there is need of INTA signal for transferring m/m location.

10

RST4.5 8 36 H

24

10

RST 7.5 8 60 H

3C

RST 10

6.5 8 52 H

23

RST H105.5 8 44 (2C)

Priority order of Interrupts in 8085:

TRAP RST7.5 RST6.5 RST5.5 INTR

TRAP has lower priority than Hold signal used by DMA.

TRAP Both level & edge triggered

RST 7.5 edge triggered

RST 6.5, 5.5 & INTR level triggered

INTR: RST 0 00H

RST 1

RST 2

:

:

RST 7 (38H)

Maskable & Nonmaskable Interrupt:

Masking is always done from soft ware.

Interrupts which can be made ineffective are maskable interrupt

Trap can’t be done enable or disable this is not accessible for user and is generally useful for emergency

operations.

Software and Hardware Interrupt:

Interrupts caused by i/p & o/p devices are known as hardware interrupts

Interrupts caused by internal condn or special instruction are known as s/w interrupts

eg. RST n instruction is a s/w interrupt. Program will be executed up to the point where RST ‘n’ instruction

is inserted.

44. (D)

45. (D)

DMA transfer scheme:

In this case CPU doesn’t participate and data are transferred directly from input device to memory &

vice-versa.

In this case data transfer is controlled by input device or DMA controller.

This scheme is generally employed when large amount of data is to be transferred

Working of DMA:


An input & output device which wants to send data using DMA will send a request HOLD to CPU. On

receiving hold signal from input output device CPU gives control of bus as soon as current cycle is

completed.

Now CPU will send an acknowledgment signal to input output device to indicate that it has received the

whole signal and released busses

Now DMA will take control of bus and will send data or received data by use of DMA controller. For small

data BURST mode is used. For large data cycle stealing mode is used.

There are two type of modes:

(i) BURST mode transfer

(ii) Cycle stealing

BURST Mode: I/P O/P device draw DMA request only after data has been transferred. By this technique a

block of data is transferred.

Cycle stealing: This is used for transfer of non block of data and here steal bus cycle from CPU when ever it

is not using s/m bus.

46. (A) READY pin is an input pin here READY Signal is used to delay, up read or write cycles until a slow

peripheral device is ready to send accept data. Once peripheral device becomes ready to transfer data then

Ready pin becomes high.

47. (A) INR &DCR are 1 byte instructions

48. (D) Accumulator is an 8 bit register

49. (B) MVIA, 7FH A 7F

ORA A A 7F

CPI A2H CPI compare data immediate with Accumulator

A = 7F <A2H

50. (C)

51. (B) If LXI H, 2500 is immediate addressing mode

LXI H, 2500H Register indirect addressing mode

52. (C) 1000 LXI SP, 27FF

1003 CALL (–2) 1006

1006 POPH (+2)

SP, HL

53. (C) LXI H, 9258H 9258 is located in HL

MOVA, M Contents of 9258 address is transferred into Accumulator

CMA It will complement data of 9258 address

MOV M, A Complement of A is stored in 9258

54. (B) 178 7 16 8 120

DCRC 120 1 119

Total cycle = 119 + 1 = 120

55. (D) 56. (B) 57. (A)

58. (C) 59. (D) 60. (B)

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