technology development methodology – cmos as a game-changer

Presenta)on at the 6th Workshop of the “IIPCC HK Chapter IP Workshop Series: IP’s Role in Entrepreneurship & Innova)on” (in HKSTP on February 11, 2015)

Prepared by: Al Kwok (郭灿辉) Governor & Co-‐founder, IIPCC Hong Kong Chapter Governor & Co-‐founder, HKIURCA (⾹香港產學研合作促進會) Member, HKSAR “IP Trading” Working Group

Governor & Co-‐founder, Savantas Policy Ins)tute President, CASPA (华美半导体协会) PRD Chapter Former VP & CIPO, NetLogic Microsystems (“NETL”)

Technology Development Methodology - CMOS 1

Technology Development Methodology – Making CMOS

the Game-Changer!

Feb. 11, 2015

Acknowledgement n  Innovations in IC industry have been

collaborative efforts. n  I am indebted to my colleagues and co-

workers at IDT for their assistances and supports for developing my early career to acquire the needed domain expertise as a “Yield Guru” to be a pioneer launching the Information Age – driven by the Moore’s Law and Metcalfe’s Law scalability.

Feb. 11, 2015 Technology Development Methodology - CMOS 2

Outline n  The Impact of CMOS: How & Why?

n  As basic to “Information Age” as “Wheel” to “Early Civilization” n  IDT (founded by Indian & Chinese, first in Silicon Valley) made history

n  The Basic in Technology Development n  The Big Picture: How it fits in? From Corporate and Individual perspectives n  Process, Building Blocks, Organization/Lay-out n  Supporting Equipment, Infrastructure & Ecosystem

n  The Methodology of Tech. Development – Product/Yield Driver! n  Yield (Profitability & Manufacturability) as the Initial Focus, then

Quality and Reliability n  The Learning Curve – Yield Optimization & Iterations

n  Tools: Yield & Failure Analyses, H/W, SPC, CPK n  Critical Skill-sets: Root-cause Analyses, DOE (Design-Of-Experiment),

Solution Formulation, STR learning cycles n  Critical Success Factors:

n  Baseline, STR, Human, Team, Time, Data, Tools, etc.


CMOS (Complementary Metal Gate-On-Silicon Invertor) – the “Wheel” of Information Age


The Core Value of CMOS (Patents?!)

CMOS is the “Wheel” of “Information Age” n  Basic switch: the Simplest implementation of “1” or “0”

n  The most basic in the Digitization World (IC Designs) n  Signal integrity: the Best, to “Vcc (Power)” & “Gnd” levels n  Power: the Lowest, only switching current (& no DC) n  Structure: the most Fundamental (time invariant)

n  4 terminals: Input, Output, Vcc (Power) and Ground (Zero Ref.)


Latch-up is the Achilles’ heel

Feb. 11, 2015 6

The CMOS Low Power Advantage (2005) Picture was taken on September 7, 1983 by A. Kwok (IDT) for a Fortune Magazine article about IDT (Integrated Device Technology) and CMOS technology published on the Oct. 17, 1983 issue (P.85) written by Gene Bylinsky. IDT went IPO in Feb. 1984 on CMOS.

Source: “(Silicon Valley) High Tech – Window to The Future” (Gene Bylinsky)

Technology Development Methodology - CMOS

Feb. 11, 2015 7 Source: Intel Presentation

Moore’s Law as the growth engine of hardware platform: IC cost reduction by 50% in every 18 months or less

CMOS power scaling => Feature size scaling Feature size scaling => Price scaling The secret behind scaling: Price can drop because power can be reduced!

Technology Development Methodology - CMOS

Source: Intel Presentation

This future of semiconductor industry could not happen w/o CMOS!


IDT Founders’ Spin-off (Serial Entrepreneurs) 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001

Al Kwok AMD AMD AMD A/I IDT IDT IDT IDT VTI QSI QSI QSI QSI QSI QSI Self PMC P/N NMI NMI NMI NMI #256 # 7 # 7 # 10

George IDT IDT IDT IDT IDT IDT Clon Laws Huang Frank Lee IDT IDT IDT IDT IDT IDT IDT PSI PSI PSI PSI PSI PSI PSI GVT GVT GVT GVT GVT GVT G/C Norm IDT IDT IDT IDT IDT IDT IDT PSI PSI PSI PSI PSI PSI PSI PSI Nova Nova NMI NMI NMI NMI NMI Godinho Chun Chiu IDT IDT IDT IDT IDT IDT IDT IDT QSI QSI QSI QSI QSI QSI QSI QSI QSI QSI QSI Q/I Mano HP HP H/I IDT IDT IDT IDT IDT QSI QSI QSI QSI QSI QSI QSI QSI QSI QSI Malwah Varad ? ? ? ?/I IDT IDT IDT IDT QSI QSI QSI QSI QSI QSI QSI QSI Nova NMI NMI NMI NMI NMI Srinivasan Jen Hong ? ? ? ?/I IDT IDT IDT IDT QSI QSI QSI QSI QSI QSI QSI QSI ? NY NY NY NY NY

Feb. 11, 2015 9 Technology Development Methodology - CMOS

n  Collaborative Innovations leads to Co-founders n  Entrepreneurs create their own jobs n  Serial Entrepreneurs are the major job creators and new

engines of GDP – treasure of a Knowledge-based Society n  IDT (CMOS) & NMI (KBP) enabling IT, impacting >>$10T GDP globally

Technology Evolutions Encountered n  IDT (w/ its own fab): Mil. grade; Fastest speed

n  CEMOS I (1981-4, 2um): yield improvement only n  Contact mask -> Projection mask, no redundancy, <30% yield n  100% Wet Etch, Poly gate, 1 layer metal (evaporation)

n  CEMOS II (1984-5, 1.5-1.2 um): T.D. & P.D. n  Projection mask, Dry & Wet etch, Silicide gate, Implant, Sputter

n  CEMOS III (1986, 1.2-1.0 um): T.D. & P.D. n  Stepper, Dry etch, Contact plug, 2-metal, Ldd…

n  BiCEMOS I (1987, 0.8um): 10 ns (T.D. & P.D.)

n  Quality Semiconductor Inc. (@ SII & Yamaha) n  Ultra-fast CMOS (1989-90, 0.5um), Idsat ~ 450uA/um

n  With back bias (charge-pump ~0.5 mA) – negative feature! n  FCT yielded >95% @ W/S in SII within 1 year (skipped W/S)

n  FCT @ F grade; SRAM @ 10 ns (the fastest) Feb. 11, 2015 Technology Development Methodology - CMOS 10

Migration to Low-Power (Battery) Applications


Portable Battery Operated Devices were dominating since 1990 Low Power IC’s were dominating!

Technology Development Principles – the Survival Guide


The Learning Curve – Core of Tech. Dev. n  In any situation, the Learning Curve starts:

n  Where we are: What is the baseline? n  Where should we go: What is the direction for

improvement? What should be the DOE? n  Repeating the process until we achieve our objectives

n  Improvements by iterations based on DOE n  DOE must be Well-Conceived (multi-disciplinary!)

n  Winner gets more data with less DOE within less time

n  Iterative optimization to pin down the global optimal point(s) of operation w/ least effort (by experimenting)

n  There is No Failure in an iterative process n  We Only FAIL, if we GIVE UP (Learning) n  Chinese create their own worst enemy by seeing

iterations (iterative optimizations) as “Failures” Feb. 11, 2015 Technology Development Methodology - CMOS 13

The Big Picture for Technology Development

Lead Customers’ Requirements => 2nd G => 3rd G =>…

Differentiating Value Creations => 2nd G => 3rd G =>…

Business Model => 2nd G => 3rd G =>…

Service/Product Roadmap => 2nd G => 3rd G =>…

Application/Technology Roadmap => 2nd G => 3rd G =>…

IP Portfolio Development => 2nd G => 3rd G =>… The next innovation ideas come from customers (CRE) & “Stress Tests” identifying (1)  The weak-links in product design & performance and scalability (2)  System (architecture) integrity and scalability (elasticity) issues (3)  The bottlenecks for scalability (technology and manufacturability roadmap) NetLogic Microsystems is a good benchmark for SMEs as innovators

Close collaboration between the customer (CRE) and the vendor Mission-&-Time Critical Requirements along Demand-chain

Technology Development Methodology - CMOS 14 Feb. 11, 2015

Differentiating Value Creation ó Innovation n  Values (to Customers) to get paid - Maximizing

n  Performance/Power n  Max. performance at a low (specific) power

n  Performance => speed + functionalities (features)

n  Battery power for portability, anywhere and anytime n  Personalization

n  Quality/Reliability => High Yield too!! n  Food safety assurance is an universal pressing issue

n  Delivery => throughput time + logistics + zero waiting n  Just-In-Time + Mini. Process time + Mini. Handling time

n  Price => Priced according to values instead of costs n  Price = “Brand (Trust) + Emb. IP + Services” + Cost > 4X Cost

n  IP = “Brand (Trademark) + Embedded IP (Patents & Copyrights) + Pre-sale Design Win & Post-sale Services (Trade Secrets)”


Product/Tech. Dev. & Intro. Methodology


New Technology

Collaborative Innovation

T.D.

Differentiate Tech. vs. Product Development n  Product is a “physical” object deliverable to customers n  Technology is the means to make the Product

n  Transparent to the customer

n  Technology Dev. needs Product Vehicle – Yield Driver n  Ideal Yield Driver facilitates Yield Improvement & Failure Analyses n  Close collaboration among key engineers is paramount


CEMOS II Fab Production Transfer Integration: J. Hong

CEMOS II / 6116X Product Development Prod. Engr.: A. Kwok

CEMOS II Technology Development T.D. Architect: M. Malwah

Yield/Quality Reliability

CEMOS II Products Product Development Prod. Engr.: Others

Yield Improvement & Failure Analysis Data

Technology Development Deliverables n  New Technology Development (process, package

or test) key factors: n  The Process (technology) to make the product

n  Process Flow - End-to-end Integration to make the Product step-by-step, including:

n  Process Modules (Specific equipment operations) n  The floor-plan (equipment lay-out) of Production Line

n  The Characteristics of the Building Blocks (Elements) n  Electrical Design Rules (EDR) - Device Modeling

n  Active components & passive components to make the Products n  For whole Product (IC) simulation (behavior prediction)

n  The Arrangements of the Building Blocks n  Topological Design Rules (TDR) - Layout Rules

n  How to pack the building blocks closer to make Products – CD’s! n  Such that the behavior modeling (EDR) still valid!


Technology Development – the Survival Guide:

How to be the Champion?


T.D. Methodology: Increasing Difficulties (I) n  I) Devices (circuit elements) work individually:

n  Behave well - perform as expected n  Individual-element Manufacturable - reproducible, spatial invariant n  Reliable - no appreciable degradation due to W/C operational stresses.

n  II) Process architecture sound - best case integration: n  Devices can work together to perform (logical) circuit functions. n  Easy topography, wide separation. n  Minimum proximity effects - only allow 1st and 2nd order effects, higher

order effects are excluded. n  Less stringent on equipment performance requirements on consistency,

uniformity, resolution, etc. n  III) Process manufacturability acceptable – W/C integration:

n  Circuit functions properly (logics and timings). n  Conform with all topological design rules (including W/C). n  Evaluate lots of proximity effects - higher order effects. n  Equipment meet all design rule performance requirements.


T.D. Methodology: Increasing Difficulties (II) n  IV) Yield/performance optimization & Q/R qualification:

n  1) ≥ 50% wafersort yield (with redundancy) demonstrated n  No systematic yield limiter. Yield is limited by random defects.

n  2) > 90% Pre Burn-in yield (at post packaging process) n  3) > 95% Post Burn-in yield (after 160 hrs. Vccmax burn-in) n  4) > 75% Military yield (to 10% Vcc variation @ 125C) n  5) > 30% yield to the fastest grade (also depends on design) n  6) Acceptable lifetest (HTOL) results (up to 2000 hrs.) n  7) No appreciable parametric shifts after 2Khrs. HTOL (trade secret)

n  Monitoring Iccsb, Iol, Ioh, taa, Icc, etc. n  8) Pass all required Groups B & D MIL-STD-883 tests n  9) Acceptable reliability results on ESD, latch-up, soft-error, hot-electron

effect, etc. (internal requirements) n  10) Good metal integrity and contact step coverage ≥ 40% (past) n  11) Tolerance to X-ray (Co-60) radiation ≥ 40 Krad (Si) (prepare for Class S

requirement)


1988 notes

Technology Dev. (IC) Analytical Tools (I) n  I) Fab Process Control / Monitor:

n  Prometrix Defect Monitor n  Emission Microscope Analysis Workstation n  Semiconductor Parameter Analyzer (HP 4145) n  Parametric Testers

n  II) Reliability Control / Monitor: n  Wafer-level Reliability Monitor. n  Emission Microscope Analysis Workstation n  Semiconductor Parameter Analyzer (HP 4145)

n  III) Product Evaluation / Design Verification Tools: n  Dynamical Voltage Contrast and E-beam Prober n  Emission Microscope Analysis Workstation n  Micromanipulator with long working length lenses & hot-chuck n  Laser Line-cutter; Digital and Real-time Oscilloscopes n  Semiconductor Parameter Analyzer (HP 4145) n  Curve Tracer n  Power supplies and Multi-meters n  Function (word) Generator and Logic Analyzer n  Bench Tester.


Technology Dev. (IC) Analytical Tools (II) n  IV) Yield Improvement/ Failure Analysis Tools:

n  Wafermap Capability n  Bitmap Capability n  Infra-red Microscope n  Liquid Crystal Hot-spot Detection Kit; Emission Microscope Analysis Workstation n  Semiconductor Parameter Analyzer (HP 4145) n  Failure Analysis Lab:

n  Plasma (preferably with Reactive Ion etching capability) Etcher n  Wet Chemical Sink n  Micro-sectioning Station n  Microscope (bright field, dark field and Nomarski) n  SEM:

n  Secondary Electron (SE) mode n  Voltage Contrast (VC) mode n  Backscatter Electron (BE) mode n  Electron Beam Induced Current (EBIC) mode

n  Dispersive X-ray (EDX & WDX) n  Auger Microscopy


The Baseline (Data) Progression n  Existing Baselines (Reference points for Learning Curves

for yield improvement) n  Success Data Base (wafer lot basis) n  High-low analyses (with Student-t statistics)

n  Highest 1/3 vs. Lowest 1/3 n  Significant parameters (process variations affecting yields)

n  Design-of-Experiment (DOE) - for improving baseline n  Optimization for yields/reliability/speed/power improvements n  STR (Special Test Run) as the vehicle: Super Hot Lots, Hot Lots n  Well-coordinated efforts to expedite, test, analyze and learn STRs n  STR to qualify new process flow, steps, modules and equipment

n  New Baseline (B/L) established by at least 2 STRs n  Need at least eq. 1000 hrs lifetest to prove reliability (w/ stress tests) n  Must be very carefully to switch into a new baseline!!


Baseline Data (I)


Key Information & Data Prd./Prc. Yield Nature of problems Char. Imprvmt. Systmtc. Random

I Key governing documents: B/L 1 Electrical Design Rules X X B/L 2 Topological Design Rules X X B/L 3 Process (flow) specifications X X

II Design: B/L 1 Circuit schematics X B/L 2 Simulation data vs. spec. X Maybe X B/L 3 Layout plots: composite and single-layer X Maybe X B/L 4 DRC: violations and marginality X Maybe X B/L 5 Parasitics extraction / back annotation X Maybe X Maybe B/L 6 Clock distribution layout X Maybe X Maybe B/L 7 Data bus routing layout X Maybe X Maybe

III Process: 1 Process device parameters (electrical) X X X

B/L 2 Device paramter trend-charts 3 Process defect monitors (physical) X X Maybe Maybe

B/L 4 Defect monitor trend-charts 5 Lot traveler (overall history) X X X 6 Run cards (at individual process step) X X Maybe Maybe

B/L 7 Station log (status of equipment) X X Maybe Maybe B/L 8 Equipment SCM trend-charts X X Maybe Maybe

9 Problem log / Eng. disposition record X X X

Baseline Data (II)


Key Information & Data Prd./Prc. Yield Nature of problem Char. Imprvmt. Systmtc. Random

IV Wafersort / laser repair: 1 W/S test traveler (overall yield summary) X X X X 2 W/S test summary (for individual wafer) X X X X

B/L 3 W/S yield trend-charts (product/process) X Maybe Maybe 4 Wafermaps: composite and single X X X X 5 Bitmaps: composite and single X X X X

B/L 6 Success data base X X X 7 Correlation test procedure/record X X 8 Test hardware log/record X X

V Assembly (packaging): 1 Eng. build inst. (Eng. split lot traceability) X Maybe

B/L 2 Assembly yield trend-charts X Maybe Maybe

VI Class Tests (at Pre B/I, Post B/I and Temp. test): 1 Test Traveler (execution to Eng. inst.) X X X X 2 Test summary (individual split yield data) X X X X

B/L 3 Test yield trend-charts X Maybe Maybe 4 Correlation test record X X 5 Separate into bins (speed grades) X X 6 Reject analyses and correlation X X X 7 AC reject characterization X Maybe X Maybe 8 Speed bin characterization over temp. X Maybe X

Root-cause Analysis – e.g., IC Industry n  Observability is essential at all critical steps

n  Insert adequate test points along the entire process n  Each test result must reflect specific physical phenomena (the acid test!)

n  Capable to pin down to a single variable conclusively n  Overall systematic test points correlation (triangulation for the root-cause)

n  Technology ó (Process Flow/mod. + Elect. D/R + Layout D/R) ó Product n  Need to differentiate Technology vs. Product issues


Wafer (wafer level)

W/L Process (Fab.)

Laser Repair (Redundancy)

Assembly (Packaging)

Burn-in Vmx 125C 160hrs

Post L/R Wafersort

Wafer (die level)

Packaged unit

Wafer -> Dice -> Pack’d unit

Pre B/I Class Test

Post B/I Class Test

Pre L/R Wafersort

Elec. Test Device Para.

Lot Traveller Run Cards

Wafersort Summary

Assem. Lot Summary

B/I Lot Summary

Product Product Product Product Technology

Wafersort Flow for Tech Driver (SRAM) n  Open (check continuity = probe card OK)

n  @ -0.5V, Imea > 100mA n  Short - All pins except Gnd are at Vcc (CS & OE = Off) n  Two-bit (write A D, read A D, write Abar Dbar, read Abar Dbar)

n  Check all decoders, all peripheral circuits n  Gross Functional (Vcc, Vcc/0, 0.5Vcc/0.5Vcc, f > 2 fmax)

n  Address Complement March – any failing bit? n  Gross Funct. (Vccmin, Vihmin/Vilmax, Volmax/Volmin) ó Vihmin/

Vilmax & Volmax/Volmin DC tests n  Current measurements:

n  Iccmax (Vccmax, Vcc/0, 0.5Vcc/0.5Vcc) n  Isb(CS=Off, Vccmax, dynamic timing) n  Isb2 (CS=Off, Vccmax, static) n  Iin (measure gate leakage) n  Ioh/Iol (optional) – great correlation with Idsat

n  Data Retention check – proving each cell can hold data @ power-down


Integrated Solution Formulation (2005) Key Design Considerations

Noise (Low)

Performance (High Speed & Features)

(Low) Power

(High) Density (/area)

Yield/ Reliability

(High)

Form Factor/ Thermal Stress

(Small & Robust)

Reducing Overall

Cost to End Customers

Sys

tem

Inte

rface

Fac

tors Fab Technology Factors

Package Technology


"Design-in Methodology” for "Doing the Right Things Right at the First Time" mindset (to proactively solve problems at their sources of creation) to enable "First-Silicon” Success: Marketability, Scalability, Robustness, Manufacturability, Reusability, Quality/Reliability, Testability, etc. – All for “Integrated Design Capability”

Costs to Society is the Wildcard

A Process Control System


Process Optimization and Control n  Process Integration

n  Device architecture and engineering to EDR & TDR

n  Process Modular Development n  Masking, etches, implants, diffusions, thin films, interconnects

n  Process Development Methodology n  Process characterization

n  Actual vs. Stimulation; Build Success Data Base n  Process (equipment) capability determination

n  CD variation vs. yield: Find yield cliffs for equipment controls

n  Process optimization n  Optimization of yields/speed/power and process windows

n  Process Control n  100% Critical Variables with Cpk > 1.5 & Cp > 2.0


STR (Special Test Run) Evaluation Roadmap & Methodology


STR Evaluation Roadmap


n  Test flow is designed to pinpoint problem a variation step at a time

n  Non-destructive stress tests are needed for early warning system

n  The worst problem is the walking wounded causing reliability problem – need to screen them out

n  Quality overrides yield – better to reject good than to accept failure

STR Evaluation Methodology (I) n  I) Process Evaluation:

The following information must be collected systematically and diligently by Fab Engineering and/or Technology Development and made easily accessible: n  Post metal electrical data: E.T. (Electrical Tests), defect monitor data,

etc. n  In-line process control data: CD measurements, thickness

measurements, sheet resistance measurements, etc. n  Run problem logs: Engineering Hold Cards, Q.C. Inspection Records

and Run History Card, Sort Alert Card, etc. n  Experiment records: Engineering Split Information, STR (Special Test

Run) Description, STR data (measurements, photos and SEM), etc. n  II) Wafersort:

The following practices are imperative for STR evaluation or yield improvement: n  A) Yield data - wafersort result: The individual test must be well

designed to both: n  1) Verify if the (gross) product specifications are met n  2) Monitor specific device, process or design problem


STR Evaluation Methodology (II) n  B) Yield analyses:

n  1) Yield comparison to the Success Data Base (SDB) as the baseline reference. n  2) Statistical analysis (mean and sigma calculation) on key W/S yield/failure, PCM

(device & defect) and process parameters (in-line process control data) n  3) High/low (yielding wafer) data comparison analysis to determine the key

cause(s) for yield variation within the lot by: n  a) Separate the highest and lowest yielding wafers into 2 groups -- minimum 7 wafers

each. n  b) Apply Student-t statistics to identify the key parameters that affect yield most. n  c) Proceed with wafermap and bitmap comparison analyses if needed.

n  C) Wafermap analysis: n  1) Generate a map on the wafer sorted to indicate the W/S yield or failure

category of an individual die. n  2) Generally, there are 2 kinds of wafermaps:

n  a) Single wafermap of an individual die. n  b) Composite wafermap of a group of wafers on a single (or a set of) yield or failure

categories. n  3) Yield/failure pattern study can show if yield is limited by any systematic

problem: e.g., a repeating failing die can indicate mask or masking defects. This is a necessary check to qualify new masks.

n  4) High/low analysis with wafermap is a very powerful tool. n  n  Feb. 11, 2015 Technology Development Methodology - CMOS 35

STR Evaluation Methodology (III) n  D) Bitmap analysis (for memory products only):

n  1) Generate a map (according to address and data locations) of failing bits (to a specific functional test/condition) on an individual die.

n  2) Generally, there are 2 kinds of bitmaps: n  a) Single bitmap of an individual die. n  b) Composite bitmap of a group of dice.

n  3) Bitmap pattern study can show if yield is limited by any systematic problem: e.g., a (or a set of) repeating failing bit(s) can indicate mask or masking defects. This is a necessary check to qualify new masks.

n  4) Failing bits are to be categorized according to specific "patterns": column, row, pair, cluster, line, etc.

n  5) Each failing bit pattern category is to be analyzed with Strip-back visual/SEM inspection.

n  6) High/low analysis with bitmap is a very powerful tool. n  7) Defect density can be estimated by counting and visual identification

of the failing bit patterns.


STR Evaluation Methodology (IV) n  E) Strip-back visual inspection:

n  1) Select the sample (representing specific failing category/pattern) from wafermap and bitmap analyses

n  2) Use wafermap and bitmap to locate the failing memory cell and see if the defect is visible.

n  3) Etch back the wafer layer-by-layer one at a time to identify the defect (with high resolution microscope and SEM) with comparison to the adjacent good cell.

n  4) The etch-back should be well controlled with proper wet chemicals or plasma etch. Sometimes, staining is needed to "highlight" the defect -- e.g., silicon pits.

n  5) Make sure no artifacts are introduced in the process. n  6) Identified defects should be categorized w.r.t. the failing bit

patterns for consistency check and future reference.


STR Evaluation Methodology (V) n  F) Integrated data cross-check and further investigation:

n  1) All data (including the process data) must be mutually consistent (not contradictory) and supportive.

n  2) The sources of major yield problems must be identified and fixed, whether they are related people (e.g., human errors), equipment, materials, methods (e.g., specification problems), or environment.

n  H) Case record publishing and filing: n  1) The findings must be communicated, discussed and digested for:

n  a) prevention of recurrence -- top priority n  b) assessment of the impact on all affected products -- for proper containment and

disposition. n  c) future process/design improvements.

n  2) The case record with all data and photos must be filed properly - they are the treasure of the company.

n  I) Comments: n  The investigation and analyses at wafersort are inter-related and sequential --

the previous one followed by the next one, n  E.g., the hi/lo yield analysis guides the wafermap analysis, the wafermap

analysis guides the bitmap analysis, the bitmap analysis guides the strip-back visual inspection and so on.


Closing Remarks n  Technology Development Leadership is indicative of a well-

coordinated learning organization progressing with solid baselines and well-conceived iterative optimizations to achieve maximum results with minimum efforts within the shortest time.

n  Collaborative Innovation is paramount as the product goes through various stages of different domain expertise led by different people, the project hand-offs from one stage to the next have to be seamless and smooth for achieving the fastest time-to-market & time-to-mass-production.

n  Design-in Manufacturability and Testability have been the critical success factors to differentiate the market leader.

n  CMOS early innovators (IDT & Cypress) did not use patent litigations as entrance barriers to impede their competitors, instead industry-wide collaboration and knowledge sharing along the supply chain with equipment suppliers facilitated and expedited ecosystem building for CMOS to be the Mainstream IC Manufacturing Standard Technology (by 1986).


Thank You! ([email protected])

Please visit www.iipcc.org


technology development methodology – cmos as a game-changer

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