tdr techniques for characterization and modeling of ... · tdr measurements time domain...
TRANSCRIPT
TDR Measurements Time Domain Reflectometry (TDR) has traditionallybeen used as the key measurement technology forelectrical characterization of electronic packages.Theory of TDR measurement can be found in [1], anumber of papers and application materials on elec-trical characterization of packages has been pub-lished (for example, [2], [3]), and guidelines for useof TDR for package lumped parameter extractionhave been standardized by the Joint ElectronDevice Engineering Council (JEDEC) in [4] as earlyas 1994. A typical TDR measurement setup isshown in Figure 1.
Figure 1. Typical package characterization setup
TDR is a very visual and intuitive modeling method-ology; it is easier understood and accepted bydigital designers. The intuitiveness of TDR hasresulted in its wide acceptance for interconnectmeasurements and modeling work in general, andspecifically for electrical modeling of packages.Package modeling techniques using TDR can beeasily extended for characterization of other electri-cally short structures, such as connectors, socketsand multichip modules (MCMs).
Some of the advantages of TDR-based modelingover the frequency domain methodologies is thatTDR allows the designer to obtain both lumped aswell as distributed SPICE and IBIS models for thepackage interconnect that will closely correlate tothe physical layout of the package (Figure 2).
Frequency domain modeling is more focused onobtaining single-value lumped L and C, or onobtaining S-parameters, which can be difficult, if atall possible, to use with a SPICE or IBIS simulator.These S-parameter data then need to be converted
into a SPICE or IBIS model, which normally resultsin a behavioral model. The behavioral model nor-mally does not correlate to the physical layout of thepackage, and therefore cannot be used todetermine what part of the package performs theworst electrically and causes the most signal integri-ty problems.
It should be noted, however, that S-parameter datacan be computed from TDR measurements [5], aswell as TDR data can be computed from S-parame-ter measurements. In this paper, we will treat TDR-capable network analyzers the same as TDRoscilloscopes.
Multiple Reflections and the TrueImpedance ProfileTDR is a reflection measurement technology, andcan measure characteristic impedance at a singlediscontinuity very accurately. In order to determineimpedance of a structure with multiple impedancediscontinuities, one needs to deconvolve themultiple reflections from the TDR waveform, andcompute the true impedance profile for the Device
TDR TTDR Techniques for Characterization echniques for Characterization and Modeling of Electronic Packagingand Modeling of Electronic Packaging
Application Note
TDRInstrument
TDR probe withsignal and ground
connections
Cables
Board tracePackage
Package Model
Board trace
Package ShelfBondwire
Board PadDie Pad
Bondwire
Figure 2. The intuitive and easy to use TDR modelingmethodology allows the designer to extract a pack-age model that correlates well with the physical lay-out of the package under test
Copyright © 2001 TDA Systems, Inc. All Rights ReservedThis application note was published in High-DensityInterconnect (HDI) Magazine, March and April 2001
Under Test (DUT), [6], [7]. Multiple reflection effectsare evident in the following example, Figure 3.
Figure 3. TDR waveform vs. the true impedanceprofile. True impedance profile provides accurateimpedance readouts
The TDR waveform may be confusing for thedesigner and will not provide accurate impedancereadings for all but the first couple of impedancesections. The true impedance profile, in turn, com-putes accurate impedance values and provides aneasy path for computing the values of the distrib-uted model. Qualitatively, a straight-line impedanceprofile section is a transmission line, a peak is aninductance and a dip is a capacitance. Theappropriate transmission line impedance values canbe directly read from the impedance profile display,and the appropriate capacitance and inductancevalues can be computed as:
(1)
where t1 and t2 are the boundaries of the lumpedsegment "dip" or "peak," Figure 4.
Figure 4. Peaks in package impedance profile corre-spond to inductive segments, dips to capacitive seg-ments, and straight sections to transmission lines
Ctotal is the sum of the self-capacitance of the leadand its mutual capacitance to other leads. This isthe diagonal term in the capacitance matrix as it iscomputed by 3D field solvers for a segment of apackage trace1.
Impedance deconvolution algorithm discussedabove is implemented in TDA Systems IConnect®TDR software. Additionally, IConnect uses the trueimpedance profile, which it computes beforehand, toautomatically compute and save the appropriate Z,td, L and C values.
Choosing Model Type and ModelValidity RangeWhen a designer is tasked with extracting an equiv-alent circuit model for a package, he or she needsto answer two key questions:
1. Is a simple RLC, or lumped model for thepackage acceptable, or is a distributed modelrequired?2. What is the desired frequency range of validityfor the package model?
A lumped model for the package is sufficient if thepackage trace in question is electrically smallcompared to the rise time of devices for which thepackage was designed. Ideally, the length of thepackage trace should be less than 1/10 of thedevice rise time, but a more moderate factor of 1/5or 1/6 is sufficient in most practical applications.Therefore, one can say that a lumped model for thepackage trace can be used if:
(2)
TDR also provides the designer with an easy way tomeasure the electrical length of the package trace.Keep in mind, however, that TDR provides theround trip delay through the interconnect, whichneeds to be divided in half in order to obtain theactual propagation delay. Alternatively, if the pack-age inductance L and capacitance C have beenfound, the propagation delay through the packageinterconnect can be estimated as:
(3)
If a lumped model cannot be used, a more complexdistributed model must be extracted. For evenfaster rise times and higher frequencies, the level ofdetail in the distributed model increases, and some-times even high-frequency loss mechanisms mustbe taken into account. To avoid the unnecessaryhigh complexity of the model, the designer shouldkeep in mind the specific application and rise timefor which the package was designed, and limit therange of validity for his or her package model to thatrise time. The equivalent 3 dB frequency range ofvalidity for such model can then be estimated fromthe application rise time as:
(4)
2
∫∫⋅⋅==2
1
121 t
ttotal dt
tZC
)( ∫∫⋅⋅==
2
121 t
tself dttZL )(
Lt1 t2
Ct1 t2
Z, td Z, td
1 However, when a 3D field solver writes a netlist for lumpedcoupled circuit to be used for circuit simulations, it typicallywrites a self capacitance value, not the total capacitance.
6rise
packagett <<
LCt package ==
risedB tf 350
3.<<
TDR ResolutionSometimes it is believed that TDR is not capable ofresolving small features in the package under test.Generally speaking, it is true that a TDR user cannot separate two discontinuities, the electrical dis-tance between which is less than half the TDR risetime. Since a typical rise time in currently availableTDR oscilloscopes is on the order of 30-40 ps, thatmeans that a typical TDR oscilloscope can not sep-arate two discontinuities that are less than 15-20 psapart – that is, less than about 3-4 mm for a typicalpackage. This number can be somewhat better ifthe true impedance profile is used.
In fact, this analysis holds true if one really wantedto resolve the two distinct discontinuities. However,when a package is that small, for a vast majority ofhigh-speed digital applications, a simple single-ele-ment lumped model extracted using one of the tech-niques described below will be sufficient as long asthe lumped element assumption discussed below ismet. Additionally, since these techniques rely oncomparing two TDR waveforms – the DUT and thereference – capacitance and inductance of a pack-age with a trace much shorter than 3-4 mm can beobtained, and the resolution limitation discussedabove can not be applied. Inductance and capaci-tance for the package traces as short as 1 mm, withinductance of less than 1 nH and capacitance assmall as 200 fF can be computed with a sufficientlevel of accuracy.
Minimizing Measurement ComplexityModern electronic packages have become verycomplex structures, with pincounts in the hundredsand layouts utilizing multiple layers on the packagesubstrate. It is simply impractical to measure everysingle lead in the package under test in order toobtain a package model, unless the measurementcan be completely automated. Such automation canbe very costly, in particularly in terms of packagefixturing required to accommodate automatedmeasurements.
We can take advantage, however, of the packagesymmetry, thereby minimizing the amount ofmeasurement effort required. For example, we canchoose a corner pin and a pin in the middle of thepackage, which should provide us with a sufficientrange of inductance and capacitance values for thepackage under test.
For example, for a BGA package sample shown onFigure 5 below, one can choose to characterize thelongest leads in the outside row as the leads withthe largest parasitics, the shortest leads in the out-side row as the medium parasitics, and the shortest
leads in the inside row as the leads with the small-est parasitics.
Figure 5. Choosing strategic locations for the pack-age characterization. The data for these strategiclocations should represent the range of package par-asitics accurately, both self and mutual
Additionally, a number of high-quality electromag-netic field solvers exist that allow the designer toextract the parasitic values for the package undertest. If a package layout is complex and does notlend itself easily to identifying "smallest" and"largest" leads, an alternative approach that adesigner might take it as follows. First, the designerprovides the package layout data to the field solversoftware, and computes the parasitics for the pack-age leads. Then, the leads with smallest, mediumand largest parasitics can be identified, and theirparasitic values can be validated with a TDRmeasurement using one of the techniques dis-cussed below.
Validating the ModelOnce the model is extracted, whether from TDRmeasurements or from an electromagnetic fieldsolver, the designer must simulate the model for thepackage under test and ensure the correlationbetween simulation and measurement. When run-ning a validation simulation, the designer shouldalso keep in mind the desired frequency range ofvalidity and rise time for the model. Running a vali-dation simulation with a rise time much faster thanrequired by the designer's application will result inunnecessarily complex models and excessiveamount of effort required to obtain such models. It isrecommended that the simulated and measureddata be filtered down to the application-specific risetime when comparison between simulation andmeasurement is performed, using either the oscillo-scope filter, or the IConnect software rise time filter.
IConnect TDR software from TDA Systems signifi-cantly simplifies comparing results of simulationswith TDR measurements by providing a link to sim-ulators and TDR instruments and quickly combiningthe measured and simulated data in one waveformviewer. To further facilitate the validation of thepackage models, IConnect provides a quick way to
3
Shortest leads,outside row
Longest leads,outside row
model the TDR source in order to ensure that thesource in the simulation and measurement are thesame, and any discrepancy between the modelsimulation and the measurement come from themodel only.
The designer obtains immediate feedback inIConnect on accuracy of the model by comparingthe simulation and measurement. As a result, fine-tuning of the model, if the correlation betweensimulation and the measurement is not perfect, isextremely simple and quick.
Package Fixturing and ProbingA fixture or probe for package TDR measurementmust provide a 50-Ohm environment to the packageunder test in order to obtain meaningful TDRresults. It also must ensure that the fixture itselfdoes not add to the computation of inductance orcapacitance of the package, or that it is de-embedded during the measurement process.
In addition, the fixture should resemble the applica-tion environment in which the package will be used.For example, for a package with a thermal plug thatdoes not serve as a ground plane, the plug mustnot be connected to the fixture ground plane. Ifthere are current-carrying planes in the package,such planes must be connected to the fixture orprobe ground plane. The ground plane of the fix-ture, its distance from the package and its dielectricconstant should resemble those for the environmentin which the package will be used, if this informationabout the application ground plane is available. If itis known which pins in the package serve asground and power pins, connecting these pins tothe fixture ground will further facilitate accurateapplication-specific characterization of the package.
A wide variety of different techniques can be usedto provide a ground contact for the package undertest. A ground plane for a leaded package can beeasily provided by placing conductive materialunder the package, and isolating the package leadsfrom this ground plane as required by themeasurement. A chuck of a microwave probe sta-tion, or even a metal plate of sufficient thickness (atleast thicker than the skin depth at the frequencyrange of interest) can serve as good ground planes.For an area array package or a chip-scale package,developing a simple PCB or metal characterizationfixture, which allows either easy contact by amicrowave probe, or connection by a coax probe oran SMA cable, can create a high-quality groundplane, Figure 6.
Figure 6. BGA characterization fixture examples.These examples show PCB-based fixtures, whichallow for an easy connection to the package with amicrowave probe. These fixtures do not contribute tothe parasitics of the package, since the measurementreference plane can be easily established at the tip ofthe measurement probe, and the parasitics of the fix-ture can be de-embedded
A fixture with traces on a low-loss PCB leading intoSMA or similar connectors can be convenientbecause of the ease of making the connection fromthe fixture to the TDR instrument. However, suchfixture must be carefully de-embedded from themeasurement. A simple method of putting conduc-tive epoxy or paste over the package leads, provid-ing a ground connection and leaving only severalleads for testing, can be extremely effective in pro-viding a package characterization test setup. Thefixture or probe can be de-embedded from themeasurement by windowing if the impedance profiletechnique is used, or by performing a referencemeasurement with a bare fixture, and using thelumped element extraction method below.
Additional thought should also be given to the inter-action of the package leads under test with theadjacent leads, in particular in case of area array(BGA and LGA) packages. For example, for theself-capacitance measurement, the adjacent leadsmust be shorted to ground on the side where thesignal is injected to minimize the effect of mutualcapacitance of those leads. For the self-inductancemeasurement they must be open-ended, to mini-mize the effect of mutual inductance [8].Additionally, the true impedance profile method dis-cussed later may not provide correct results if thereis large amount of coupling into those adjacentleads, and the differential techniques may need tobe applied.
4
Package
Signal-GroundProbe
Vias topackage
leads
PCB providesground
connections
Package
PCB provides ground connectionsPCB trace to package lead
Fixturegroundplane
Fixturegroundplane
Via to ground for reference measurements
Copyright © 2001 TDA Systems, Inc. All Rights Reserved
Single-ended TDR TechniquesSingle-ended TDR allows the designer to obtain apackage model by sending a single TDR signal intothe package lead. A distributed model, necessaryfor multilayer packages with traces that are electri-cally long, such as PGA and some large complexarea array packages (BGA and LGA), can beextracted using the impedance profile approach. Alumped L-C model, more appropriate for electricallyshort packages, such as small area arrays, TSOP,chip-scale packages (CSP), or packages operatingat relatively low frequencies, can be extracted froma single-ended lumped element extraction method.Mutual inductance and capacitance can also befound based on near end crosstalk measurement.
Single-ended TDR measurement provides accurateresults only in case of weak coupling to the adja-cent leads in the package. If the coupling is strong,differential measurement will provide more accurateresults.
Impedance Profile AnalysisImpedance profile analysis is useful for packagesand multichip modules (MCMs) with complex lay-outs (large LGA and BGA), or for packages withtraces that are long electrically (PGA), for which thelumped model criterion defined by equation (2) doesnot hold. For MCMs and area array packages, thepackage layout may have many lines that crossover each other and have potential for coupling, andlittle symmetry is observed in the package. Overall,such layout becomes so complex that it resemblesmore a PCB layout rather than a package layout.The impedance profile analysis allows the designerto obtain a distributed model for such complex orelectrically long packages.
The value of this approach is that it allows thedesigner to obtain distributed models for the pack-age under test. The disadvantage of this method isthat the coupling to trace segments adjacent to thetrace under test is not considered during the tracemodeling, which can lead to some inaccuracies inthe model. The designer may ensure the accuracyof the model by using a transmission (TDT)measurement in addition to the TDR measurementfor model validation.
It should be noted that a package layout with highlevel of complexity presents not only characteriza-tion problems, but also has great potential for pre-senting signal integrity problems as well. Simplifyingthe layout as much as possible will not only simplifythe package characterization, but also will alloweasier package simulation as part of the systemdesign simulations and, most likely, better signal
integrity in the package.
As an example, we extracted a model for a PGApackage. The package impedance profile is shownin Figure 7.
Figure 7. Modeling the package using the trueimpedance profile analysis. The package trueimpedance profile shows several distinct segments inthe package. IConnect software computesinductance, capacitance and impedance and delay foreach of segment
The package true impedance profile shows threedistinct segments – one inductive segment in thebeginning, due to the inductance of the packagepin, and two transmission line segments on the sub-strate layers inside the package, with no termination(open-ended) inside the package. The correspon-ding model computed by IConnect TDR softwareconsists of a 3.3 nH inductor and two transmissionlines, 34 and 44 Ohms, each about 100 ps long.Once the model is extracted, the correlationbetween the simulation and measurement areshown in Figure 8.
Figure 8. Validation of the PGA package model inIConnect software. The simulated and measuredwaveforms have been filtered to 150 ps. A good levelof model accuracy is achieved
5
Lumped Element Model Extraction(JEDEC Guideline Method)The purpose of this method is to extract Cself andLself for the package lead under test, as well asCmutual and Lmutual for the given pair for the pack-age leads, if required. This technique is the pre-ferred method when a lumped model is required.However, fixturing requirements may make the adja-cent-opposite technique discussed below an easierone for inductance computation.
This lumped element model extraction relies on rel-ative measurement, comparing the reference (shortor open) waveform to the reflected or inducedwaveform. Any difference between the referenceand DUT waveform is caused by the self or mutualinductance or capacitance of the DUT. It is veryuseful for practically any type of package without aninternal current carrying ground plane, particularly ifa simple single-element model is required, and thecondition of an electrically short package trace (2) ismet. This technique can also provide excellentresults when inductance of the ground lead needsto be obtained for characterization of the packageground bounce (delta I noise).
The fixturing in this method for capacitancemeasurement is very straightforward - the leads onthe inside of the package are left open-ended,whereas on the outside of the package they shouldbe shorted to ground, except for the leads undertest.
Figure 9. Capacitance measurement setup. The leadson the inside of the package are left open-ended,whereas on the outside of the package they shouldbe shorted to ground, except for the leads under test
For self-capacitance Cself, a reference openwaveform is required, which is obtained by discon-necting the measurement probe from the packagelead, and capturing a TDR waveform while theprobe is in the air. The difference between the TDRwaveform of the package trace and the referenceopen TDR waveform gives the sum of lead capaci-tance and mutual capacitances to other leads Ctotal:
(5)
where V is the TDR voltage incident at the leadunder test, normally half the TDR source amplitude,and Z0 equals the characteristic impedance of themeasurement system, 50 Ω for currently availableTDR instruments.For practical pur-poses, it is notnecessary to inte-grate to infinity, butonly until the differ-ence between theWopen and WTDRis negligibly small.
For mutual capacitance Cmutual, the measurementsetup is the same, but the near-end crosstalkwaveform on the victim lead under test is acquiredinstead, while the TDR signal is sent on the offend-er line. Additionally, it is recommended to acquire abackground noise waveform, acquired with no TDRstimulus on either of the lines, which allows us tocorrect for possible DC offset in TDR oscilloscope,as well as take into account any additional externalsources inducing a signal on the victim line. Themutual capacitance can then be computed as:
(6)
where Wbackground is the background noisewaveform. One all the mutual capacitances for thegiven lead are found, its self capacitance can befound by subtracting all the mutual capacitancesfrom the total capacitance value.
For inductance measurements, the outside leads ofthe package are also shorted to ground or terminat-ed to 50 Ohms, except for the leads under test andseveral adjacent leads which share mutualinductance with the lead under test. On the inside ofthe package, however, for inductance measurementthe leads must be shorted to ground. At the veryleast, for inductance measurement the leads mustbe shorted together on the inside of the package toprovide a low inductance exit path for the current.
For self inductanceLself, a referenceshort waveform isnow required, whichis obtained by short-ing the measurementprobe signal lead toground on a piece ofconductive material,such as copper. Thedifference between the TDR waveform of the pack-age trace and the reference short TDR waveform
6
Packageunder testTDR into the
package lead
Measure reflection
Measure near-endcrosstalk in adjacent
lead
Packa
ge le
ads
Keep leadends open
∫∫∞∞
−⋅⋅⋅⋅⋅⋅
==002
1 dtWWVZ
C TDRopentotal )(
WTDR
Wopen
C
∫∫∞∞
−⋅⋅⋅⋅⋅⋅
==002
1 dtWWVZ
C backgroundinducedmutual )(
WTDR
WshortL
Figure 10. Self-capacitancemeasurement
Figure 11. Self-inductancemeasurement
will now give us the lead inductance:
(7)
Mutual inductance can be computed as:
(8)
In both cases, the fixturing requirements limit theusability of this method of inductancemeasurements to packages that are easily accessi-ble on the inside. This may be a preferred methodfor small packages such as TSOP, SOIC, CSP;however, if the number of leads used for a currentreturn path to ground is small, the inductance of thereturn path is extracted in addition to the leadinductance. This method can also be used for largerpackages, such PGA and QFP, as long as thelumped model approximation (2) for the packagelead holds.
The advantage of this method is that the techniqueis simple, well understood and standardized. Thefixturing disadvantages for package inductancemeasurement are obvious. There is also great pos-sibility of not taking into account coupling of energyinto leads adjacent to the lead under test.
For example, consider the following package leadmeasurement on 6-lead TSSOP package.
Figure 12. TSSOP package measurement setup. Thepackage was placed on a probe station metal chuck,which provided a good ground plane for themeasurement. The package lead to which the testprobe was connected was isolated from the probestation chuck
The lead on the inside of the package was shortedto the die paddle with a bondwire, and four groundleads were connected to the die paddle directly,with a low-inductance connection. As a result,using IConnect C and L computational proceduresthat implement equations (5) and (7), we obtaincapacitance and inductance for the package lead of200 fF and 1.0 nH (for inductance example, seeFigure 13).
Figure 13. Computation of self-inductance inIConnect. The inductance waveform is computedusing equation (7), and the difference between thetwo cursors at the beginning and end of inductancewaveform provide the inductance value of 1.0nH
The inductance for the tested lead includesinductance of the lead itself, inductance of thebondwire, and the combined inductance of the fourleads that are connected to the ground and throughwhich the current, injected into the lead under test,exits the package and returns to ground. Therefore,this additional inductive value of the four leads inparallel (Lground / 4) should be taken into account.However, in this particular case it was believed thatthe overall inductance was dominated by the bond-wire inductance, and therefore the inductance of theground leads was ignored.
The capacitance computed is just the capacitanceof the package lead and all its mutual capacitances.Keep in mind that if the die is placed inside thepackage when the characterization is performed,the total capacitance measured will be a combina-tion of the capacitance of the package lead and theinput capacitance of the die. If a designer needs toresolve the package lead capacitance separatelyfrom the die capacitance when the die is inside thepackage, a single-ended or differential impedanceprofile technique (either the single-ended techniqueabove or the differential technique discussed below)must be used.
Since this modeling technique relies on a relativemeasurement, it is easy to note that any fixture thatcan provide such relative measurement will allowthe designer to obtain the package and die para-sitics, as discussed in a corresponding IBIS specifi-cation [9]. For example, for the followingmeasurement of the input capacitance of the diecombined with the capacitance of the package lead,the fixture constituted a test board with a socket tohold the QFP type of package. To acquire thereference waveform, we sent a TDR signal into an
7
∫∫∞∞
−⋅⋅⋅⋅
==0
0
2dtWW
VZL backgroundinducedmutual )(
Die paddle
Package outline
TDR probe
Metal ground plane
BondwireLead
Isolating pad
Ground
Ground
Ground
Ground
∫∫∞∞
−⋅⋅⋅⋅
==0
0
2dtWW
VZL shortTDRself )(
empty socket. To acquire a package lead waveform,we put the packaged part into the socket and sentthe signal into the same path. The differencebetween the two waveforms, computed using equa-tion (5), constituted the input capacitance of the diecombined with capacitance of the package lead(see Figure 14).
Figure 14. Computation of a die capacitance com-bined with the package lead capacitance
Differential TDR TechniquesSingle-ended TDR allows the designer to obtain alumped or distributed model for the package lead;differential TDR, on the other hand, allows thedesigner to obtain a coupled lumped or distributedmodel for the DUT. As the name implies, differentialTDR relies on sending two simultaneous steps, ofthe same amplitude and opposite polarity, to the twopackage leads under test. Most modern TDRoscilloscopes have differential capability built in, andas many as 4 to 8 or even more ports can be meas-ured simultaneously.
The differential stimulus creates a virtual groundplane effect, which significantly simplifies completecharacterization of the package. For example, witha differential measurement setup, lead inductancecan be extracted using the even and oddimpedance profile analysis described below withoutadditional fixturing on the inside of the package,whereas the adjacent-opposite technique allows thedesigner to extract the self and mutual inductanceof a package lead essentially without providing aground connection for the measurement probe.Furthermore, the virtual ground plane createdbetween the two leads results in that the electro-magnetic field interaction is mainly limited to the twoleads under test, and minimum energy couplingoccurs into any other leads, Figure 15. In case of asingle-ended TDR measurement, on the other hand,unless all the leads around the lead under test aregrounded on the outside of the package for capaci-
tance measurements, energy coupling into thoseleads can result in incorrect measurement results.
Figure 15. In case of a differential TDR, the virtualground plane is the closest ground plane to the leadsunder test, and practically no interaction with theadjacent leads occurs. For a single-ended TDRmeasurement, energy can be coupled into the adja-cent leads, resulting in measurement error
A key assumption when performing differential TDRis that the two leads under test must be reasonablysymmetric. Therefore, the usability of this method islimited to most packages and leads, except for themore complex large-pincount ones with a complexinterleaving layout. For the complex large pincountpackage category, the impedance profile techniquein conjunction with a field solver analysis must beused.
Another assumption when performing a differentialmeasurement is that the two steps of oppositepolarity in the differential stimulus arrive at thedevice under test at the same time. This is easilyachieved, because modern TDR oscilloscopes havecapabilities to adjust the relative delay of the TDRsources within the sampling module and betweendifferent modules up to several hundred picosec-onds. To adjust the position of the two TDRsources, disconnect the probes that will be used inthe differential measurement from the DUT, andconnect them to ground. The difference betweenthe two TDR responses observed on the TDRoscilloscopes will be the round trip delay differencebetween the two sources; adjusting the relativesource position by half that delay will ensure thatthe sources arrive to the DUT at the same time.After that, use the acquisition delay adjustment tocorrect for the signal path back to the scope andensure that the two signals are observed at thesame time position on the oscilloscope.
Alternatively, to adjust the relative source position,you can TDR into a short symmetric test device,such as a power combiner, with TDR sources beingin differential mode, and observe the difference inthe wave shape between the two TDR channels.
8
SG S S GG
Virtual Ground
Field interaction for singleended TDR
Field interaction fordifferential TDR
G
Since the device is absolutely symmetric, nodifferential discontinuities should be observed, andthe two TDR responses should look absolutelyidentical in shape. You can adjust the source delayuntil such identical waveshape is observed.
Even and Odd Impedance AnalysisThe even and odd impedance profile analysis isuseful when a coupled line model is necessary forpackages and modules with complex layout, or forpackages with traces that are long electrically(PGA). It has the advantages of the single-endedimpedance profile analysis, but also takes intoaccount coupling between leads under test. Theeven and odd impedance profile analysis allows thedesigner to obtain a distributed model for thesecomplex or electrically long packages, using amethodology for differential line characterization dis-cussed in [10], or to compute a complete LC matrixfor a short package lead pair. However, thisapproach can be used only if the package lead pairin question exhibits a reasonable level of symmetry– otherwise the basic differential modeling assump-tion does not hold.
One advantage that this approach gives the design-er is that many times one can get away with a muchsimpler fixturing setup than otherwise required bysingle-ended modeling techniques. For example, noshorting of the package leads on the inside of thepackage is required; however, good grounding onthe side of the package where the stimulus isapplied is still necessary for a good common modemeasurement.
An additional important advantage of this methodcompared to a single-ended method is in the morecontrolled field interaction in the case of area arraypackages, and, therefore, better measurementaccuracy. For a differential measurement, a virtualground plane created between the two leads, pads,or balls under test results in a very controlled fieldinteraction just between these two leads, pads orballs. In case of a single-ended measurement, how-ever, unless the leads, pads or balls are adjacent tothe test leads are grounded, the interaction to theseleads can change the computed inductance / capac-itance values (see Figure 15).
This approach, however, may not be quite as accu-rate as the lumped element method or adjacent-opposite method if a single value lumped modelmust be extracted, and the extracted model mustalways be validated with a simulation from IConnectsoftware.
Additionally, compared to the adjacent-oppositemethod discussed in the following section, even-odd
impedance profile analysis still requires a goodground contact for the probe for the common modemeasurement.
To perform the measurement, the designer mustTDR into the two leads under test with a differentialand common mode stimulus, and acquire channel 1only on the TDR oscilloscope in both cases (nowaveform math is required), Figure 16.
Figure 16. Differential and common modemeasurements for even and odd impedance profilecomputations
Then a reference short or open waveform isacquired, and the even (common mode channel 1)and odd (differential mode channel 1) impedanceprofiles are computed. A differential model can beextracted by partitioning the two impedance profilesin the IConnect symmetric-coupled line modelingwindow. Alternatively, L and C self and mutual val-ues can be extracted using the following equations:
(9)
(10)
(11)
(12)
where Ctotal= Cself + Cmutual, and Zodd, todd, Zeven,teven are the odd and even impedances and delays,correspondingly. The reason for using Ctotal ratherthan Cself is that most field solver analysis will pro-duce a value equivalent to Ctotal. To achieve goodcharacterization accuracy, the board traces leadingto the package leads under test must be symmetricalso.
Consider the following example of an LGA package.The conductive epoxy covering most of the packagecontacts was used as a ground plane. The dieplacement area was planar with the top side of thepackage, and it was easy to short all the leads onthe die side of the package to ground by turning thepackage upside down and placing it on a probe sta-tion chuck. The differential and common mode TDR
9
TDR into the two adjacentsocket leads with differentialand common mode stimulus
Measure odd mode TDR withdifferential stimulus, and
even mode TDR with commonmode stimulus
Packageunder test
Packa
ge le
ads
(( ))oddoddevenevenself tZtZL ++==2
1
(( ))oddoddevenevenmutual tZtZL −==21
++==
even
even
odd
oddtotal Z
tZtC
21
−==
even
even
odd
oddmutual Z
tZtC
21
measurements are performed on two packageleads, and the even and odd mode impedances arecomputed, Figure 17.
Figure 17. Even and odd impedance profile analysisfor an LGA package. The selected section can bemodeled as a coupled transmission line section ofabout 90 ps, or as a lumped coupled segment forslower rise time
The fast TDR rise time resolves two sections. Thefirst section is lumped, mainly capacitive and notcoupled, as seen from the fact that the even andodd mode impedances for this first segment are thesame. Computed capacitance of the segment is 730 fF. The other section is a distributed one; it canbe modeled separately as a symmetric-coupledmodel discussed in [10], with 98 ps even modedelay and 92 ps odd mode delay. For slower risetime of 500 ps, it can be treated as a lumped ele-ment with the following parameters: Lself=3.9 nH,Lmutual=0.7 nH, Cself=2.2 pF, Cmutual=0.4 pF. Thecorrelation between simulation and measurementfor this model is shown in Figure 18. Filtering the
waveforms down to an application-specific rise timewill further improve the correlation. The combinedvalue of the package lead self-inductance is 4.4 nHand mutual inductance remains 0.7 nH.
It is worth noting the single-line impedance profileanalysis for one lead in this package provides val-ues of Lself =3.9 nH and Cself =2.3 pF. These valuesare sufficiently close to those for Lself and Cself com-puted using even and odd impedance profile.
Adjacent-Opposite AnalysisThe technique described here was originally report-ed in [11]. The purpose of this approach is only tocompute Lself and Lmutual. It is the preferred methodfor package characterization when a lumped modelfor the package inductance is required. This methodis useful for smaller BGA packages, SOICs andother packages that do not provide easy connectionfrom the package cavity to a ground plane. Theadvantage of this approach is in its better accuracycompared to single-ended measurement, due to thepresence of the virtual ground plane between thetwo differential signals. However, you still have toconnect the leads under test together (but not toground) on the inside of the package, and only theinductances can be computed using this method.
To perform the measurement, you first do adifferential measurement on the two package leadsunder test. The inductance is measured based onthese two waveforms using the self-inductancemeasurement procedure in IConnect and equation(7). The measured inductance, however, is not justan inductance of one lead, but also a difference ofself and mutual inductance between the leads:
Ltotal adjacent = Lself - Lmutual (13)
Then a differential measurement is performed, buton leads on the opposite or orthogonal sides of thepackage, the leads that do not share any mutualinductance between each other, Figure 19.
Figure 19. Adjacent-opposite inductance modeling
10
Figure 18. Validation of even and odd mode analysismodel for an LGA package. Filtering the waveformsdown to a slower rise time will further improve thecorrelation
Differentialmeasurement ofadjacent leads
Differentialmeasurement oforthogonal leads
Packageunder test
Packa
ge le
ads
The inductance is again computed using IConnectself-inductance computation or equation (7), but theresulting inductance in that case is just Lself foreach pin. For better accuracy, one can subtract thepositive going waveform and the negative goingwaveform and divide it by two before computing theinductance of the pin, thereby taking the averagebetween the two measurements. Then, the mutualinductance between the two pins can be computedas:
Lmutual = Ltotal opposite - Ltotal adjacent (14)
For the same LGA package used in the even andodd impedance profile analysis, the computed valueof Ltotal adjacent is computed to be 3.5 nH and Ltotal
separate = 4.3 nH, which gives the values of Lself of4.3 nH and Lmutual = 0.8 nH, sufficiently close tothose obtained using the even and odd mode analy-sis (4.3 nH for self and 0.7 nH for mutual).
Selecting the Package ModelingMethod The following table provides suggestions on how toselect an appropriate TDR modeling method for thegiven package type.
Table 1. Recommendations for selecting a TDRmodeling method for different packages
Small packages, such as SOIC or TSOP, aretypically electrically short and a lumped elementmodel for those packages is sufficient. Small CSPcan be modeled using the same lumped modelingapproaches. Larger packages typically require a
distributed model, although sometimes a lumpedmodel can be used if short interconnect condition(2) is met. The amount of coupling in a PGA pack-age varies, and sometimes an uncoupled model forthis package type is sufficient; however, a coupledmodel is normally preferred. Larger and complexBGA, LGA and MCM packaging solutions some-times can be characterized using the even and oddimpedance profile analysis. However, many times amore complex model, which takes into account thecomplexity of the package, may be necessary.
11
Model required
Primary modeling method
Secondary modeling method
C Lumped
LAdjacent-opposite
C Lumped
LAdjacent-opposite
C Lumped
LAdjacent-opposite
LumpedCSP
MCM
Distributed, coupled
Distributed-coupled
Distributed-coupled
Distributed-coupled
Distributed-coupled
Small BGA, LGALarge BGA, LGA
SOIC
TSOP
PGA
QFP
Impedance profile
Even-odd impedance
Impedance profile
Even-odd impedance
Even-odd impedance
Lumped, adjacent-opp.
Lumped
Lumped
Even-odd impedance
Lumped, adjacent-opp.
Even-odd impedance
Impedance profile
Copyright © 2001 TDA Systems, Inc. All Rights Reserved
Appendix A. DerivationsLumped Model Circuit DescriptionA lumped model describing a package is typicallydefined by its inductance and capacitance matrices:
(A1)
(A2)
where n is the number of leads in the package.These matrices are diagonal symmetric, that is:
(A3)
These matrices are also normally sparse, becausethe elements that are far from the diagonalrepresent package pins that are far away from eachother, and therefore have little or no coupling.
When performing circuit simulation, the followingequivalent circuit for a pin pair, represented by 2x2L and C matrices, is used in simulators (Figure A1).
Note that the coupled line matrix notation uses theCtotal term, whereas a circuit simulator uses Cselffor netlist syntax.
Capacitance and Inductance of anImpedance Segment (equation 1)First, consider the inductance of an impedance seg-ment. Inductance can be determined frominductance per unit length as:
(A4)
Length dx can be found from velocity of propagationthrough this impedance segment, and time requiredto propagate through the segment:
(A5)
The factor of ½ comes from the fact that TDR givesus the round trip delay value, and we need to takehalf of that delay in order to get an accurate delaycomputation. Converting equation (3) to obtain thevelocity of propagation, we obtain:
(A6)
Using this equation, we obtain:
(A7)
Similar reasoning gives us:
(A8)
Self and Mutual Capacitance andInductance from Lumped ElementExtraction Method (5)-(8)The equations (5)-(8) are derived here for a case ofa lumped interconnect.
Lumped Self-CapacitanceLumped self-capacitance measurement is per-formed with the far end of the line open ended. Theequivalent circuit for such measurement is shown inFigure A2.
12
−−
−−−−
==
ntotalnmutualnmutual
nmutualtotalmutual
nmutualmutualtotal
CCC
CCCCCC
C
L
MOMM
L
L
21
2212
1211
==
nselfnmutualnmutual
nmutualselfmutual
nmutualmutualself
LLL
LLLLLL
L
L
MOMM
L
L
21
2212
12111
nmmutualmnmutual
nmmutualmnmutual
LL
CC==
==
Cself1/2
Cmutual/2
Lself1
Lmutual
Lself2
Cself1/2
Cself2/2
Cself2/2
Cmutual/2
Figure A1. Equivalent circuit for a pin pair, represent-ed by a 2x2 L and C matrices
∫∫==2
1
x
xselfself dxxLL )(
∫∫ ⋅⋅==2
121 t
tpropselfself dttVtLL )()(
)()()(
tCtLtV
totalselfprop
⋅⋅== 1
∫∫∫∫
∫∫
==⋅⋅==
⋅⋅⋅⋅
==
2
1
2
1
2
1
21
21
121
t
t
t
t total
self
t
t totalselfselfself
dttZdttCtL
dttCtL
tLL
)()()(
)()()(
∫∫⋅⋅==2
1
121 t
ttotal dt
tZC
)(
2V
Z0
C
LIwfm
+Vwfm
-
Figure A2. Equivalent circuit for a lumped selfcapacitance measurement
Copyright © 2001 TDA Systems, Inc. All Rights Reserved
2V is the amplitude of the TDR source, and Z0 theequivalent resistance of the source. For the lumpedstructure shown in the figure above, no currentflows through the inductor. Using:
(A9)
we obtain:
(A10)
(A11)
Since V(0) = 0 and V(∞) = 2V, we obtain:
(A12)
Since:
(A13)
(A14)
In practice, we have not only the output resistanceZ0, but also a cable, a fixture or a probe. This iswhy a reference waveform is required to allow us toremove the capacitance of the cable, fixture orprobe. Subtracting the capacitance obtained using areference waveform, we obtain equation (5).
In the presence of mutual capacitance, however, themeasurement setup for capacitance measurementis determined by Figure A3. As one can readilyobserve, the mutual capacitance to adjacent linesCmutual is in parallel with the capacitance C2 of theline under test. Therefore, the derivation above
describes the sum of self-capacitance and mutualcapacitance to adjacent leads, or total capacitanceof the lead Ctotal.
Lumped Self-InductanceLumped self inductance measurement is performedwith the far end of the line shorted to ground. Theequivalent circuit for such a measurement is shownin Figure A4.
Figure A4. Equivalent circuit for a lumped selfinductance measurement
For the lumped structure shown in figure A4, above,no current flows through the capacitor. Using:
(A15)
we obtain:
(A16)
(A17)
Since i(0) = 0 and i(∞) = 2V / Z0 , we obtain:
(A18)
(A19)
In practice, we have not only the output resistanceZ0, but also a cable, a fixture or a probe. This iswhy a reference waveform is required to allow us toremove the inductance of the cable, fixture orprobe. Subtracting the inductance obtained using areference waveform, we obtain equation (7). Thisequation is correct for the self inductance (Lself) ofthe lead.
Lumped Mutual CapacitanceMutual capacitance measurement is performed withthe far end of the victim line open ended. Theequivalent circuit for such a measurement is shownin Figure A5 on the following page.
13
∫∫∞∞
==0
12 dtIC
V wfm
0
2Z
VVI wfm
wfm
−==
∫∫∞∞
−⋅⋅⋅⋅
==00
22
1 dtVVZV
C wfm )(
2V
Z0
C1
C2
Cmutual
L1
L2
Figure A3. Equivalent circuit for a lumped self capaci-tance measurement in presence of mutual capaci-tance
dtdI
LV wfmwfm ==
∫∫∫∫∞∞∞∞
==00
dtVdiL wfm
∫∫∞∞
==−∞∞0
10 dtVL
ii wfm)()(
∫∫∞∞
==⋅⋅
00
12 VdtLZ
V
∫∫∞∞
⋅⋅==
0
0
2dtV
VZ
L wfm
∫∫∫∫∞∞∞∞
==00
dtIdvC wfm
∫∫∞∞
==−∞∞0
10 dtIC
VV wfm)()(
dtdVCI wfm ==
2V
Z0 L
C
Iwfm
+ Vwfm -
Copyright © 2001 TDA Systems, Inc. All Rights Reserved
Figure A5. Equivalent circuit for a lumped mutualcapacitance measurement
Induced current can be determined as:
(A20)
which gives us:
(A21)
(A22)
Since v1(∞) = 0, v1(0) = 0, v2(0) = 0, and v2(∞) = 2V,we obtain:
(A23)
Then using:(A24)
we obtain:
(A25)
In order to remove background noise and possibleDC offset in the TDR oscilloscope, we need to sub-tract the background noise waveform from theinduced waveform, which gives us equation (6).
Lumped Mutual InductanceMutual inductance measurement is performed withthe far end of the victim line shorted to ground. Theequivalent circuit for such measurement is shown inFigure A6.
Figure A6. Equivalent circuit for a lumped mutualinductance measurement
Induced voltage can be determined as:
(A26)
which gives us:
(A27)
(A28)
Since i1(∞) = 0, i1(0) = 0, i2(0) = 0, and i2(∞) = 2V / Z0, we obtain:
(A29)
In order to remove background noise and possibleDC offset in the TDR oscilloscope, we need to sub-tract the background noise waveform from theinduced waveform, which gives us equation (8).
Self and Mutual Capacitance andInductance from Even and OddImpedance Analysis (9)-(12)Even and odd mode impedance and delays can beshown to be:
(A30)
(A31)
(A32)
(A33)
From this, equations (9)-(12) easily follow.
dtdvC
dtvvdCI mutualinduced
11
12 −−== )(
0ZVI inducedinduced ==
dtVZV
C inducedmutual ∫∫∞∞
⋅⋅⋅⋅==
0021
mutualtotal
mutualselfodd CC
LLZ
++−
==
(( ))(( ))mutualtotalmutualselfeven CCLLt −++==
(( ))(( ))mutualtotalmutualselfodd CCLLt ++−==
mutualtotal
mutualselfeven CC
LLZ
−++
==
2V
Z0
Z0+
Vinduced_
L1
L2
Lmutual
Iinduced=I1
I2
dtdiL
dtdiLV mutualinduced
11
2 ++==
∫∫∫∫∫∫∞∞∞∞∞∞
++==0
110
20
diLdiLdtV mutualinduced
[[ ]] [[ ]] dtViiLiiL inducedmutual ∫∫∞∞
==−∞∞++−∞∞0
11122 00 )()()()(
dtVV
ZL inducedmutual ∫∫∞∞
==0
0
2
∫∫∫∫∫∫∫∫∞∞∞∞∞∞∞∞
−
−==
011
01
02
0
dvCdvdvCdtI mutualinduced
[[ ]]
[[ ]] dtIvvC
vvvvC
induced
mutual
∫∫∞∞
==−∞∞−
++++∞∞−−∞∞
0111
1122
0
00
)()(
)()()()(
dtIVC inducedmutual ∫∫∞∞
==0
2
14 Copyright © 2001 TDA Systems, Inc. All Rights Reserved
2V Z0 C2
Cmutual
L1
L2+v2_
Z0
+Vinduced-
Iinduced
C1
+v1
-
Self and Mutual Inductance fromAdjacent-Opposite Analysis (13), (14) The following figure shows the measurement setupfor the adjacent-opposite measurement.
Figure A7. Equivalent circuit for an adjacent-oppositeself and mutual inductance measurement
We can see that:
(A34)
Since V1 = -V2, i1 = -i2, and L1 = L2 = Lself , we obtain:
(A35)
This equation, following the derivation for the selfinductance of the package lead, gives us:
(A36)
which leads to equation (13). Equation (14) followseasily.
Appendix B. AbbreviationsCSP – Chip Scale PackageLGA – Land Grid ArrayBGA – Ball Grid ArrayMCM – Multichip ModulePGA – Pin Grid ArrayQFP – Quad Flat PackSOIC – Small Outline Integrated CircuitTSOP – Tape Small Outline Package
Appendix C. Bibliography[1] "TDR Theory," – Hewlett-Packard ApplicationNote 1304-2, November 1998 [2] J.-M. Jong, B. Janko, V.K. Tripathi, "EquivalentCircuit Modeling of Interconnects from Time DomainMeasurements," – IEEE Transactions on CPMT,Vol. 16, No. 1, February 1993, pp. 119-126[3] "TDR Tools in Modeling Interconnects andPackages," – Tektronix Application Note 85W-8885-0, 1993[4] "Guidelines for Measurement of ElectronicPackage Inductance and Capacitance ModelParameters," – JEDEC Publications JEP-123, 1994[5] L. Taira-Griffin, D. Smolyansky, M. Resso,“Improved Method for Characterizing and ModelingFlex-Circuit Based Connectors at 2.5 Gbps,” –DesignCon 2001, Santa Clara, CA, January 2001[6] L.A. Hayden, V.K. Tripathi, "Characterization andmodeling of multiple line interconnections from TDRmeasurements," – IEEE Transactions on MicrowaveTheory and Techniques, Vol. 42, September 1994,pp.1737-1743 [7] D.A. Smolyansky, S.D. Corey, "PCBInterconnect Characterization from TDRMeasurements" – Printed Circuit Design Magazine,May 1999, pp. 18-26 (TDA Systems ApplicationNote PCBD-0699)[8] "Design Guidelines for a Measurement Board forElectrical Characterization of Peripheral LeadedSurface Mount Semiconductor Packages," – JEDECPublication Proposal, 2000[9] "I/O Buffer Accuracy Handbook," – EIA IBIS,Revision 2.0, April 20, 2000[10] D. A. Smolyansky, S. D. Corey,"Characterization of Differential Interconnects fromTime Domain Reflectometry Measurements," –Microwave Journal, Vol. 43, No. 3, March 2000,pp. 68-80 (TDA Systems application note DIFF-1099)[11] M.A. Lamson, “Comparison of ElectricalParameters of TAB vs. Flat Pack IC Packages,” –Proc. 3d Int’l Tape Automated Bonding Symposium,San Jose, CA, Feb. 1991
∫∫∞∞
⋅⋅==−
0
0
2dtV
VZLL wfmmutualself )(
dtdiLLV mutualself )( −==
15
2V
Z0
Z0L1
L2Lmutual
2V
Z0
- V1 +
I2
I1
- V2 +
dtdiL
dtdiLV
dtdiL
dtdiLV
mutual
mutual
22
12
2111
++==
++==
Copyright © 2001 TDA Systems, Inc. All Rights Reserved
© 2001 TDA Systems, Inc. All Rights Reserved4000 Kruse Way Pl. 2-300, Lake Oswego, OR 97035, USATelephone: (503) 246-2272 Fax: (503) 246-2282E-mail: [email protected] Web site: www.tdasystems.comThe Interconnect Analysis Company™
PKGM-0301
Data subject tochange without notice
16