Tasks andTasks andFunctionsFunctions

Programmable Logic Design (40-Programmable Logic Design (40-493)493)

Fall 2001Fall 2001Computer Engineering DepartmentComputer Engineering Department

Sharif University of TechnologySharif University of Technology Maziar Gudarzi

IntroductionIntroduction

Procedures/Subroutines/Functions in Procedures/Subroutines/Functions in SW programming languagesSW programming languages The same functionality, in different The same functionality, in different

placesplaces Verilog equivalence:Verilog equivalence:

TasksTasks and and FunctionsFunctions Used in behavioral modelingUsed in behavioral modeling Part of design hierarchy Part of design hierarchy Hierarchical Hierarchical

namename

ContentsContents

Differences between tasks and Differences between tasks and functionsfunctions

TasksTasks FunctionsFunctions

Differences Differences between Tasks between Tasks and Functionsand Functions

Tasks andTasks andFunctionsFunctions

Differences between...Differences between...

FunctionsFunctions Can enable (call) just Can enable (call) just

another function (not another function (not task)task)

Execute in 0 simulation Execute in 0 simulation timetime

No timing control No timing control statements allowedstatements allowed

At lease one inputAt lease one input Return only a single Return only a single

valuevalue

TasksTasks Can enable other tasks Can enable other tasks

and functionsand functions May execute in non-May execute in non-

zero simulation timezero simulation time May contain any timing May contain any timing

control statementscontrol statements May have arbitrary May have arbitrary

input, output, or inoutsinput, output, or inouts Do not return any valueDo not return any value

Differences between… Differences between… (cont’d)(cont’d)

BothBoth are defined in a are defined in a modulemodule are local to the are local to the modulemodule can have local variables (registers, but not can have local variables (registers, but not

nets) and eventsnets) and events contain only behavioral statementscontain only behavioral statements do not contain do not contain initialinitial or or alwaysalways statements statements are called from are called from initialinitial or or alwaysalways statements statements

or other tasks or functionsor other tasks or functions

Differences between… Differences between… (cont’d)(cont’d)

Tasks can be used for common Verilog Tasks can be used for common Verilog codecode

Function are used when the common codeFunction are used when the common code is purely combinationalis purely combinational executes in 0 simulation timeexecutes in 0 simulation time provides exactly one outputprovides exactly one output

Functions are typically used for Functions are typically used for conversions and commonly used conversions and commonly used calculationscalculations

TasksTasks

Tasks andTasks andFunctionsFunctions

TasksTasks

Keywords: Keywords: task, endtasktask, endtask MustMust be used if the procedure has be used if the procedure has

any timing control constructsany timing control constructs zero or more than one output zero or more than one output

argumentsarguments no input argumentsno input arguments

Tasks (cont’d)Tasks (cont’d)

Task declaration and invocationTask declaration and invocation Declaration syntaxDeclaration syntax

task <task_name>;task <task_name>;

<I/O declarations><I/O declarations>

<variable and event declarations><variable and event declarations>

beginbegin // if more than one statement needed// if more than one statement needed

<statement(s)><statement(s)>

endend // if // if beginbegin used! used!

endtaskendtask

Tasks (cont’d)Tasks (cont’d)

Task declaration and invocationTask declaration and invocation Task invocation syntaxTask invocation syntax

<task_name>;<task_name>;

<task_name> (<arguments>);<task_name> (<arguments>);

inputinput and and inoutinout arguments are passed arguments are passed into the taskinto the task

outputoutput and and inoutinout arguments are passed arguments are passed back to the invoking statement when back to the invoking statement when task is completedtask is completed

Tasks (cont’d)Tasks (cont’d)

I/O declaration in modules vs. I/O declaration in modules vs. taskstasks Both used keywords: Both used keywords: inputinput, , output, output,

inoutinout In modules, represent portsIn modules, represent ports

connect to external signalsconnect to external signals In tasks, represent argumentsIn tasks, represent arguments

pass values to and from the taskpass values to and from the task

Task ExamplesTask Examples Use of input and output Use of input and output argumentsarguments

module operation;module operation;parameter parameter delaydelay = 10; = 10;reg [15:0] A, B;reg [15:0] A, B;reg [15:0] AB_AND, AB_OR, AB_XOR;reg [15:0] AB_AND, AB_OR, AB_XOR;

initialinitial$monitor( …);$monitor( …);

initialinitialbeginbegin

……endend

always @(A or B)always @(A or B)beginbegin

bitwise_oper(AB_AND, AB_OR, bitwise_oper(AB_AND, AB_OR, AB_XOR, A, B);AB_XOR, A, B);

endend

task bitwise_oper;task bitwise_oper;output [15:0] ab_and, ab_or, output [15:0] ab_and, ab_or,

ab_xor; ab_xor; input [15:0] a, b; input [15:0] a, b; beginbegin ##delaydelay ab_and = a & b; ab_and = a & b; ab_or = a | b;ab_or = a | b; ab_xor = a ^ b;ab_xor = a ^ b;endendendtaskendtask

endmoduleendmodule

Task ExamplesTask Examples Use of module local Use of module local variablesvariables

module sequence;module sequence;

reg clock;reg clock;

initialinitial

beginbegin

……

endend

initialinitial

init_sequence;init_sequence;

always always

asymmetric_sequence;asymmetric_sequence;

task init_sequence;task init_sequence;

beginbegin

clockclock = 1'b0; = 1'b0;

endend

endtaskendtask

task asymmetric_sequence;task asymmetric_sequence;

beginbegin

#12 #12 clockclock = 1'b0; = 1'b0;

#5 #5 clockclock = 1'b1; = 1'b1;

#3 #3 clockclock = 1'b0; = 1'b0;

#10 #10 clockclock = 1'b1; = 1'b1;

endend

endtaskendtask

endmoduleendmodule

FunctionsFunctions

Tasks andTasks andFunctionsFunctions

FunctionsFunctions

Keyword: Keyword: function, endfunctionfunction, endfunction Can be used if the procedureCan be used if the procedure

does not have any timing control constructsdoes not have any timing control constructs returns exactly a single valuereturns exactly a single value has at least one input argumenthas at least one input argument

Functions (cont’d)Functions (cont’d)

Function Declaration and InvocationFunction Declaration and Invocation Declaration syntax:Declaration syntax:

function <range_or_type> <func_name>;function <range_or_type> <func_name>;

<input declaration(s)><input declaration(s)>

<variable_declaration(s)><variable_declaration(s)>

begin begin // if more than one statement needed// if more than one statement needed

<statements><statements>

endend // if begin used// if begin used

endfunctionendfunction

Functions (cont’d)Functions (cont’d)

Function Declaration and Function Declaration and InvocationInvocation Invocation syntax:Invocation syntax:

<func_name> (<argument(s)>);<func_name> (<argument(s)>);

Functions (cont’d)Functions (cont’d)

Semantics Semantics much like much like functionfunction in in PascalPascal An internal implicit An internal implicit regreg is declared inside is declared inside

the function with the same namethe function with the same name The return value is specified by setting that The return value is specified by setting that

implicit implicit regreg <range_or_type> defines width and type of <range_or_type> defines width and type of

the implicit the implicit regreg typetype can be can be integerinteger or or realreal default bit width is 1default bit width is 1

Function ExamplesFunction ExamplesParity GeneratorParity Generator

module parity;module parity;

reg [31:0] addr;reg [31:0] addr;

reg parity;reg parity;

Initial beginInitial begin

……

endend

always @(addr)always @(addr)

beginbegin

parity = parity = calc_parity(addr);calc_parity(addr);

$display($display("Parity calculated = %b""Parity calculated = %b", , calc_parity(addr)calc_parity(addr) ); );

endend

function calc_parity;function calc_parity;

input [31:0] address;input [31:0] address;

beginbegin

calc_paritycalc_parity = ^address; = ^address;

endend

endfunctionendfunction

endmoduleendmodule

Function ExamplesFunction ExamplesControllable ShifterControllable Shifter

module shifter;module shifter;

`define LEFT_SHIFT 1'b0`define LEFT_SHIFT 1'b0

`define RIGHT_SHIFT 1'b1`define RIGHT_SHIFT 1'b1

reg [31:0] addr, left_addr, reg [31:0] addr, left_addr, right_addr;right_addr;

reg control;reg control;

initialinitial

beginbegin

……

endend

always @(addr)beginalways @(addr)begin

left_addr =left_addr =shift(shift(addr, `LEFT_SHIFTaddr, `LEFT_SHIFT););

right_addr =shift(right_addr =shift(addr,`RIGHT_SHIFTaddr,`RIGHT_SHIFT););

endend

function function [31:0][31:0] shift; shift;

input [31:0] address;input [31:0] address;

input control;input control;

beginbegin

shift = (control==`LEFT_SHIFT) ?shift = (control==`LEFT_SHIFT) ?(address<<1) : (address>>1);(address<<1) : (address>>1);

endend

endfunctionendfunction

endmoduleendmodule

Today SummaryToday Summary

Tasks and functions in behavioral modelingTasks and functions in behavioral modeling The same purpose as subroutines in SWThe same purpose as subroutines in SW Provide more readability, easier code Provide more readability, easier code

managementmanagement Are part of design hierarchyAre part of design hierarchy Tasks are more general than functionsTasks are more general than functions

Can represent almost any common Verilog codeCan represent almost any common Verilog code Functions can only model purely combinational Functions can only model purely combinational

calculationscalculations