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The top documents tagged [area overhead]

Survey of Detection, Diagnosis, and Fault Tolerance Methods in FPGAs Dan Fisher, Addison Floyd
Survey of Detection, Diagnosis, and Fault Tolerance Methods in FPGAs Dan Fisher, Addison Floyd
221 views
University of Toronto Minimization of Delay Sensitivity to Process Induced Vth Variations Georges Nabaa Farid N. Najm University of Toronto (georges,najm)@eecg.utoronto.ca
University of Toronto Minimization of Delay Sensitivity to Process Induced Vth Variations Georges Nabaa Farid N. Najm University of Toronto (georges,najm)@eecg.utoronto.ca
223 views
On the Capability and Achievable Performance of FPGAs for HPC Applications
On the Capability and Achievable Performance of FPGAs for HPC Applications
867 views
Random access scan
Random access scan
91 views
Power Gating
Power Gating
116 views
Test Data Compression Using Bitmask & Dictionary Selection
Test Data Compression Using Bitmask & Dictionary Selection
42 views
An Analytical Model for Worst-case Reorder Buffer Size of Multi-path Minimal Routing NoCs Gaoming Du 1, Miao Li 1, Zhonghai Lu 2, Minglun Gao 1, Chunhua
An Analytical Model for Worst-case Reorder Buffer Size of Multi-path Minimal Routing NoCs Gaoming Du 1, Miao Li 1, Zhonghai Lu 2, Minglun Gao 1, Chunhua
220 views
NATW 2008 Using Implications for Online Error Detection Nuno Alves, Jennifer Dworak, R. Iris Bahar Division of Engineering Brown University Providence,
NATW 2008 Using Implications for Online Error Detection Nuno Alves, Jennifer Dworak, R. Iris Bahar Division of Engineering Brown University Providence,
218 views
1 A Design Approach for Radiation-hard Digital Electronics Rajesh Garg Nikhil Jayakumar Sunil P Khatri Gwan Choi Department of Electrical and Computer
1 A Design Approach for Radiation-hard Digital Electronics Rajesh Garg Nikhil Jayakumar Sunil P Khatri Gwan Choi Department of Electrical and Computer
214 views
Routing Track Duplication with Fine- Grained Power-Gating for FPGA Interconnect Power Reduction Yan Lin, Fei Li and Lei He EE Department, UCLA Partially
Routing Track Duplication with Fine- Grained Power-Gating for FPGA Interconnect Power Reduction Yan Lin, Fei Li and Lei He EE Department, UCLA Partially
218 views
Priyadharshini Shanmugasundaram priyas@nvidia.com Vishwani D. Agrawal vagrawal@eng.auburn.edu DYNAMIC SCAN CLOCK CONTROL FOR TEST TIME REDUCTION MAINTAINING
Priyadharshini Shanmugasundaram [email protected] Vishwani D. Agrawal [email protected] DYNAMIC SCAN CLOCK CONTROL FOR TEST TIME REDUCTION MAINTAINING
218 views
Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt1 Lecture 20alt DFT: Partial, Random-Access & Boundary Scan n Definition n Partial-scan architecture
Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt1 Lecture 20alt DFT: Partial, Random-Access & Boundary Scan n Definition n Partial-scan architecture
225 views