Presented by:

Harish Peta – IMI2013002

• Scan design has been the backbone of design for testability (DFT) in industry for about three decades

• However, as the complexity of circuits has grown, the serial-scan has some inherent problems• test data volume

• test application time

• test power

• Switching activity and power consumption of serial-scan based DFT method is known to be much higher than normal circuit operation

• Excessive heat dissipation in high-speed and high density deep sub-micron (DSM) integrated circuits with the system-on-chip (SoC) scheme• produce incorrect responses

• permanently damage a circuit under test (CUT)

• reduce its reliability due to accelerated electromigration

• An alternate to serial scan architecture is Random Access Scan (RAS)

• In RAS, flip-flops work as addressable memory elements in the test mode.

• This approach reduces the time of setting and observing the flip-flop states.

• Requires a large overhead both in gates and test pins.

• Address three limitations of the traditional serial scan• test data volume

• test application time

• test power

• In the previous design, a single decoder was used.

• A more feasible decoder has been designed.

• There are only sqrt(N) address wires in modified decoder when compared to N address wires in the basic architecture decoder.

• Assuming a circuit has 𝑛𝑔 gates and 𝑛𝑓𝑓 FFs each consisting of 10 gates

• Gate overhead of scan =4∗𝑛𝑓𝑓

𝑛𝑔+10∗𝑛𝑓𝑓∗ 100% ------------------ (1)

• Gate overhead of RAS =6∗𝑛𝑓𝑓+

𝑐+𝑑

2

𝑛𝑔+10∗𝑛𝑓𝑓∗ 100% ------------------ (2)

• Let us consider a circuit with 5,120 gates and assume that there are 512 FFs in the circuit. The gate overhead of serial scan is 20% from Equation (1) and the gate overhead of RAS is 30.2% from Equation (2). Hence there is an increase of 10%.

• The FFs are cleared initially and then the following test is performed

{ (w0); (r0,w1); (r1,w0,r0) }

• All the stuck at faults (SAF) are detected because, from each cell a `0' and a `1' is read uniquely.

Test vector generating algorithm is as follows:

1. Obtain the combinational vectors along with good circuit responses and store the results in a stack

2. Find the FFs where faults are propagated at each vector

3. While number of vectors > 0(a) Read all the FF where the faults are detected

(b) Choose the next vector from stack that has least hamming distance from current FF states

4. End While

• During scan-in, the CUT is subject to unnecessary activity and all the FFs are subject to change state.

• Assuming that the power dissipation in the CUT, is directly proportional to the number of transitions in the primary inputs and the transitions in the states of FFs, the power dissipation in RAS is reduced drastically, since, the only activity during scan mode is the transition in state of a single FF under consideration and transitions at the primary input pins that control the decoder.

• [1] Dong Hyun Baik, Kewal K. Saluja, Seiji Kajihara, “Random Access Scan: A solution to test power, test data volume and test time”, Proceedings of the 17th International Conference on VLSI Design, 2004

• [2] H. Ando, “Testing VLSI with Random Access Scan”, in Proc. Of the COMPCON, Feb. 1980

• [3] V. D. Agrawal, K.-T. Cheng, D. D. Johnson, and T. Lin, “Designing Circuits with Partial Scan”, IEEE Design & Test of Computers, vol. 5, pp. 8 - 15, Apr. 1988.

• [4] Fan Wang, Auburn University, Dept. of Electrical and Computer Engineering, “Random Access Scan”, Term Paper, 2006

• [5] www.Wikipedia.org