t anenbaum, structured computer or ganization, fifth

on Education, Inc. All rights reserved. 0-13-148521-0

3

th (2)

and the function performed.


4

iming

ata path cycle.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-1

The data path of the example microarchitecture used in this

chapter.

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2Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pears

Timing diagram of one d


La couche micro-architecture (Chap

1. Un exemple de micro-architecture

Chemin de données

Micro-instructions

Contrôle de micro-instructions

2. Exemple de couche ISA: l’IJVM

3. Exemple d’implémentation

4. Conception d’une micro-architecture

5. Amélioration des performances

The Data Path (1)

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1

ter 4)

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pears

The Data Pa

Useful combinations of ALU signals

Data Path T


7


8

l: The Mic-1 (2)

t to 1 has two potential ors.

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A microinstruction with JAMZ sesuccess


Memory Operation

Mapping of the bits in MAR to the address bu

Microinstructions (Mic-1)
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5

s.


Microinstruction Control: The Mic-1 (1)

The complete block diagram of our example microarchitecture, the

Mic-1.

Microinstruction Contro


11

2)

n arithmetic computation.


12

ry Model

IJVM memory.


Use of a stack for storing local variables. (a) While A is active. (b) After A calls B. (c) After B calls C. (d) After C and B return and A

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calls D.


The various parts of the



1. Un exemple de Microarchitecture


Pile

Modèle de mémoire

Jeu d’instructions

Compilation de code Java pour l’IJVM



5.Amélioration des performances

Stacks (1)

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ter 4)


Stacks (

Use of an operand stack for doing a

The IJVM Memo


15

tion Set (3)

g IRETURN.


16

o IJVM (1)

embly language.

cimal.
(a) Memory before executing INVOKEVIRTUA

(b) After executing it.
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L.


(a) A Java fragment.

(b) The corresponding Java ass

(c) The IJVM program in hexade


The IJVM Instruction Set (1)

The IJVM instruction set. The operands byte, const, aare 1 byte. The operands disp, index, and offset are

The IJVM Instruction Set (2)

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13

nd varnum 2 bytes.


The IJVM Instruc

(a) Memory before executin(b) After executing it.

Compiling Java t


19

nd Notation


20

sing the Mic-1 (1)

r the Mic-1.


1. Un exemple de micro-architecture



Notation des micro-instructions

Implémentation de l’IJVM avec Mic1


5.Amélioration des performances

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The microprogram fo


Compiling Java to IJVM (1)

The stack after each instruction of Fig. 4-14(b


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17

).

ter 4)


Microinstructions a

• Permitted operations • May be extended by

• adding ‘‘<< 8’’: • shift left by 1 byte.

• A common operation: • H = MBR << 8.

Implementation of IJVM U


23

sing the Mic-1 (4)

r the Mic-1.


24

sing the Mic-1 (5)

r the Mic-1.


The microprogram for the Mic-1.
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The microprogram fo


Implementation of IJVM Using the Mic-1

The microprogram for the Mic-1.


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(2)

(3)



The microprogram fo



27

sing the Mic-1 (8)

fferent operand fields.


28

sing the Mic-1 (9)

arious microinstructions.

to2. (d) goto3. (e) goto4.
The initial microinstruction

sequence for ILOAD

and WIDE ILOAD. The

addresses are examples.

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The situation at the start of v

(a) Main1. (b) goto1. (c) go



The BIPUSH instruction format.

(a) ILOAD with a 1-byte index.

(b) WIDE ILOAD with a 2-byte index.


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(6)

(7)



The IINC instruction has two di



31

itecture (1)


32

itecture (2) ting ILOAD.

cuting ILOAD.


Enhanced microprogram sequence for executing

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POP.


Three-bus code for exe


Merging the Interpreter Loop with the Microcode (1)

Original microprogram sequence for executing P

Merging the Interpreter Loop with the Microcode (2)

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OP.


A Three Bus Arch

A Three Bus ArchMic-1 code for execu


35


36
A finite state machine for implementing the IF

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U.



A Three Bus Architecture (3)

A fetch unit for the Mic-1.

A Three Bus Architecture (4)

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39

egister Renaming (1)

e and in-order completion.


40

egister Renaming (2)

e and in-order completion.

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A superscalar CPU with in-order issu

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Out-of-Order Execution and R

A superscalar CPU with in-order issu

Out-of-Order Execution and R


43

Microarchitecture

he Pentium 4.


44
(a) A program fragment. (b) The corresponding basic block graph.

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A simplified view of the Pentium 4 data path.


Out-of-Order Execution and Register Renaming

Operation of a superscalar CPU with out-of-orderand out of-order completion.

Speculative Execution

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41

(3)

issue


Overview of the NetBurst

The block diagram of t

The NetBurst Pipeline

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45

cture

.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

47

The Microarchitecture of the 8051 CPU

The microarchitecture

of the 8051.


A simplified representation of the UltraSPARC III Cu pipeline.

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46


Overview of the UltraSPARC III Cu Microarchite

The block diagram of the UltraSPARC III Cu

UltraSPARC III Cu Pipeline

t anenbaum, structured computer or ganization, fifth

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