Syed Mohsin Abbas, Jihun Jung,and Sungju ParkMultimedia Systems Lab,

Dept. of Computer Science & EngineeringHanyang University, South Korea

BCH Codes

BCH Encoder◦ Serial BCH Encoder◦ Parallel BCH Encoder

Hamming Distance

False Positive

Logic Sharing

Proposed Algorithm

Simulation Results

Implementation

Conclusion

Widely used in communication systems and digital

technology

◦ Long Haul Optical Communication

◦ Digital Video Broadcasting

◦ NAND Flash

N-bit N-bit K-bitK-bit

A (n,k) binary BCH code encodes a k-bit message block into an n-bit codeword.

k-bit message (mk-1,mk-2,……,m0) (mi∈GF(2), 0≤i<k).

n bit codeword (cn-1,cn-2,……c0).

g(x) is the degree n-k generator polynomial.

c(x) = m(x)·xn-k + Rem(m(x)·xn-k)g(x)

Implementation◦ Serial (LFSR).◦ Parallel.

In high-speed applications, the clock frequency of such LFSR-based encoders cannot keep up with the data transmission rate.

There are many non-zero coefficients in the generator polynomial of long BCH encoders, the large fan-out will influence the delay of the critical paths seriously.

To get l-bit parallel encoder, we need to know the state of LFSR at the time t+1 from the state at time t and l input bits.

Sharing sub-expressions is an effective way to reduce area and complexity.

The more sub-expressions are used, the more circuit is simplified

Hamming distance between two strings of equal length is the number of positions at which the corresponding symbols are different .

One codeword is transformed to other codeword.

Solution:◦ CRC

BCH (15, 7) code, which can correct 2 errors. Its generator polynomial is

g(x) = x8 + x7 +x6 +x4 +1.

O[0]= s[0] ^ s[1] ^ s[3] ^ s[7] ^ d[0] ^d[1] ^ d[3]^ d[7]

O[1] = s[1]^s[2]^s[4]^d[1]^d[2]^d[4]

O[2] = s[2]^s[3]^s[5]^d[2]^d[3]^d[5]

O[3] = s[3]^s[4]^s[6]^d[3]^d[4]^d[6]

O[4]= s[0] ^ s[1] ^ s[3] ^ s[4] ^ s[5] ^d[0] ^ d[1] ^ d[3]^ d[7] ^ d[5]

O[5]= s[1] ^ s[2] ^ s[4] ^ s[5] ^ s[6] ^d[1] ^d[2] ^ d[4]^ d[5] ^ d[6]

O[6]= s[0] ^ s[1] ^ s[2] ^ s[5] ^ s[6] ^d[0]^ d[1] ^ d[2]^ d[5] ^ d[6]

O[7] = s[0]^s[2]^s[6]^d[0]^d[2]^d[6]

Step 1: ◦ Transform the output

equations in matrix, named equation matrix

Step 2: ◦ Compute similarity matrix,

take each row and check degree of similarity between other rows

Example:First row is taken and similarity between first row and second row is s[0]^s[1]^d[0]^d[2] similarly check similarity between first and other rows

Step 3: ◦ Delete similar rows

and rows containing less than 2 number of 1’s

◦ Sort the similarity matrix in ascending order based upon number of in each row.

Step 4: ◦ Check for covered rows

and covering rows and write covering rows in terms of covered rows.

P7 = s[0]^P[4]

P8 = P0^P2

P9 = P4^s[2]^d[0]

P10 = P2^P5

Step 5: ◦ Repeat step 4 for

output equations.

O[0] = p8

O[1]=p2^p9

O[2] = p3

O[3] = p9

O[4] = p7

O[5] = p10

Step 6: ◦ Check for shortest path in

output equations.O[1] = p2^p9 O[1] = p3^p8 O[1] = p0^p10

Criteria:◦ First compute column wise

sum of similarity matrix.◦ Now select that path which has

minimum sum.

Now compute sum for each path.

Path 1, O[1]=p2^p9 => s[0]^d[2]^s[1]^s[2]^d[0]^d[1]Sum = 6 + 4 + 6 + 4 + 3 + 6 => 29.

Path 2 sum = 27. path 3 sum = 29.

The BCH(31,16) and BCH(63,39) are used for testing of algorithm

Algorithm is implemented in MATLAB.

Coded in Verilog ModelSim is used for

Simulation Xilinx ISE is used for

Synthesis

BCH BCH BCH BCH BCH BCH

An algorithmic approach for logic sharing between parallel BCH encoder and CRC is presented.

Optimizations in terms of both area and frequency are achieved.