substrates for medical implantable applications finalmeptec.org/resources/15 - dyconex.pdf ·...
TRANSCRIPT
Substrates for Medical Implantable Applications
Dr. Marc Hauer
© DYCONEX AG 23.08.2011 2
Agenda
• Introduction
• Minimize Interconnect
• Minimize Routing Space
• Minimize Volume I: Thinner substrates
• Minimize Volume II: Folding
• Vertical Interconnects
• Selecting Materials
• Summary
© DYCONEX AG 23.08.2011 3
Introduction
The Key driver for new developments
• Comfort of the patient �
• Increase in functionality �
• Reduced power consumption �
• Cost reduction �
• Radio communications �
and their impact on the interconnecting
substrates
smaller devices
higher integration density
shorter signal paths
cost efficient materials / assembly
processes
RF requirements
© DYCONEX AG 23.08.2011 4
Introduction
• The substrate is the backbone of an electronic device
– It interconnects all components electrically
– It is the mechanical carrier for the components
• Substrate technology has a direct impact on
– Achievable form factors
– Available assembly processes
– Reliability and performance of the device
• Substrate technologies can be divided into
– Rigid substrates � based on glass reinforced materials
– Full Flex substrates � based on flexible foils which are glued with adhesives
– Rigid-Flex substrates � a combination of the above
© DYCONEX AG 23.08.2011 5
Minimize Interconnect
• Simplify interconnects within a device
– Ideally all components should a be connected with a single technology (i.e. soldering)
� Minimizes design restrictions on the substrate
� Reduces substrate and assembly cost
• Reduce the number of interconnect levels within a device
– Allow a direct interconnect to components
� With the right substrate / interconnect technology “interposers” can be avoided
– Allow direct access to all components
� Position components (i.e. feedthroughs) so that they can be connected directly
� Use a flexible substrate to bring the substrate and the component together
• Minimizing the interconnect will improve reliability and reduce costs
© DYCONEX AG 23.08.2011 6
Minimize Interconnect
Example:
• A flexible substrate
• A flexible arm connects to the feed-through
– Interconnects on different planes
– Direct interconnect of the flexible arm via soldering
– Lower number of interconnects vs. “wire option”
© DYCONEX AG 23.08.2011 7
Minimize Routing Space
• Smaller components
� More IO’s per surface area
� More vias for routing required
• In parallel type build-ups vias / pads
absorb a significant amount of routing
space
• This effect increases when routing dense
pad arrays
• Sequential type build-ups reduce the
routing space for interconnects
• Sequential type build-ups using filled vias
allow a maximum interconnect density
(sequential type build-up)
(paralell type build-up)
(sequential type build-up)
© DYCONEX AG 23.08.2011 8
Minimize Routing Space
Examples with maximum routing density:
• A flexible substrate with 6 layers
– With a sequential build-up
– Stacked and filled vias from Layer 1-3
• A flexible substrate, 6 layers
– With a sequential build-up
– Stacked and filled vias from Layer 1-6
• Filling the vias on the outer layer
maximizes the interconnect density
� via in pad design
© DYCONEX AG 23.08.2011 9
Minimize Volume I
• The size of a substrate is driven by:
– Surface area for routing
– Surface area for components
• The volume of a substrate is driven by the surface area and the thickness� The thinner the substrate � The smaller the volume
• A Thinner substrate
� Less expansion in Z-direction allows less copper in vias
� Less copper in vias allows finer artwork
� Finer artwork reduces the surface area for routing
• A Thinner substrate is more flexible
� May require more support during assembly / mechanical shock protection
� May allow tighter bending (for flexible substrates)
© DYCONEX AG 23.08.2011 10
Minimize Volume I
Examples
• Typical rigid substrate
– Using standard materials
– Parallel Build-up with two cores
– Blind and buried vias
• Typical flexible substrate
– Using standard materials
– Sequential Build-up
– Blind an buried vias
• Flexible materials are mostly thinner than
rigid materials leading to thinner overall
substrates
30 µm Cu
60 µm PP
30 µm Cu
100 µm Core
18 µm Cu
60 µm PP
18 µm Cu
100 µm Core
30 µm Cu
60 µm PP
30 µm Cu
TOTAL: 540 µm
25 µm Cu
25/25 µm Pi/ Ad25 µm Cu
25/25 µm Pi/ Ad18 µm Cu25 µm Pi
18 µm Cu25/25 µm Pi/ Ad
25 µm Cu25/25 µm Pi/ Ad
25 µm Cu
TOTAL: 360 µm
33 %
thin
ner
© DYCONEX AG 23.08.2011 11
Minimize Volume II
• The surface of a pcb substrate is driven by
– Routing space
– Components size
• Increasing the surface area by using more
assembly planes
� Improving the overall volume
by inter-digitizing components
• Rigid substrates
� More interconnects required
� Lost space for interconnects
• Flexible substrates
� Due to folding
no additional interconnects
© DYCONEX AG 23.08.2011 12
Vertical Interconnect
• Vias and Through holes connect the
different routing planes (Z-axis)
• Most reliability issues on substrates are
related to this interconnect
• Reliability of vias is driven by
– CTE mismatch of the materials
– Thermal stress during assembly and
the product life
– Stiffness of the materials
– Localization of stress
– Length of the interconnect
Schöne Via bilder
© DYCONEX AG 23.08.2011 13
Vertical Interconnect
• The CTE of PCB materials:
• X / Y axis is often matched to the copper
• Z axis is often significantly higher
• Examples of standard rigid materials �
• The thermal stress of an implantable substrate occurs typically before implant:
– During manufacturing of the substrate
– Drying, cleaning and curing processes
– Reflow
– Burn-in
• These temperatures cycles create mechanical stress
which is larger in Z-Axis than in horizontal plane
MaterialHi TgFR4
PI-Glass
BT-Epoxy
CTE – X / Y (ppm / K) 12 – 17 12-15 12 - 15
CTE – Z (ppm / K) 50 – 60 50-80 ~140
© DYCONEX AG 23.08.2011 14
Vertical Interconnect
• BUT....
CTE Mismatch ≠ Stress
• Flexible substrates use adhesives with a very high CTE (up 400 ppm / K)
� As these materials are very soft only a little stress on the via results
� Flexible substrates are very reliable during thermal stress
Typical IST graph of robust via boards (2500+ cycles, little resistance change)
Resistance Change
(mOhm)
© DYCONEX AG 23.08.2011 15
Vertical Interconnect
• Rigid-Flex substrates tend to combine:
– the CTE of flex adhesives (due to the
flexible bend zone)
– the stiffness of rigid substrates (due to
the rigid outer layers)
Rigid Material
Rigid Material
Flexible Material
� Rigid-Flex substrates have therefore a higher risk of failing reliability requirements
© DYCONEX AG 23.08.2011 16
Vertical Interconnect
• Micro and through vias are predetermined breaking points:
– Disruption in the material in combination with a CTE miss match
– Focal points of the induced stress
• The shorter the vertical interconnect:
� The more reliable the micro via
• Thinner dielectric layers shorten the interconnect length
� Improves reliability of a micro via
� Reduces required plating thickness
• Improve the reliability of through holes with micro vias
– Micro vias parallel to through holes for electrical contact
– Through holes only for mounting and solder flow
(Courtesy of PWB)
© DYCONEX AG 23.08.2011 17
Material Selection
• Material selection needs to take the material requirements into account:
• Examples:
– HV requirements for implanted defibrillators:
• The dielectric strength of glass reinforced materials may become critical
� This may lead to the selection of flexible or BT based materials
– Ionic contamination requirements for implants:
• Surface contamination may reduce the resistance between traces
• Surface contamination in combination with humidity may cause reliability issues
� Certain FR4 material inherently contain ionic contamination which can limit their use
© DYCONEX AG 23.08.2011 18
Summary
• As the “Backbone” of an implanted device the substrate contributes directly to
– Interconnect options
– Number of interconnects
– Volume of an implanted device
– Reliability of an implanted device
– Overall cost of the device
A strategic partnership between substrate supplier and OEM should therefore begin in an early design phase.
© DYCONEX AG 23.08.2011 19
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