substrates … lost in translationewh.ieee.org/soc/cpmt/presentations/cpmt0403.pdf ·...

Amkor Confidential

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Enabling aMicroelectronic World

2004 IEEE PRESENTATION – Components, Packaging & Manufacturing Technology (CPMT) Society, Santa Clara Valley Chapter www.cpmt.org/scv/

Substrates … Lost in Translation

2004 IEEE PRESENTATION – Components, Packaging & Manufacturing Technology (CPMT) Society, Santa Clara Valley Chapter www.cpmt.org/scv/

Substrates … Lost in TranslationR. HuemoellerVice President, Substrate TechnologyMarch 17, 2004

Enabling a Microelectronic World© 2004 Amkor Technology, Inc.

“As higher-function, higher-dissipation, and mixed-mode ICs reach the marketplace,

The mix of packaging methods to accommodate these new devices reflects the complexity of their needs.”

Amkor Confidential

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Substrates as Chip Translators

• A World in Transition

• Today’s Packaging Migration

• Substrate Design Rule Evolution

• Substrates in Transition

• Substrates … Lost in Translation


A World in Transition

Once upon a time, life was simple . . .Once upon a time, life was simple . . .

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Changing Environment

But technology refuses to stand still . . . But technology refuses to stand still . . .

A refrigerator with a detachable Web-ready HomePAD tablet computer built into its door.

© Samsung Electronics


Communication has Transitioned from Wire-line...

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. . . to Wireless


And from Voice Stream . . .

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. . . to Data Stream


IC Packaging

The Same Was True…The Same Was True…

Once upon a time . . . packages were simpleOnce upon a time . . . packages were simple

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Changing Package Environment

Now they are incredibly sophisticated Now they are incredibly sophisticated


The New Paradigm . . .

““Technology Transitions” Technology Transitions” -- changing the way changing the way ICs are integrated at the system levelICs are integrated at the system level

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Stacked Die

System-in-Package

Camera Modules

MEMS

TouchChip™Courtesyof STMicroelectronics

Example of Technology Transition

MicroLeadFrame®

Chip scale BGA


Impact of Technology Transition

• IC packaging challenges are increasing

Wafer size is growing

Chip feature size shrinking

Fab cost per chip shrinking

Chip complexity increasing

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Today’s Packaging Migration


Hot Packages30% unit growth!

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PBGA Substrate & Packaging Trends

• General – Has NOT Kept up with Silicon Fab technology – Results

Longer wires = Thicker Au wire required to span = Higher CostAdded layers and laser vias required to route complex designs Lack of line/space progression in this space…

• Substrate Technology – Electrical management is minimal : very little impedance control– Layer Count: 2 up to 6

Line and Space: 75 migrating to 50 umBond Finger Pitch:175 migrating to 115 umPlating Technology: Elytic is std, but use of FBG, Etchback & Bussless (elytic)

• Package Trends– Thermally Enhanced PBGA

Bridging the price/performance gap between CD and std. PBGA


C.D. Substrate & Packaging Trends

• General– Slow Down in TELCO Market has caused Market to Shrink 70%– 2004 is Predicted to be the First Year for Growth since 2000– Large Range of CD BGAs

Ball count: 300 to over 1000Body Size: 31 to 50mm

• Substrate Technology– 1 to 10 Metal Layers, 1 to 3 bonding tiers– ePTFE, Polyimide, and BT dielectric– Thermal & electrcal management is critical

Up to 40W in some cases : avg 15W

• Packaging Trends– Large price gap between PBGA & CD BGA

Many new TELCO chips going into F/C packagesProven W/B substrates up to 12 Gb/s

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Tape CSP Substrate & Packaging Trends

• General– Shrinking Packaged Tape Supply Base

High Density tape substrate packages converting to laminateLower costs and addition of ground planes makes this attractiveTwo metal tape packages still price prohibitive

• Substrate Technology– Remaining Supply Base = 5

SST, LGM, H.Cable, Compass & ToppanAll others withdrawn from high density tape packagingHowever, many new players to Camera Flex

• Packaging Trends– Camera Module thriving in tape substrate platforms

Low density, uncomplicatedFits different supply stream than high density packages

– Parlex, Interflex, MekTec, Mflex


Rigid CSP Substrate & Packaging Trends

• General– Density, Density, Density– Massive growth in hand-held market

• Substrate Technology– Via Density : 400k+ vias / sq. meter– Pattern Density : 50um L/S common– Surface Finish

Selective OSP finish of choice

• Packaging Trends– Stacked Die– Packages Getting Thinner

4 Layer Ultra Thin CSP = 220 um +/_ 30um– Packages Getter Smaller / Denser

0.5mm & 0.4mm ball pitch– Transition to FC to reduce inductance of wires

Concerns with Impedance for MCM

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SiP Substrate & Packaging Trends

• General– RF Modules generally do not require advanced design rules

Higher levels of integration will drive adoption of more 4 layerstack-ups for RF Modules

– Transition from custom core materials to standard materials

• Substrate Technology– 65um line/space, 250 um drilled vias, >0.2 mm core, etc.– Exotic materials used when embedding transmission line

structures in the laminate– Selective Ni/Au plating for improved reliability– Double image processing

• Packaging Trends– MCM SiP

Embedded BALUNs & Filters– Flip-Chip SiP

Si/SiGe FC : Sn/Pb EutecticGaAs FC : Copper Pillar


FC Substrate & Packaging Trends

• General– Material cost is 60-80% of flip chip cost

• Substrate Technology– Most advanced set of materials & design rules used– Material cost will determine future of flip chip

Addition of layers driving functionality… but also driving cost– Four clear segments of substrate technology today

• Packaging Trends– Broken into cost segments and sophistication

HDI –I =HDI –II =HDI –III =HDI –IV =

(1-n-1) : ≥ 100um Line Pitch = Mixed Costs(1-n-1), (2-n-2) : ≥ 80um Line Pitch = Cont. Margin : Volume(3-n-3), (4-n-4) : ≥ 40um Line Pitch = High Cost : but dropping(Core-less) : ≥ 30um Line Pitch = Highest Cost

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Flip Chip Substrate Options

• HDI –II (2-2-2)– Two Methods - Reinforced Glass on

core or ABF on Core– Heat management necessary for

processors

• HDI –III (3-N-3+ & 5/7 Lyr ePTFE)– Two Methods –

ABF on Core or ePTFE Buildup

– All packages require heat management

• HDI –I (1-N-1)– Virtually all structures use glass

reinforced structures with lased vias– Very little heat dissipation concerns


Flip Chip Substrate Options “Supply Base & Technology”

• Flip Chip Tier IV = Core-less Structures– Filled via structures – Drop down connections – no stagger

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Substrate Material Transitions “Embedded Components”

• Embedded Resistors– Very costly and too large for packages

Good for Motherboards, not practical for substrates

• Embedded Capacitors– Two Choices : Thick film or Thin film– Barriers to Technology Emergence:

Design Tools Needed Testing – known good passivesCost : need 6-8 components/ sq.cm to be competitive

• Embedded Planar Structures– Inductors, Baluns and Filters

Designed into substrate


Substrate Design RuleEvolution

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Bond Finger Pitch (µm)

Bond Finger Width (µm)

Bond Finger Space (µm)

Pattern Width / Space -R (µm)-T

Laser Via / Pad Size (µm)

Mech Via / Pad Size (µm)

Cu Foil / Plating (µm)

2004 2006

100

55

25

50 / 5018 / 17

75 / 200

150 / 300

5 / 10

2005

90

50

20

40 / 4018 / 17

60 / 150

100 / 250

3 / 10

90

50

20

35 / 3515 / 15

50 / 125

75 / 200

3 / 5

2003

130

60

25

60 / 60

100 / 250

150 / 350

7 / 10

Substrate Design Rules“Wirebond Substrates”

2003

110

60

25

60 / 6020 / 20

100 / 250

200 / 350

7 / 10


Substrate Design Rules“Flip Chip Substrates”

2003 2004 2005100 100 60

160 140 130100 90 85250 220 200100 100 100

45/45 37.5/37.5 30/30BT/PHP BT/PHP BT/PHP

40 35 35100/220 80/150 60/10035/35 30/30 25/25

2 2 215 12 1010 10 10

130/215 120/200 120/200

25 20 20

Glass Reinforced

AUS 303/703, BGX700 20µ

BT HS, E679F(G)

2003 2004 2005400 400 400

350 300 150200 150 100

50/50 40/40 30/30

33 30 2450/100 50/90 50/8025/25 20/20 15/15

4 4 510 10 1010 10 10

140/200 130/180 110/150

20 17.5 15

Film Based

BT, E679F(G), R5715S (L)

BGX5E, AUS703, SR7000/7200G 15µ

PHP900 DC5-4, IR6, THP1000 DX1

Core Design Rules Min Core Thick - (mm) Desired Core Material TypeLaser Min Via Pad Size (µm) Laser Min Via Size (µm) Mech Min Via Pad Size (µm) Mech Min Via Size (µm) Min Line Width / Space (µm) Via Fill Material (µm)

Min Dielectric Thickness (µm) Min Via Drill / Pad Size (µm) Min Line Width / Space (µm) Max B.U. Layers Min Trace Plating Thickness (µm) Min Via Plating Thickness (µm) Bump Pad Size / Pitch (µm) S/M Type and Thickness (µm) S/M Min Registration Toler. (µm)

B.U. Design Rules

2003 2004 200535 35 35Cu Cu Cu

35 35 3550/110 50/90 35/9025/25 25/25 20/20

12 12 1212 12 12180 150 150

25 25 25

4 per side

LPI/PTFE

ePTFE

200 clearance

Etched Core Clearances

N/APTFE

The Break-down …

GlassGlass FilmFilm ePTFEePTFE

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Substrate Supplier Trends “Flip Chip Substrates”

– Historically :

• Core Transitions

– Today, density of chip is forcing migrationThinner cores 0.8mm to 0.4mmMultilayer coresMore signals through the core

800 µm core PTH pitch & 100 µm line and space


Substrates in Transition

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Substrate Innovation Stagnating

New New Solution Solution RequiredRequired

Prices Will Prices Will Not Drop Not Drop Below This Below This PtPt

Operation Break Even

Total CostTo

Manufacture

MarginMargin

Rigid CSP

FC 2-N-2PBGA 2L

FC 3+-N-3+

1-N-1 PBGA

Tape CSPPBGA 4L

FC 1-N-1

4 Lyr &1-N-1 SiP

Why are Suppliers not Investing??Why are Suppliers not Investing??


AdvancedMotherboard PBGA

PBGAHDI

MotherBoard

SOA = State of Art

Need InvestmentOpportunity

Advanced BGA

CSPPBGA

Adv-PB, SiPAdv-C

Interposer BGA

CSPPBGA, FC

Adv-PB, SiPAdv-C

1990 1994 1998 2000 2002 2004

BGA Board Manufacturing Trends

JCI, CCIKCC

PBGACSP

SBGA

IBI, SGTiLG, SSE

ST

Std Drill225kVias

Std CuPatternPlate

Std Image75umL/S

Adv Drill275-400k

Vias

Adv CuPatternPlate

Adv Image45umL/S

SOA Drill400k+B-Vias

Via FillPatternPlate

SOA Image20umL/S

JCI, IBISSE

JCI, SSEIBI, LG

NanYa,UMTC

JCI, IBISSE

IBM, KYOIBI

JCI, PPTKinsus

NanYa,UMTCSGTi

UMTCKinsus,Kyo

NanYa

Who Next?

Eastern

CSP, WLPBGA, FC

Adv-PB, SiPAdv-CExited

KCC

ACL

Astron

Hadco

Merix

CCI

DTI

LG

Unicap

SMST

Compeq

WUS DTI

Boardtek

KCCDDE

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Advanced BGACSP, FC, SiPPBGA

Std Drill Std Plate Std ImageAdv Drill

400kVias

Adv Plate

“Shut”Adv

Image< 50um

Std Drill225kVias

Std Plate

Std Image

> 65um

Adv CostStd Cost

BGA Board Manufacturing Trends

Motherboard“Needed Growth”

$250 Sq. M $400 Sq. M $200 Sq. M

LasersSteppersGlass AW

ENIGSelect OSPBussless

LowCost

Laminate


Substrates… Lost in Translation

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Translating Die Complexity“Substrate vs. Interposer”

• Substrates are Slipping Further Behind Foundry Technology– 130 & 90-nm processes are maturing, but still have challenges:

Copper MetalizationLow-K DielectricMixed Signal Integration - SoC

I.C’s need a translator to the motherboardInterposer has moved directly into critical path of wafer fabrication roadmap

– Wafer Level InterposersUsing thin film techniques for interstitial via connection to die (RDL)Not a substrate…. merger of die & package technologies

Interposer manufactured at back-end or front-end


Wafer Level Interposers

• Wafer level CSP

– Technology where most or all of the process steps are carried out at the wafer level (RDL)

Method of choice to translate from die to motherboard for true CSP

Able to redistribute with 15um lines/spacesDoing it better, cheaper with new solutionsOnly real potential 0.3mm solution knownHowever, WLP today is most appropriate for low pin-count, small chips

– Why?

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Translating Die Complexity“Substrate vs. Interposer”

Interposer Negates Need for SubstrateISP’s (Integrated Service Providers)

– Filling space once owned by substrate fabricators and assemblers


Translating the Die

• The Substrate Gap…– RDL & Bump technologies have won the 1st round

However, limited to fan-in approaches only 0-100 I/O

And, limited in routing complexity> 100 I/O, much more costly, compliant bump approaches required

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• An Opportunity?

Translating the Die

– The Ideal Scenario…. simplification of the process !!Extreme miniaturizationLower manufacturing costsBetter reliabilityBetter performance

Yes !!

– The Industry Needs a New Solution


Translating the Die“Ultimate Interposers”

25um L/S

1-2-1 B.U.10um L/S

Ultimate Interposer

100um

250um

250um 250um

30um

10 Channels ofRouting in ReinforcedAll Vias are Pad-less

18um L/S

Adv.Tape

250um

“Best in Class”Substrates

Today”

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Translating the Die “2-2-2 Re-Designed into 1-2-1”

Took 37.5mm 1156 I/OAll Routing on Single Plane


Translating the Die“Ultimate Interposers”

10 µm lines10 µm spacesAramid

10 µm lines10 µm spaces

ePTFE

Multiple Dielectrics

Possible

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Translating the Die“The Ultimate Interposer”

• A Giant Step Forward…

~ Industry Changing Technology ~~ Industry Changing Technology ~

1. Recessed features prevent migration and shorting2. Reduction in number of steps to manufacture a substrate3. Potential elimination of Ni, Au interconnects – Cu only

interconnects possible 4. Dielectrics can be tailored to electrical needs5. Choice of buildup on wafer 6. Very high yielding process 7. Reduced die size and die pad / pitch as a result8. Better thermal performance9. Extremely dense due to miniaturization10. Lower Cost

substrates … lost in translationewh.ieee.org/soc/cpmt/presentations/cpmt0403.pdf ·...

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