Stuck-Open and -Short Faults

Stuck-at fault assumption: components fault-free; interconnects faulty

Shorts formed by unintended connectionsOpens resulted from breaking the connection

Corresponding logical faults: stuck-at value v (v ∈ {0,1})

Example: Opens as s-a-v Faults

stem fan-out branch

open

stuck lineMultiple s-a-v’s

stuck line

open

Single s-a-v

Single Stuck-at-Value FaultsSingle s-a-v: single line permanently tied to 0 or 1

Most commonly usedCan represent many other fault typesRelatively “small” in size

Three properties define a single stuck-at faultOnly one line faultyFaulty line permanently set to 0 or 1Fault present at input or output of gate

Multiple s-a-vFor n lines: 3n-1 stuck line combinations vs. 2n in single s-a-v

S-a-v model: Gates still functioning correctly!

Fault Detection – Overall Process

Three major parts:Reduction in number of faults: use of equivalence and dominance relationFault simulation: O(n2) procedure to evaluate test vector setTest pattern generation: search for vectors detecting the faults

Book – Ch. 4, Sec. 1-3

Relating and Classifying FaultsFault equivalence: two faults with same effectFault dominance: tests for dominating fault detect the otherExample:

Fault Collapsing: no equivalent, dominated fault

a

b

c

d

x1

x2x3

f

s-a-1Equivalent:

s-a-1

Equivalent Faults

Consider single output n-bit input circuit, f0(V), where V is an n-bit Boolean vector. Let f1(V) and f2(V) be different faults detectable by V1 and V2.

When V1 = V2 = V, then

hence

1)()( 1110 =⊕ VfVf1)()( 2220 =⊕ VfVf

[ ] [ ] 1)()()()( 2010 =⊕⊕⊕ VfVfVfVf

0)()( 21 =⊕ VfVf

Fault Equivalence - Definition

Def.: Two faults f1(V) and f2(V) of a Boolean circuit are equivalent iff

Equivalent fault are also called indistinguishable and have exactly the same set of tests.

0)()( 21 =⊕ VfVf

Fault Equivalence - Summary

Number of fault sites in a Boolean gate circuit = #PI + #gates + # (fanout branches)Fault equivalence: Two faults f1 and f2 equivalent if all tests detecting f1 also detect f2

Faulty functions corresponding to equivalent faults f1 and f2 identical

Fault collapsing: All single faults of a logic circuit divisible into disjoint equivalence subsets

All faults in a subset are mutually equivalentCollapsed fault set containing one fault from each equivalence subset

ab c

sa1

sa1sa1

sa0

sa0

sa0

Pair-wise Equivalence in AND2

a b c a: s-a-0 a: s-a-1 b: s-a-0 b: s-a-1 c: s-a-0 c: s-a-10 00 0 0 0 0 0 10 01 0 1 0 0 0 11 00 0 0 0 1 0 11 11 0 1 0 1 0 1

sa0

sa0sa0a

bc

sa1sa1

sa1

Pair-wise Equivalence in OR2

a b c a: s-a-0 a: s-a-1 b: s-a-0 b: s-a-1 c: s-a-0 c: s-a-10 00 0 1 0 1 0 10 11 1 1 0 1 0 11 10 0 1 1 1 0 11 11 1 1 1 1 0 1

Pair-wise Equivalence

ab

sa1csa1sa0

sa0

sa1sa0

ab

csa0 sa1

sa0 sa1

sa1sa0ab c

sa1sa0

sa1sa0

sa0sa1

ab c

sa1sa0

sa1sa0

sa0sa1

a sa0sa1

sa1sa0

c

Fault Collapsing

All design faults partitioned into equivalence sets

All faults in each equivalence set are equivalent to each otherInstead of simulating all design faults, one fault from each equivalence set is selected for simulations. This process of selection is called fault collapsing.

Set of selected faults is the equivalence collapsed set

faultsallofSetfaultscollapsedofSet

ratioCollapsed =

Equivalence Collapsing–Example

sa0sa0sa0

sa0sa0

sa0

sa0sa0sa0sa0

sa0

sa0

sa0

sa1sa1

sa1sa1sa1

sa1sa1sa1sa1

sa1

sa1

sa1

sa0

sa0

sa0

sa0sa1

Faults removed after collapsing

sa1

sa1

sa1

Collapse Ratio=1630

= 0.533

Fault Dominance

Def.: Let Tg be set of all test vectors that detect fault g. Fault f dominates fault g iff f and g are functionally equivalent under Tg

Fault f dominates g iff any test t that detects g also detect f

Conclusion: It is necessary to generate only test vectors Tg to detect both f and g

Tg Tf TfTg ⊆

Fault Dominance

Def.: If all tests of fault f1 detecting another fault f2, then f2 dominate f1

Two faults also called conditionally equivalent w.r.t. test set of f1Two faults f1 and f2 dominating each other are equivalent

Dominance fault collapsingIf fault f2 dominates f1, then f2 removed from fault listWhen using dominance fault collapsing, then sufficient to consider only input faults of Boolean gates

sa0

sa0 sa

0ab

c

Fault Dominance in OR2

a b c a: s-a-0

a: s-a-1 b: s-a-0 b: s-a-1 c: s-a-0 c: s-a-10 00 0 1 0 1 0 10 11 1 1 0 1 0 11 10 0 1 1 1 0 11 11 1 1 1 1 0 1

Fault c:s-a-0 dominates faults:a:s-a-0 and b:s-a-0

Fanout-Free Circuits

Def.: Fanout Free Circuit - Single fanout on each node

Theorem: Test set detecting all single s-a-v faults at primary inputs detects all faults in fanout-free circuits

Def.: Primary inputs and fanout branches are called checkpoints

Theorem: Detection of all s-a-v faults at checkpoints is sufficient for detecting all such faults in the circuit

Multiple Stuck-at Faults

Multiple stuck-at fault affecting more than one circuit lines with combination of (0,1) valuesTotal number of single and multiple stuck-at faults in circuit with k single fault sites 3k-1Why taking about multiple s-a-v faults

Tests for single s-a-v not necessarily sufficient for detecting multiple s-a-v faults

Single fault test can fail to detect target fault if another fault present– Masking of one fault by another rare

Statistically single fault tests covering very large number of multiple faults

Redundant and Detectable Faults

Def. (Redundant Fault): Any fault that does not modify the I/O function of circuit called redundant fault

Redundant fault not detected by any test, and can be removed from circuit without changing its output function.

Removal of redundant s-a-v faults often used for circuit optimization

Example: Redundant q s-a-1

Bushnell and Agrawal

Redundancy Removal – AND(n)

Given: s-a-1 at input to AND(n) undetectableSolution: Place ‘1’ at this input – equivalent to substituting AND(n) with AND(n-1)

Given s-a-0 input of AND(n) undetectableSolution: Replace AND(n) with ‘0’ signal

sa1

x1x2xn

x2xn

sa0

x1x2xn

Redundant Fault Elimination

Simplifications to circuit based removal of redundant single s-a-v faults

AND(NAND) input s-a-1

AND(NAND) input s-a-0

OR(NOR) input s-a-0

OR(NOR) input s-a-1

Remove gate, replace by 0(1)

Remove input

Remove gate, replace by 1(0)

Remove input

Simplification ruleOR(NOR) input s-a-1

Redundancy Removal - Example

ba

c

xy

z

s-a-0

ba

c

x

z

0

ba

cz

Modified circuit

Original circuit with s-a-0

Simplified circuit

Redundant Faults and Fault Masking

f s-a-0 tested when fault q s-a-1 not there

Bushnell and Agrawal

Redundant Faults and Fault Masking, cont.

f s-a-0 masked when fault q s-a-1 also present

Bushnell and Agrawal

Redundancy in Circuits

Sum of Products (SOP): two level, AND-OR circuit implementations

Prime – no literal can be removedIrredundant – no implicant can be removed

Theorem: Prime and irredundant SOPs are fully testable for stuck-at faultsProof:

(=>) s-a-v changes function of p.i. SOP expression(<=) non-prime implicants or non-irredundant

SOPs can have redundant faults

Test Effectiveness

Testability = (#detectable faults) / #faultsEffective faults = faults\redundant faults

(Must detect these to completely test the chip. Since redundant faults cause no harm, they should not be counted against us.)

(This is a better measure of how well a circuit is tested by a set of test vectors.)

Fault Modeling Literature J. A. Abraham and W. K. Fuchs, “Fault and Error Models for VLSI”, Proc. IEEE, vol. 75, No. 5, pp. 639-654, May 1986. J. P. Hayes, “On the Properties of Irredundant Logic Networks”, IEEE Trans. Computers, vol. C-25, No. 9, pp. 884-892, Sept. 1976.E. J. McCluskey and F. W. Clegg, “Fault Equivalence in Combinational Logic Networks”, IEEE Trans. Computers, vol. C-20, No. 11, pp. 1286-1293, Nov. 1971. J. E. Smith, “On Necessary and Sufficient Conditions for Multiple Fault Undetectability, IEEE Trans. Computers, vol. C-28, No. 10, pp 801-802, Oct. 1979.

Testing Tools Availability

CMC Distribution – Mentor

ls 2004.4 installed on the system under /CMC/tools/mentor/dft/.

** To use the DFT tools, first type "use mentor-dft".

The following commands start the GUI for the various tools:% dftadvisor% fastscan% bsdarchitect% mbistarchitect

Conclusions

Combinational circuit and fault modelsLevels of abstractionStuck-at value faults

Equivalent and dominant faultsFault collapsing

Redundant faults