stm32 f4 series -...

STM32 F4 series

High-performance Cortex™-M4 MCU

Presentation highlights

The STM32 F4 series brings to the market the world’s highest performance Cortex™-M microcontrollersperformance Cortex -M microcontrollers

168 MHz FCPU/210 DMIPS363 Coremark score

The STM32 F4 series extends the STM32 portfolio 250+ compatible devices already in production, including the p y p , gF1 series, F2 series and ultra-low-power L1 series

The STM32 F4 series reinforces ST’s current leadership in Cortex-M microcontrollers, with 45% world market share by units in (2010 or cumulated 2007 to Q1/11) according to ARM reporting

STM32 F4 seriesHigh-performance digital signal controller

Single precisionEase of use

FPUBetter code efficiencyFaster time to marketEliminate scaling and saturationEasier support for meta-language tools

(M tl b )

DSPMCUWhat is Cortex-M4?

(Matlab…)

Harvard architectureSingle-cycle MACBarrel shifter

Ease of use of C programmingInterrupt handlingUltra-low power

Cortex-M4Ultra low power

STM32 F4 Series highlights 1/4

ST is introducing STM32 products based on Cortex M4 core. Over 30 new part numbers pin-to-pin and software compatibleOver 30 new part numbers pin to pin and software compatible with existing STM32 F2 Series.

Th DSP d FPU i t ti bi d t 168MhThe new DSP and FPU instructions combined to 168Mhz performance open the door to a new level of Digital Signal Controller applications and faster development time.

STM32 Releasing your creativity

4


Advanced technology and process from ST:M l t ART A l t ™Memory accelerator: ART Accelerator™Multi AHB Bus Matrix90nm process90nm process

Outstanding results:210DMIPS at 168Mhz. Execution from Flash equivalent to 0-wait state performance up to 168Mhz thanks to ST ART Accelerator

5


More MemoryU t 1MB Fl hUp to 1MB Flash,192kB SRAM: 128kB on bus matrix + 64kB on data bus dedicated to the CPU usageg

Advanced peripherals shared with STM32 F2 SeriesUSB OTG High speed 480Mbit/sEthernet MAC 10/100 with IEEE1588PWM High speed timers: Now 168Mhz max frequency!PWM High speed timers: Now 168Mhz max frequency!Crypo/hash processor, 32-bit random number generator (RNG)32-bit RTC with calendar: Now with sub 1 second accuracy, and

6

y<1uA typ!


Further improvementsLow voltage: 1 8V to 3 6V VDD down to 1 7*V on mostLow voltage: 1.8V to 3.6V VDD , down to 1.7 V on most packagesFull duplex I2S peripherals12-bit ADC: 0.41µs conversion/2.4Msps (7.2Msps in interleaved mode)High speed USART up to 10.5Mbits/sg p pHigh speed SPI up to 37.5Mbits/sCamera interface up to 54MBytes/s

7

*external reset circuitry required to support 1.7V

STM32 F4 series – applications served

Points of sale/inventory management

Building management

Industrial automation Security/fire/HVACIndustrial automation and solar panels

Secu ty/ e/ C

Test and measurementTransportation

Test and measurement

Medical

Consumer

2Communication 2

STM32 F4 block diagramFeature highlight

168 MHz Cortex-M4 CPU

Floating point unit (FPU)

ART Accelerator TM

Multi-level AHB bus matrix

1-Mbyte Flash, 192-Kbyte SRAM

1.7 to 3.6 V supply1.7 to 3.6 V supply

RTC: <1 µA typ, sub second accuracy

2x full duplex I²S2x full duplex I S

3x 12-bit ADC 0.41 µs/2.4 MSPS

168 MHz timers 2168 MHz timers 2

STM32 F4 portfolio

22

STM32 product series4 product series

22

STM32 – leading Cortex-M portfolio

22

The cheapest and quickest way to discover the STM32F4Everything included for a quick start with the STM32F4 serie

Order code: STM32F4DISCOVERYAvailable in ST stock from October 2011

In circuit ST-LINK/V2 debugger / programmer included to debug Discovery kit applications or other target board applications.

Dedicated web site www.st.com/stm32F4discoveryLarge number of examples ready to runS h tiSchematicsForums and more

13

STM32F4 Discovery BoardOn-board ST-LINK/V2 with selection mode switch to use the kit as stand-alone ST-LINK with SWD connector ST-LINK/V2

Designed to be powered by USB or by external power 5V or 3.3V supply

Can supply target application with 5 Volts or

SWD connector

Ca supp y a ge app ca o 5 o s o3 Volts

Two User LEDs (Green and Blue)Audio codec

STM32F407VGT6Audio codecMems Micro (MP45DT02)

One user Push Button

User button

Extension header for all QFP64 I/Os for quick connection to prototyping board or easy probing

Audio Jack

14

September : STM32F4 eval board

Eval board : STM3240G-EVAL : 21st of SeptemberFor any needs before contact your local ST supportFor any needs before contact your local ST support

Sample :21st of September

LQFP100 STM32F407VGT6LQFP144 STM32F457ZGT6LQFP176 STM32F457IGT621 of September LQFP176 STM32F457IGT6BGA176 STM32F457IGH6LQFP64 STM32F455RGT6

Full production November

Advanced Information15

p2011

STM32 F4 key features

STM32 F4 Key features

11

Real time performance

STM32 F4 series: Cortex M4-based



What is Cortex-M4?

DSPMCUHarvard architectureSingle-cycle MACBarrel shifter



1

STM32F4 versus competitors

11

STM32 F4: World’s #1 in performance

Dhrystone

It takes ART to be #1 in performance: It is a combination of core embedded 1It takes ART to be #1 in performance: It is a combination of core, embedded Flash design, process, acceleration techniques. 1

ST’s ART Accelerator™

The adaptive real-time memory accelerator unleashes the Cortex-M4 core’smaximum processing performance equivalent to 0-wait state executionFl h t 168 MHFlash up to 168 MHz

11

Real-time performance

32-bit multi-AHB bus matrix Compressed audio stream (MP3) to 16kByte SRAM

MP3 decoder code execution by coreAccess to the MP3

data for decompression

Decompressed audio stream to 112kByte SRAM

DMA transfer to audio output stage

(I2S)

User interface: DMA transfers of

the graphical icons blockblockfrom Flash to

display

rb4

rb4 Use the updated chart provided by Olivier Ferrand. Also, we will use the example of datatransfers provided by Olivier Ferrand.Annimations as in the F4 video would be great.renaud bouzereau, 8/30/2011

Outstanding power efficiency

Outstanding power efficiency

230 μA/MHz, 38.6 mA at 168 MHz executing gCoremark benchmark from Flash memory (with peripherals off), made

Typical values in VBAT mode

possible with:ST’s 90 nm process allowing the CPU core

ART Accelerator™ reducing the number of accesses to FlashV lt li t ti i f / ti

yp BAT to run at only 1.2 V

Voltage scaling to optimize performance/power consumptionVDD min down to 1.7 VLow-power modes with backup SRAM and RTC support

1p p pp

1

Low power and real life applications

Low power in real life applications is not just Low-power modeNeed to consider the % of time spend in LP mode and in Run mode

% Low power mode

μA/MHz%

RunMode

Run

modeMode

Run

Low powertime

Low power

μA/MHz

Average consumption

μA/MHz

1Average consumptiontime 1

Superior and innovative peripherals

Superior and innovative peripherals

Ethernet with IEEE 1588v2

Audio architecture2 USB OTG

2 full duplex I²S

PWMs @ 168 MHz and

ADC 2 4 MSPS

HW crypto/hash coprocessor

and2 full duplex I S ADC 2.4 MSPSand<1 µA RTC

11

Digital Camera Interface

Digital Camera interface, up to 54 Mbyte/sThe Camera interface is a universal 8 to 14-bit parallelThe Camera interface is a universal 8 to 14 bit parallel interface (no industry standing name). It supports the following data formats :

- 8-bit progressive video monochrome or raw bayerp g y-YCbCr 4:2:2 progressive video-RGB 565 progressive video compressed data (like JPEG)It also supports the following features:continuous mode or snapshot (a single frame) mode-continuous mode or snapshot (a single frame) mode

-automatically image cropping-8-word FIFO.-AHB slave interface with capability to control the GP-DMA (request/acknowledge)

i 1 h lusing1 channel.-Various Interrupts Flags such as End Of Line, End of Frame, Vertical Synchronization, Overun or Errors Flags

29

Crypto/Hash Processor and RNG

Encryption/DecryptionDES/TDES (data encryption standard/triple data encryption standard): ECB (electronic codebook) and CBC (cipher block chaining) chaining algorithms, 64-,128- or 192-bit keyAES (advanced encryption standard): ECB, CBC and CTR (counter mode) chaining algorithms, 128, 192 or 256-bit key

Universal hashSHA-1 (secure hash algorithm)SHA 1 (secure hash algorithm)MD5

True random number generator (RNG) that delivers 32-bit d b d d b i t t d lbit random numbers produced by an integrated analog circuit.

30

Crypto/Hash Processor performance

AES DES TDES

192*** 128** or 64*

Key sizes 128, 192 or 256 bits 64* bits

* 8 parity bits

192 , 128 or 64bits* 8 parity bits : Keying option 1** 16 parity bits: Keying option 2***24 parity bits: Keying option 3

Block sizes 128 bits 64 bits 64 bits

Time to process 14 HCLK cycle for key = 128bits

16 HCLK cycle for key = 16 HCLK cycles 48 HCLK cyclesone block16 HCLK cycle for key 192bits

18 HCLK cycle for key = 256bits

16 HCLK cycles 48 HCLK cycles

Type block cipher block cipher block cipheryp

Structure Substitution-permutation network Feistel network Feistel network

1977

31

First published 1998 1977 (standardized on January 1979)

1998 (ANS X9.52)

Crypto/Hash Processor

Key: 128 192 and 256 bit

AES ECB CBC CTR

DMA request for incomingdata transfer

DMA request for outgoing data transfer

Key: 128-, 192- and 256-bit

Key: 64-, 128- and 192-bit

TDES

Ong ng

ECB CBC

Key: 64-bit

y ,

DES

ut F

IFO

put

FIFO

ta s

wap

pi

ta s

wap

pi

ECB CBC

Key: 64 bit

CRYPTO ProcessorInp

OutDa

Da

FlagsBUSY OFFU OFNEIFNFIFEM OUTRISINRIS

CRYPTO Gl b l i t t

OUTIMINIMOUTMISINMIS

32

32

CRYPTO Global interrupt

(NVIC)

USB OTG

Up to 2 USB OTG peripherals (on STM32F4x7 devices) compliant with the USB 2 0 specificationdevices), compliant with the USB 2.0 specification and with the OTG 1.0 specification.

One is Full Speed (12 Mb/s) onlyOne is Full Speed (12 Mb/s) only, One is Full Speed or High Speed (480 Mb/s), Both embeds a FS PHY

33

USB OTG HS

The USB FS/HS peripheral supports both full-speed and high-speed operations. It features aspeed and high speed operations. It features a UTMI low-pin interface (ULPI) to connect an external HS PHY device. The OTG PHY is connected to the microcontroller ULPI port through 12 signals. Features a dedicated RAM of 4 Kbytes with advanced FIFO controlD di t d DMA t llDedicated DMA controller

34

Audio architecture

Two PLLs are available for more flexibilty of the system:

The main PLL (PLL) clocked by HSI or HSE used toThe main PLL (PLL) clocked by HSI or HSE used to generate the System clock (up to 168MHz), and 48 MHz clock for USB OTG FS, SDIO and RNG. A dedicated PLL (PLLI2S) used to generate an accurateA dedicated PLL (PLLI2S) used to generate an accurate clock to achieve high-quality audio performance on the I2S interface.

USB OTG peripherals facilitate audio synchronization: each time a SOF event occurs a pulse can be output on a pindynamic trimming capability of SOF framing period in host

dmode2xI2S Full duplex peripherals with:

Less than 0.5% error on sampling frequency

35

Clock input in case an external high quality audio PLL is needed

More peripherals improvements

Flexible Static Memory Interface for external LCD, SRAM, PSRAM, NOR and NAND Flash, CompactFlashrunning at up to 60MHz to expand memory space or support an external display3 SPIs running at up to 37 5 Mbit/s3 SPIs running at up to 37.5 Mbit/s, 6 USARTs running at up to 10.5Mbit/sAnalog: g

ADCs and DACs work down to VDD min3x 12-bit ADC, 2.4 MSPS, up to 7.2MSPS in interleaved mode

F t GPIO (84 MH t li d)Fast GPIO (84 MHz toggling speed)RTC: sub second accuracy, <1uA typ

36

Maximum integration

The 1-Mbyte Flash and 192-Kbyte SRAM memories available in the product accommodatememories available in the product accommodate advanced software stacks and user data, with no need for external memoriesneed for external memories

4-Kbyte SRAM battery back-up: EEPROM used4 Kbyte SRAM battery back up: EEPROM used to save application state, calibration data

In addition, 528 bytes of OTP memory make it possible to store critical user data such as

1pEthernet MAC addresses or cryptographic keys 1

Extensive tools and SW

Extensive tools and SW

Evaluation board for full product feature evaluationHardware evaluation platform for all interfacesHardware evaluation platform for all interfacesPossible connection to all I/Os and all peripherals

Discovery kit for cost-effective evaluation and prototyping

STM3240G-EVAL

$349p yp g

Starter kits from 3rd parties available soon

STM32F4DISCOVERYLarge choice of development IDE solutions from the STM32 and ARM ecosystem

STM32F4DISCOVERY $14.90

Software LibrariesST software libraries free atwww.st.com/mcuC source code for easy implementation of allC source code for easy implementation of all STM32 peripherals in any application

Standard library – source code for implementation of all standard peripherals. Code implemented in demos for STM32 evaluation board

Motor Control library – Sensorless Vector Control for 3-phase brushless motors

DSP library – PID IIR FFT FIR (free with license agreement) ST engineered, tested, DSP library – PID, IIR, FFT, FIR (free with license agreement)

Audio library – MP3/WMA decoder, volume control, equalizer (free with license agreement)

g , ,documented and free

(free with license agreement).

40

Key messages to remember

STM32 F4 seriesWorld’s highest performanceWorld s highest performanceExtends the STM32 portfolio to over 250+ compatible devices One-in-two Cortex-M MCUs shipped worldwide is an STM32

Discovery kits available now

STM32F4DISCOVERY

Thank you

www.st.com/stm32f4

STM32F roadmap

STM32F series short term roadmap

STM32F4series

STM32F2i

Cortex-M4@ 168 MHz

STM32F1

series

Cortex-M3 @ 120 MHz

STM32F1series

Cortex-M3Cortex M3@ 72 MHzSTM32F0

seriesCortex-M0Cortex-M0

44

STM32 Next 2 Major Launch

STM32F4series

Cortex-M4@ 168 MHz

STM32F4 Cortex M4Increasing ST leadership in the performance race

STM32F0 Cortex M0Expanding Market Reach towards 8-16 bit

STM32F0

PR September 2011 Early 2012

STM32F0series

Cortex-M0Cortex-M0

45

Flash Size

STM32 F4 Roadmap

STM32 F4 2MB Flash Die

Flash Size (bytes)

2 MB


1 MB


512 K

256 K

46

100 pins LQFP

64 pinsLFQFP/WLCSP

144 pinsLQFP

176 pinsLQFP/UFBGA

Pin count208 pinsUFBGA

Flash Size

STM32 F4 Roadmap

STM32 F4 2MB Flash DieSamples Q3 2012

Flash Size (bytes)

2 MB

Samples Q3 2012Production end of 2012

1 MB

STM32 F4 1MB Flash DieProduction now

512 K

256 K

47

100 pins LQFP

64 pinsLFQFP/WLCSP

144 pinsLQFP

176 pinsLQFP/UFBGA

Pin count208 pinsUFBGA

Backup Slides

STM32 F4 Block diagram AHB2• Cortex M4 w/FPU 168 MHz

• pin-to-pin compatible with Mangusta

• More SRAM (192KB)

CORTEX M4 CPU+ MPU

+ FPU168 MHz

Flas

h I/F 1MB Flash

Memory

Encryption

Camera Interface

USB 2 0 OTG FS

AHB2(max 168Mhz)

s m

atrix

)More SRAM (192KB)

• Same IPS as Mangusta

• I2S: now full duplex

• New RTC sub second

168 MHz 192KB SRAM

JTAG/SW Debug Power SupplyReg 1.2V

POR/PDR/PVDETM

External Memory Interface

USB 2.0 OTG FS

bit m

ulti-

AH

B b

urb

iter (

max

120

MH

z)

• New RTC sub second precision

• Faster serial I/F

• Faster ADC

XTAL oscillators32KHz + 8~25MHz

POR/PDR/PVD

DMA16 Channels

Nested vect IT Ctrl

1 x Systic TimerUSB 2.0 OTG HS

Ethernet MAC 10/100, IEEE1588

Int. RC oscillators32KHz + 16MHz

AR

M ®

32-

bA

r

USB 2.0 OTG HS

• 64 pins to 176 pins

• 1.7V-3.6V Supply 80/112/140 I/Os

2x6x 16-bit PWM

5x 16-bit Timer

2x DAC + 2 TimersBridge

Bridge PLLClock Control

RTC / AWU

APB1(max 42MHz)

4KB backup RAM

AHB1(max 168Mhz)

2x 32-bit TimerA

PB2

(max

84M

Hz)

3x 12-bit ADC24 channels / 2Msps

Up to 16 Ext. ITs

Synchronized AC Timer 2x Watchdog(independent & window)

2x DAC + 2 Timers

1 x SPI

1x SDIO

3 x 16bit Timer2x CAN 2.0B

2 x SPI/I2S

49

24 channels / 2Msps

3x I2C2 x USART/LIN

1 x SPI4x USART/LIN

Temp Sensor

STM32 F2 portfolio

Flash Si e

STM32 F-2 Series portfolioFlash Size (bytes)

1MBSTM32F205ZG128 KB RAM

STM32F205VG128 KB RAM

STM32F205RG128 KB RAM

STM32F207ZG128 KB RAM


STM32F207IG128 KB RAME* E* E*

E* E*E* Ethernet, 2xUSB OTG camera IF

768 KSTM32F205VF STM32F205ZFSTM32F205RF

STM32F207VF128 KB RAM

STM32F207ZF128 KB RAM

STM32F207IF128 KB RAM

OTG, camera IF

1xUSB OTG FS/HSOTG, camera IF

512 KSTM32F205VE

128 KB RAM

STM32F205ZE

128 KB RAM

STM32F205RE

128 KB RAM

STM32F207VE128 KB RAM

STM32F207ZE128 KB RAM

STM32F207IE128 KB RAME* E* E*

Encryption peripheral on

STM32F217 and STM32F115E*



STM32F205RE128 KB RAM

STM32F207VC128 KB RAM

STM32F207ZC128 KB RAM

STM32F207IC128 KB RAM

256 K

E*E*E*

STM32F205VB64 KB RAM



STM32F205RB64 KB RAM

STM32F205RC96 KB RAM

128 K

51

100 pins LQFP

64 pinsLFQFP/WLCSP

144 pinsLQFP

176 pinsLQFP/UFBGA

Pin count

Flash Si e

STM32 F2 and F4 Series coverageFlash Size (bytes)

1MBSTM32F205ZG128 KB RAM


STM32F205RG128 KB RAM

STM32F207ZG128 KB RAM


STM32F207IG128 KB RAME* E* E*

E* E*E*

768 KSTM32F205VF STM32F205ZFSTM32F205RF

STM32F207VF128 KB RAM

STM32F207ZF128 KB RAM

STM32F207IF128 KB RAM

STM32 F2 to F4

U d Z512 K

STM32F205VE

128 KB RAM

STM32F205ZE

128 KB RAM

STM32F205RE

128 KB RAM



STM32F207IE128 KB RAME* E* E*

Upgrade Zone



STM32F205RE128 KB RAM



STM32F207IC128 KB RAM

256 K

E*E*E*

STM32F205VB64 KB RAM



STM32F205RB64 KB RAM

STM32F205RC96 KB RAM

128 K

52

100 pins LQFP

64 pinsLFQFP/WLCSP

144 pinsLQFP

176 pinsLQFP/UFBGA

Pin count

STM32 F4 Hardware tools

STM32 F4 Discovery kit

•Develop your applications easily with everything required for beginners andeverything required for beginners and experienced users to get started quickly.

•Based on STM32F407 in LQFP100 packageQ p g

•Includes on-board ST-LINK/V2,

Only $14.90*

54

*RRP

STM32 F4 Discovery kit

•STM32F407VGT6 MCU in LQFP100 package,•on-board ST-LINK/V2, •2x ST MEMS motion sensor and microphone,•Audio DAC,•USB OTG with micro-AB connector•Extension header for all LQFP100 I/OsEi ht LED•Eight LEDs:

55

STM32 F4 Eval Board from ST

Evaluation board for full product feature evaluationevaluation

Hardware evaluation platform for all interfacesPossible connection to all I/Os and all peripherals

Based on STM32F407 in UFBGA176 package

STM3240G-EVAL

$349*

56

*RRP

Starter kits from 3rd parties

STM32F4 starter kits from IAR and Keil available in Q4 2011in Q4 2011

Order codes:Order codes: IAR: STM3240G-SK/IARKEIL: STM3240G-SK/KEI

57

High Performance

How to benchmark microsThe core

The first think to consider is the core : no wait states shall be introduced to decrease the resultAs a consequence, the maximum frequency achievable is the q , q ymaximum frequency of the Flash

The compiler used for the code generation of the benchmark have aThe compiler used for the code generation of the benchmark have a significant influence on the result : for a same core, you can have two different benchmark result with two different compilers

59

0-ws performance chartDMIPS

150Good CPU, fast flash

100

125

75

50

25Equivalent CPU, better flash for STM32F4

Fcpu (MHz)

Competitor AM fl h

Competitor BM fl h

STM32 F4M fl h

40 8020 60 1000

60

Max flash frequency

Max flash frequency

Max flash frequency

All the results are with the best compiler for each MCU

How to benchmark microsThe flash acceleration

As the Flash access time is limiting the micro speed, wait state have to be introduce the reach higher frequencyThe influence of wait state is reduced using a flash accelerator gwhich combined a buffer and/or a cache system taking benefit of a wide access bus to the flash (ex.128-bit wide)

The quality and the efficiency of the flash accelerator can be evaluated looking at the loss of performance on a given benchmark each time a wait state is added

An excellent flash acceleration will result in no penalty each time a wait state is addedA poor flash acceleration will result in a big penalty each time a wait state is added

As a consequence, a fast flash or a powerful CPU may not

61

q p ynecessary means best MCU performance

FPU benefits and performance

FPU benefits in real life applications

High level approachMatrix, mathematical equations

Meta language toolsMatlab ,Scilab…etc…

C code generationFloating point numbers (float)Floating point numbers (float)

FPU No FPU No FPUDirect mapping

No code modificationHigh performance

Optimal code efficiency

Usage of SW libNo code modification

Low performanceMedium code efficiency

Usage of integer based formatCode modification

Corner case behavior to be checked(saturation, scaling)

Medium/high performance

63

Medium code efficiency

FPU assembly code generation

float function1(float number1, float number2){

float temp1, temp2;

temp1 = number1 + number2;temp1 number1 + number2;temp2 = number1/temp1;

return temp2;}

# float function1(float number1, float number2)# {# float temp1, temp2;# # 1 b 1 b 2

# float function1(float number1, float number2)# {

PUSH {R4,LR}MOVS R4,R0O S 0 1# temp1 = number1 + number2;

VADD.F32 S1,S0,S1# temp2 = number1/temp1;

VDIV.F32 S0,S0,S1## return temp2;

BX LR# }

MOVS R0,R1# float temp1, temp2;## temp1 = number1 + number2;

MOVS R1,R4BL __aeabi_faddMOVS R1,R0

# t 2 b 1/t 1# } # temp2 = number1/temp1;MOVS R0,R4BL __aeabi_fdiv

## return temp2;

POP {R4,PC}# }Call Soft-FPU

1 assembly instruction

64

Call Soft FPU

Floating point benchmark

Time execution comparison for a 29 coefficient FIR on float 32 with and without FPU (CMSIS library)

ExecutionTime

10x improvement10x improvementBest compromise

Development time vs. performance

65

FPUNo FPU

DSP benefits and performance

Single-cycle multiply-accumulate (MAC)

The multiplier unit allows any MUL or MAC instructions to be executed in a single cycle

Signed/Unsigned MultiplySigned/Unsigned MultiplySigned/Unsigned Multiply-AccumulateSigned/Unsigned Multiply-Accumulate Long (64-bit)

Benefits : Speed improvement vs. Cortex-M34x for 16-bit MAC (dual 16-bit MAC)2x for 32-bit MACup to 7x for 64-bit MAC

67

Saturated arithmetic

Intrinsically prevents overflow of variable by clipping to min/max boundaries and remove CPU burden due to software range checks

BenefitsAudio applications

0.51

1.5

Without

1 50

0.5

1

1.5

-1.5-1

-0.50

0.5Withoutsaturation

-1-0.5

00.5

11.5

-1.5

-1

-0.5

0

Withsaturation

Control applicationsThe PID controllers’ integral term is continuously accumulated over time. The saturation automatically limits its value and saves several CPU cycles per

-1.5-1

saturation automatically limits its value and saves several CPU cycles per regulators

Single-cycle SIMD instructions

Stands for Single Instruction Multiple Data

Allows to do simultaneously several operations with 8-bit or 16-bit data format

Ex: dual 16-bit MAC (Result = 16x16 + 16x16 + 32)Ex: Quad 8-bit SUB / ADD

BenefitsParallelizes operations (2x to 4x speed gain)Minimizes the number of Load/Store instruction for exchanges between memory and register file (2 or 4 data transferred at once), if 32-bit is not necessaryMaximizes register file use (1 register holds 2 or 4 values)

69

DSP performances for filtering applications

FIR filter execution time (CMSIS library)

100

80

100

10x improvement

60

10x improvementBest compromise

Development time vs. performance 17.9x improvement

Best performance

20

40 Requires effort for proper data management

0

32-bit floatFPU

32-bit floatFPU

16-bit fixed-pointSIMD ti i d

70

no FPU FPU SIMD optimized

DSP performances for control application

Cortex M3 (28-38 c.) Cortex M4 (18-28 c.)

LDRSH R12,[R4, #+12] LDR R10,[R4, #+12]

LDRSH R0,[SP, #+20] (1 single 32-bit load replacing two 16-bit load with sign extension. Gain: 2 cycles

Example based on a complex formula used for sensorlessmotor drive

SXTH LR,R8

MUL R8,LR,R0

LDR R1,[R4, #+44]

SDIV R0,R1,R7

Gain comes for load operations and SIMD instructions LDRSH R2,[R4, #+24]

LDRSH R3,[R4, #+26] LDR R2,[R4, #+22]

LDRSH R10,[R4, #+22] (1 single 32-bit load replacing to 16-bit with sign extension. Gain: 2 cycles)

SXTH R6,R6

instructions

Total gain on this part is 25 to 35% SXTH R6,R6

MLS R5,R6,R10,R5

MLA R5,R9,R12,R5 SMLSD R5, R10, R6, R5(1 SIMD instruction replacing two multiply-accumulate. Gain: 3 cycles)

ASR R6 R8 #+15

35%

ASR R6,R8,#+15

MLA R5,R6,R3,R5

SXTH R0,R0

MLS R5,R0,R2,R5 SMLSD R5, R0, R2(1 SIMD instruction replacing two multiply-( g yaccumulate. Gain: 3 cycles)

STR R5,[SP, #+12]

7171

ARM Cortex M4 in few words

Cortex-M processorsForget traditional 8/16/32-bit classifications

Seamless architecture across all applicationsE d t ti i d f lt l d fEvery product optimised for ultra low power and ease of use

Cortex-M0 Cortex-M3 Cortex-M4Cortex-M0 Cortex-M3 Cortex-M4“8/16-bit” applications “16/32-bit” applications “32-bit/DSC” applications

Binary and tool compatible

73

Cortex-M processors binary compatible

ARM Cortex M4 Core



What is Cortex-M4?

DSPMCUHarvard architectureSingle-cycle MACBarrel shifter



1

Cortex-M4 processor microarchitecureARMv7ME Architecture

Thumb-2 TechnologyDSP and SIMD extensionsSingle cycle MAC (Up to 32 x 32 + 64 > 64)Single cycle MAC (Up to 32 x 32 + 64 -> 64)Optional single precision FPU Integrated configurable NVICCompatible with Cortex-M3

Microarchitecture3-stage pipeline with branch speculation3x AHB-Lite Bus Interfaces

Configurable for ultra low power Deep Sleep Mode, Wakeup Interrupt ControllerPower down features for Floating Point UnitPower down features for Floating Point Unit

Flexible configurations for wider applicabilityConfigurable Interrupt Controller (1-240 Interrupts and Priorities)Optional Memory Protection UnitOptional Memory Protection UnitOptional Debug & Trace

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Cortex-M feature set comparisonCortex-M0 Cortex-M3 Cortex-M4

Architecture Version V6M v7M v7ME

Instruction set architecture Thumb, Thumb-2 System Instructions

Thumb + Thumb-2 Thumb + Thumb-2,DSP, SIMD, FP

DMIPS/MHz 0.9 1.25 1.25

Bus interfaces 1 3 3

Integrated NVIC Yes Yes Yes

Number interrupts 1-32 + NMI 1-240 + NMI 1-240 + NMINumber interrupts 1 32 + NMI 1 240 + NMI 1 240 + NMI

Interrupt priorities 4 8-256 8-256

Breakpoints, Watchpoints 4/2/0, 2/1/0 8/4/0, 2/1/0 8/4/0, 2/1/0

Memory Protection Unit (MPU) No Yes (Option) Yes (Option)

I t t d t ti (ETM) N Y (O ti ) Y (O ti )Integrated trace option (ETM) No Yes (Option) Yes (Option)

Fault Robust Interface No Yes (Option) No

Single Cycle Multiply Yes (Option) Yes Yes

Hardware Divide No Yes Yes

WIC Support Yes Yes Yes

Bit banding support No Yes Yes

Single cycle DSP/SIMD No No YesFloating point hardware No No Yesg p

Bus protocol AHB Lite AHB Lite, APB AHB Lite, APB

CMSIS Support Yes Yes Yes

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Cortex-M4 extended single cycle MAC

OPERATION INSTRUCTIONS CM3 CM416 x 16 = 32 SMULBB, SMULBT, SMULTB, SMULTT n/a 116 x 16 + 32 = 32 SMLABB, SMLABT, SMLATB, SMLATT n/a 116 x 16 + 32 32 SMLABB, SMLABT, SMLATB, SMLATT n/a 116 x 16 + 64 = 64 SMLALBB, SMLALBT, SMLALTB, SMLALTT n/a 116 x 32 = 32 SMULWB, SMULWT n/a 1(16 x 32) + 32 = 32 SMLAWB, SMLAWT n/a 1(16 x 16) ± (16 x 16) = 32 SMUAD, SMUADX, SMUSD, SMUSDX n/a 1

(16 x 16) ± (16 x 16) + 32 = 32 SMLAD, SMLADX, SMLSD, SMLSDX n/a 1(16 x 16) ± (16 x 16) + 64 = 64 SMLALD, SMLALDX, SMLSLD, SMLSLDX n/a 1

32 x 32 = 32 MUL 1 132 ± (32 x 32) = 32 MLA MLS 2 132 ± (32 x 32) = 32 MLA, MLS 2 132 x 32 = 64 SMULL, UMULL 5‐7 1(32 x 32) + 64 = 64 SMLAL, UMLAL 5‐7 1(32 x 32) + 32 + 32 = 64 UMAAL n/a 1

32 ± (32 x 32) = 32 (upper) SMMLA, SMMLAR, SMMLS, SMMLSR n/a 1(32 x 32) = 32 (upper) SMMUL, SMMULR n/a 1

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All the above operations are single cycle on the Cortex-M4 processor

Cortex-M4 DSP instructions comparedCycle countsCycle counts

CLASS INSTRUCTION CORTEX‐M3 Cortex‐M4Arithmetic ALU operation (not PC) 1 1

ALU operation to PC 3 3CLZ 1 1QADD, QDADD, QSUB, QDSUB n/a 1QADD8 QADD16 QSUB8 QSUB16 n/a 1QADD8, QADD16, QSUB8, QSUB16 n/a 1QDADD, QDSUB n/a 1QASX, QSAX, SASX, SSAX n/a 1SHASX, SHSAX, UHASX, UHSAX n/a 1SADD8, SADD16, SSUB8, SSUB16 n/a 1SHADD8, SHADD16, SHSUB8, SHSUB16 n/a 1UQADD8, UQADD16, UQSUB8, UQSUB16 n/a 1UQADD8, UQADD16, UQSUB8, UQSUB16 n/a 1UHADD8, UHADD16, UHSUB8, UHSUB16 n/a 1UADD8, UADD16, USUB8, USUB16 n/a 1UQASX, UQSAX, USAX, UASX n/a 1UXTAB, UXTAB16, UXTAH n/a 1USAD8, USADA8 n/a 1

Multiplication MUL, MLA 1 ‐ 2 1p ,MULS, MLAS 1 ‐ 2 1SMULL, UMULL, SMLAL, UMLAL 5 ‐ 7 1SMULBB, SMULBT, SMULTB, SMULTT n/a 1SMLABB, SMLBT, SMLATB, SMLATT n/a 1SMULWB, SMULWT, SMLAWB, SMLAWT n/a 1SMLALBB, SMLALBT, SMLALTB, SMLALTT n/a 1

Singlecycle

SMLAD, SMLADX, SMLALD, SMLALDX n/a 1SMLSD, SMLSDX n/a 1SMLSLD, SMLSLD n/a 1SMMLA, SMMLAR, SMMLS, SMMLSR n/a 1SMMUL, SMMULR n/a 1SMUAD, SMUADX, SMUSD, SMUSDX n/a 1

yMAC

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UMAAL n/a 1Division SDIV, UDIV 2 ‐ 12 2 – 12

Cortex-M4 non–DSP instructionsC l tCycle counts

CLASS INSTRUCTION CORTEX‐M3 Cortex‐M4Load/Store Load single byte to R0‐R14 1 ‐ 3 1 ‐ 3

Load single halfword to R0‐R14 1 ‐ 3 1 ‐ 3Load single word to R0‐R14 1 ‐ 3 1 ‐ 3Load to PC 5 5L d d bl d 3 3Load double‐word 3 3Store single word 1 ‐ 2 1 ‐ 2Store double word 3 3Load‐multiple registers (not PC) N+1 N+1Load‐multiple registers plus PC N+5 N+5Store‐multiple registers N+1 N+1Load/store exclusive 2 2Load/store exclusive 2 2SWP n/a n/a

Branch B, BL, BX, BLX 2 ‐ 3 2 ‐ 3CBZ, CBNZ 3 3TBB, TBH 5 5IT 0 ‐ 1 0 ‐ 1

Special MRS 1 1Special MRS 1 1MSR 1 1CPS 1 1

Manipulation BFI, BFC 1 1RBIT, REV, REV16, REVSH 1 1SBFX, UBFX 1 1UXTH UXTB SXTH SXTB 1 1UXTH, UXTB, SXTH, SXTB 1 1SSAT, USAT 1 1SEL n/a 1SXTAB, SXTAB16, SXTAH n/a 1UXTB16, SXTB16 n/a 1SSAT16, USAT16 n/a 1PKHTB, PKHBT n/a 1

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PKHTB, PKHBT n/a 1

16-bit DSP functions comparedRelative cycle counts for DSP tasks running on 16-bit data shown belowSmaller is better on the chart – Cortex-M4 is 30% to 70% better

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32-bit DSP functions comparedRelative cycle counts for DSP tasks running on 32-bit data shown belowSmaller is better on the chart – Cortex-M4 is 25% to 60% better

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DSP application example:MP3 audio playback

MHz required for MP3 decode (smaller is better !)MHz required for MP3 decode (smaller is better !)

83DSP Concept

M4 Benefits50% more performance than M3 for signal processing calculations

25% better than ARM9E at equivalent frequency

50% better than M3 for Audio (MP3 codec)5% better than ARM9E at equivalent frequency

MMACS 72 MHz 72 MMACS (32bits) or 144 MMACS (16bits)150 MHz 150 MMACS (32bits) or 300 MMACS (16bits)

Floating point UnitGraphic acceleration: moves like rotations and so on...Advanced algorithms: audio (voice recognition pitch detection) or imageAdvanced algorithms: audio (voice recognition, pitch detection) or image processingDirect Matlab interface: PC tools generate floating point code, directly portable on FPU. A fixed point device will require more care and

d t ti

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adaptation.

DSP lib provided for free by ARM

The benefits of software libraries for Cortex-M4Enables end user to develop applications faster

K d b t t d f l l l iKeeps end user abstracted from low level programmingBenchmarking vehicle during system developmentClear competitive positioning against incumbent DSP/DSC offeringsAccelerate third party software developmentAccelerate third party software development

Keeping it easy to access for end userMinimal entry barrier - very easy to access and use

One standard library – no duplicated effortsOne standard library – no duplicated effortsARM channels effort/resources with software partnerValue add through another level of software – eg: filter config tools

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DSP lib function list snapshot

Basic math – vector mathematicsFast math – sin, cos, sqrt etcInterpolation – linear, bilinearComplex mathComplex mathStatistics – max, min,RMS etcFiltering – IIR, FIR, LMS etcTransforms – FFT(real and complex) , Cosine transform etcMatrix functionsPID ControllerSupport functions – copy/fill arrays, data type conversions etc

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STM32 F4 vs.

STM32 F2

Differences in Core and System Architecture

STM32 F2 STM32 F4

C ARM C t M3 ( 2 0) ARM C t M4F * ( 0 1)Core ARM Cortex M3 (r2p0) ARM Cortex M4F * (r0p1)

Floating point calculation s/w Single precision h/wg p g p

Performance / with ART ON “0ws like” performance thanks to ART

“0ws like” performance thanks to ART Accelerator:thanks to ART

Accelerator:120MHz:1.65V-3.6V

ART Accelerator: 168Mhz: 2.1V–3.6V144MHz:1.8V–2.1V128MHz:1.7V–1.8V

SRAM internal capacity 128KB of system memory

192KB (128KB system memory + 64KB dedicated to CPU data)

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)

Differences in Core and System Architecture

STM32 F2 STM32 F4Internal Regulator Bypass Available only on WLCSP64 Available only on WLCSP64 and

(IRR_OFF pin) and BGA176 (BYPASS_REG pin) packages

O WLCSP64 thi

BGA176 (BYPASS_REG pin) packages

On WLCSP64 this functionality can not be dissociated from BOR OFF

BOR OFF and Internal regulator bypass are non exclusive on the above packages

VDD i t i f 1 8V d A il bl l WLCSP64 A il bl ll k (PDR ONVDD min extension from 1.8V down to 1.65V (requires BOR OFF) on F21.7V (requires BOR OFF) on F4

Available only on WLCSP64 package (IRR_OFF pin)

This functionality can not be dissociated from Regulator

Available on all packages (PDR_ON pin) except on LQFP64 pin package

This functionality can be dissociated from Regulator bypassdissociated from Regulator

bypassfrom Regulator bypass

Voltage Scaling (Internal regulator )

None Performance Optimization (150 MHz )

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output) max)Power Optimization (120MHz max)

Differences in Peripheral System Architecture

STM32 F2 STM32 F4FSMC (improvements) Remap capability on Remap capability onFSMC (improvements) Remap capability on

bank1-NE1/NE2, but no capability to access other banks

Remap capability on bank1-NE1/NE2, with access to other FSMC banks while remapped.

while remapped pp

I2S 2x I2S Half duplex 2x I2S Full duplex.

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New RTC implementation

STM32 F2 STM32 F4Calendar Sub seconds access

NO YES (resolution down to RTC clock)access to RTC clock)

Calendar resolution From RTCCLK/2 to RTCCLK/2^20

From RTCCLK/1 to RTCCLK/2^22

Calendar read and synchronization on the fly

NO YES

Alarm on calendar 2 alarms 2 alarmsSec, Min, Hour, Date/day

Sec, Min, Hour, Date/day, Sub seconds

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New RTC implementation

STM32 F2 STM32 F4Calendar Calib window : 64min

C lib ti tCalib window : 8s/16s/32s

Calibration Calibration step: Negative:-2ppm Positive: +4ppm

Calibration step: Negative or Positive:3.81ppm/1.91ppm/0.95 ppm

Range [-63ppm+126ppm]pp pp pp

Range [-480ppm +480ppm]Timestamp YES YESTimestamp YES

Sec, Min, Hour, DateYESSec, Min, Hour, Date, Sub seconds

Tamper YES (2 pins /1 event)Edge Detection only

YES (2 pins/ 2 events)Level Detection with Configurable filtering

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Compatible board design for LQFP100-144-176 and BGA 176 packages

F2xx – RFU (reserved for future use) can be connected to VDD/VSS/NC

F4xx – PDR_ON can be connected to VDD or VSS (should be connected to VDD to maintain compatibility with the STM32 familyfamily

RFU / PDR_ON

VDD VSS

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Compatible board design forWLCSP64+2 package

F2xx – IRR_OFF(Internal Reset and Regulator OFF pin) can be connected to VDD/VSS. The BOR and the Internal Regulator is switched OFF when IRR_OFF is set to VDD.

F4xx – PDR_ON (BOR OFF pin). The BOR is switched OFF when PDR_ON pin is set to VSS. (Internal regulator is controlled (Internal regulator is controlled independently using the BYPASS_REG pin)

IRR_OFF/ PDR_ON

VDD VSS

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Thank you

www.st.com/stm32f4

Glossary

ART Accelerator ™ : ST’s adaptive real-time acceleratorCMSIS: Cortex™ microcontroller software interface standard C S S Co e c oco o e so a e e ace s a da dMCU: microcontroller unitDSC: digital signal controllerDSP: digital signal processorDSP: digital signal processorFPU: floating point unitRTC: real-time clockMPU: memory protection unitFSMC: flexible static memory controller

stm32 f4 series -...

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