stick diagrams and tutorial
TRANSCRIPT
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Stick Diagrams
by
Rita JainProfessor and Head
Department of Electronics and Communication EngineeringLakshmi Narain College of Technology, Bhopal
Stick Diagrams
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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Stick Diagrams
Layout
The Design Rules describe: Minimum width to avoid breaks in a lineMinimum spacing to avoid shorts between linesMinimum overlap to ensure two layers completely overlap
Unit TransistorTransistor dimensions are specified by their W/L ratioFor 0.6 μm process, W = 1.2 μm and L = 0.6 μm Such a minimum width contacted transistor is called UNIT TRANSISTOR
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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Stick Diagrams
Inverter Layout
Transistor dimensions specified as Width / Length• Minimum size is 4λ / 2λ, sometimes called 1 unit• For 0.6 mm process, W=1.2 μm, L=0.6 μm
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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Stick Diagrams
LayoutA conservative but easy to use Design Rules for n-
well process is as follows: Metal and diffusion have minimum width spacing of 4λContacts are 2λ X 2λ and must be surrounded by 1λon the layers above and belowPolysilicon uses a width of 2λPolysilicon overlaps diffusion by 2λ where a transistor is desired and has a spacing of 1λ away where no transistor is desiredPolysilicon and contacts have a spacing of 3λ from other polysilicon or contactsN-well surrounds PMOS transistors by 6λ and avoids NMOS transistors by 6λ
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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Stick Diagrams
Simplified Design Rules
Conservative rules to get you started
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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Stick Diagrams
Stick Diagrams
Stick diagrams help plan layout quickly• Need not be to scale• Draw with color pencils or dry-erase markers
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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Stick Diagrams
VLSI design aims to translate circuit concepts onto silicon.stick diagrams are a means of capturing topography and layer information using simple diagrams.Stick diagrams convey layer information through colour codes (or monochrome encoding).Acts as an interface between symbolic circuit and the actual layout.
Stick Diagrams
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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Stick Diagrams
Does show all components/vias.It shows relative placement of components.Goes one step closer to the layoutHelps plan the layout and routing
Stick Diagrams
Does not show• Exact placement of components• Transistor sizes• Wire lengths, wire widths, tub boundaries.• Any other low level details such as parasitics.
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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Stick Diagrams
Wiring Tracks
A wiring track is the space required for a wire• 4λ width, 4 λ spacing from neighbor = 8λ pitch
Transistors also consume one wiring track
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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Stick Diagrams
Well Spacing
Wells must surround transistors by 6λ• Implies 12λ between opposite transistor flavors• Leaves room for one wire track
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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Stick Diagrams
Area Estimation
Estimate area by counting wiring tracks• Multiply by 8 to express in λ
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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Stick Diagrams
Example: Inverter
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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Stick Diagrams
Example: NAND3
Horizontal N-diffusion and p-diffusion stripsVertical polysilicon gatesMetal1 VDD rail at topMetal1 GND rail at bottom32 l by 40 l
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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Stick Diagrams – Some rulesRule 1.
When two or more ‘sticks’ of the same type cross or touch each other that represents electrical contact.
Stick Diagrams
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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Stick Diagrams – Some rulesRule 2.
When two or more ‘sticks’ of different type cross or touch each other there is no electrical contact. (If electrical contact is needed we have to show the connection
explicitly).
Stick Diagrams
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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Stick Diagrams – Some rulesRule 3.
When a poly crosses diffusion it represents a transistor.
Note: If a contact is shown then it is not a transistor.
Stick Diagrams
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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Stick Diagrams – Some rulesRule 4.
In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff. All pMOS must lie on one side of the line and all nMOS will have to be on the other side.
Stick Diagrams
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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Stick Diagrams
N+ N+
Stick Diagrams
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Stick Diagrams
Gnd
VDD
x x
X
X
X
X
VDD
x x
Gnd
Stick Diagram
Stick Diagrams
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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Stick Diagrams
Gnd
VDD
x x
X
X
X
X
VDD
x x
Gnd
Stick Diagrams
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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Stick Diagrams – Notations
Metal 1
poly
ndiff
pdiffCan also drawin shades of
gray/line style.
Stick Diagrams
Similarly for contacts, via, tub etc..
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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How to draw Stick DiagramsStick Diagrams
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NOR GateStick Diagrams
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Stacked Layout
Power
Ground
B
C
OutA
Stick Diagrams
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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Methods for generating Stick Diagrams
Construct a Logic Graph of the SchematicsIdentify each transistor by a unique name of its gate signal (A, B, C, D …..)Identify each connection to the transistor by a unique name (1,2,3,4,5,…..)Construct an Euler Path for both pull-up and pull-down networkEuler Path is defined by a path that traverses each node in the path, such that each edge is visited only oncePath is defined by the order of each transistor nameEuler Path for the pull-up network must be same as the path of pull-down networkEuler paths are not necessarily uniqueIt may be necessary to redefined the function to find a Euler path
Stick Diagrams
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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Methods for generating Stick DiagramsOnce the Euler path is found it is time to layout the stick
diagramTrace two lines horizontally to represent PMOS and NMOSTrace the number of Inputs vertically across each strip. These represent the gate contacts to the devices that are made of polySurround NMOS and PMOS by P-well and N-wellTrace a blue line horizontally above and below the PMOS and NMOS lines to represent the metal of VDD and VSSLabel each poly line with the Euler path label, in order from left to rightPlace the connection label upon NMOS and PMOS devices
Stick Diagrams
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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Stick DiagramsStick Diagrams
Sketch a stick diagram for O3AI and estimate area• Y = ((A+B+C).D)’
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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Stick DiagramsStick Diagrams
VSS
VDD
A
A
B
B C
C
D
DY
B
VDD
A
C
D
Y
VDD
Pull-up Network
BA C
D
Y
VSS
Pull-down Network
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Stick DiagramsStick Diagrams
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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Area EstimationStick Diagrams
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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Stick Diagrams
OAI21 Logic Graph
C
A B
X = !(C • (A + B))
B
AC
i
j
X
X
i
GND
C
j
VDD
A
B
PUNPDNABC
AB
C
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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Home Work
1. Draw the stick diagram for two input CMOS NAND gate.2. Draw the stick diagram for two input NAND gate using NMOS
Logic.3. Draw the stick diagram for 2:1 MUX using
a) Pass transistorsb) Transmission gates.
4. Draw Stick Diagrams for the following equations :
5. For a process technology with L = 5 micron meter give the size of the layout for the following : (a) 4-input NOR gate and 4-Input NAND gate
6. Draw Stick Diagram for the circuits given below and estimate its area (circuits given in next few slides)
7. Identify the logic functions (stick diagrams given in next few slides)
Drawing stick diagram is truly Fun !!! Enjoy it !!!
Stick Diagrams
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
DCBAY ).( ++=DCBAY ).( ++=
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Draw Stick Diagram for the circuit given below and estimate its area
Stick Diagrams
OUT = !(D + A • (B + C))
DA
B C
D
AB
C
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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Stick Diagrams
Draw Stick Diagram for the circuits given below and estimate itsarea
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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Stick Diagrams
C
A B
X = !((A+B)•(C+D))
B
A
D
C
D
ABCD
Draw Stick Diagram for the circuits given below and estimate its area
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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Stick Diagrams
What logic function is this?
signals
Routingchannel
VDD
GND
What logic function is this?
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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Stick Diagrams
A B C
X
VDD
GND
X
CA B
VDD
GND
What logic function is this?
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
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Stick Diagrams
BA D
VDD
GND
C
X
What logic function is this?
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal