stellaris lm3s9d92 microcontroller data sheet (rev. c)

Stellaris LM3S9D92 Microcontroller

DATA SHEET

Copyr ight 2007-2014Texas Instruments Incorporated

DS-LM3S9D92-15852 .2743SPMS257C

TEXAS INSTRUMENTS-PRODUCTION DATA

CopyrightCopyright 2007-2014 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas InstrumentsIncorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as theproperty of others.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standardwarranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductorproducts and disclaimers thereto appears at the end of this data sheet.

Texas Instruments Incorporated108 Wild Basin, Suite 350Austin, TX 78746http://www.ti.com/stellarishttp://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

July 03, 20142Texas Instruments-Production Data

http://www.ti.com/stellarishttp://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

Table of ContentsRevision History ............................................................................................................................. 42About This Document .................................................................................................................... 45Audience .............................................................................................................................................. 45About This Manual ................................................................................................................................ 45Related Documents ............................................................................................................................... 45Documentation Conventions .................................................................................................................. 46

1 Architectural Overview .......................................................................................... 481.1 Overview ...................................................................................................................... 481.2 Target Applications ........................................................................................................ 501.3 Features ....................................................................................................................... 501.3.1 ARM Cortex-M3 Processor Core .................................................................................... 501.3.2 On-Chip Memory ........................................................................................................... 521.3.3 External Peripheral Interface ......................................................................................... 531.3.4 Serial Communications Peripherals ................................................................................ 551.3.5 System Integration ........................................................................................................ 611.3.6 Advanced Motion Control ............................................................................................... 661.3.7 Analog .......................................................................................................................... 681.3.8 JTAG and ARM Serial Wire Debug ................................................................................ 691.3.9 Packaging and Temperature .......................................................................................... 701.4 Hardware Details .......................................................................................................... 70

2 The Cortex-M3 Processor ...................................................................................... 712.1 Block Diagram .............................................................................................................. 722.2 Overview ...................................................................................................................... 732.2.1 System-Level Interface .................................................................................................. 732.2.2 Integrated Configurable Debug ...................................................................................... 732.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 742.2.4 Cortex-M3 System Component Details ........................................................................... 742.3 Programming Model ...................................................................................................... 752.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 752.3.2 Stacks .......................................................................................................................... 752.3.3 Register Map ................................................................................................................ 762.3.4 Register Descriptions .................................................................................................... 772.3.5 Exceptions and Interrupts .............................................................................................. 902.3.6 Data Types ................................................................................................................... 902.4 Memory Model .............................................................................................................. 902.4.1 Memory Regions, Types and Attributes ........................................................................... 922.4.2 Memory System Ordering of Memory Accesses .............................................................. 932.4.3 Behavior of Memory Accesses ....................................................................................... 932.4.4 Software Ordering of Memory Accesses ......................................................................... 942.4.5 Bit-Banding ................................................................................................................... 952.4.6 Data Storage ................................................................................................................ 972.4.7 Synchronization Primitives ............................................................................................. 982.5 Exception Model ........................................................................................................... 992.5.1 Exception States ......................................................................................................... 1002.5.2 Exception Types .......................................................................................................... 100

3July 03, 2014Texas Instruments-Production Data


2.5.3 Exception Handlers ..................................................................................................... 1032.5.4 Vector Table ................................................................................................................ 1032.5.5 Exception Priorities ...................................................................................................... 1042.5.6 Interrupt Priority Grouping ............................................................................................ 1052.5.7 Exception Entry and Return ......................................................................................... 1052.6 Fault Handling ............................................................................................................. 1072.6.1 Fault Types ................................................................................................................. 1082.6.2 Fault Escalation and Hard Faults .................................................................................. 1082.6.3 Fault Status Registers and Fault Address Registers ...................................................... 1092.6.4 Lockup ....................................................................................................................... 1092.7 Power Management .................................................................................................... 1092.7.1 Entering Sleep Modes ................................................................................................. 1102.7.2 Wake Up from Sleep Mode .......................................................................................... 1102.8 Instruction Set Summary .............................................................................................. 111

3 Cortex-M3 Peripherals ......................................................................................... 1143.1 Functional Description ................................................................................................. 1143.1.1 System Timer (SysTick) ............................................................................................... 1143.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................. 1153.1.3 System Control Block (SCB) ........................................................................................ 1173.1.4 Memory Protection Unit (MPU) ..................................................................................... 1173.2 Register Map .............................................................................................................. 1223.3 System Timer (SysTick) Register Descriptions .............................................................. 1243.4 NVIC Register Descriptions .......................................................................................... 1283.5 System Control Block (SCB) Register Descriptions ........................................................ 1413.6 Memory Protection Unit (MPU) Register Descriptions .................................................... 170

4 JTAG Interface ...................................................................................................... 1804.1 Block Diagram ............................................................................................................ 1814.2 Signal Description ....................................................................................................... 1814.3 Functional Description ................................................................................................. 1824.3.1 JTAG Interface Pins ..................................................................................................... 1824.3.2 JTAG TAP Controller ................................................................................................... 1844.3.3 Shift Registers ............................................................................................................ 1844.3.4 Operational Considerations .......................................................................................... 1854.4 Initialization and Configuration ..................................................................................... 1874.5 Register Descriptions .................................................................................................. 1884.5.1 Instruction Register (IR) ............................................................................................... 1884.5.2 Data Registers ............................................................................................................ 190

5 System Control ..................................................................................................... 1925.1 Signal Description ....................................................................................................... 1925.2 Functional Description ................................................................................................. 1925.2.1 Device Identification .................................................................................................... 1935.2.2 Reset Control .............................................................................................................. 1935.2.3 Non-Maskable Interrupt ............................................................................................... 1985.2.4 Power Control ............................................................................................................. 1985.2.5 Clock Control .............................................................................................................. 1995.2.6 System Control ........................................................................................................... 2055.3 Initialization and Configuration ..................................................................................... 2075.4 Register Map .............................................................................................................. 207


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5.5 Register Descriptions .................................................................................................. 209

6 Internal Memory ................................................................................................... 3006.1 Block Diagram ............................................................................................................ 3006.2 Functional Description ................................................................................................. 3006.2.1 SRAM ........................................................................................................................ 3016.2.2 ROM .......................................................................................................................... 3016.2.3 Flash Memory ............................................................................................................. 3036.3 Register Map .............................................................................................................. 3086.4 Flash Memory Register Descriptions (Flash Control Offset) ............................................ 3106.5 Memory Register Descriptions (System Control Offset) .................................................. 322

7 Micro Direct Memory Access (DMA) ................................................................ 3467.1 Block Diagram ............................................................................................................ 3477.2 Functional Description ................................................................................................. 3477.2.1 Channel Assignments .................................................................................................. 3487.2.2 Priority ........................................................................................................................ 3497.2.3 Arbitration Size ............................................................................................................ 3497.2.4 Request Types ............................................................................................................ 3507.2.5 Channel Configuration ................................................................................................. 3517.2.6 Transfer Modes ........................................................................................................... 3527.2.7 Transfer Size and Increment ........................................................................................ 3617.2.8 Peripheral Interface ..................................................................................................... 3617.2.9 Software Request ........................................................................................................ 3617.2.10 Interrupts and Errors .................................................................................................... 3627.3 Initialization and Configuration ..................................................................................... 3627.3.1 Module Initialization ..................................................................................................... 3627.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 3637.3.3 Configuring a Peripheral for Simple Transmit ................................................................ 3647.3.4 Configuring a Peripheral for Ping-Pong Receive ............................................................ 3667.3.5 Configuring Channel Assignments ................................................................................ 3687.4 Register Map .............................................................................................................. 3687.5 DMA Channel Control Structure ................................................................................. 3707.6 DMA Register Descriptions ........................................................................................ 377

8 General-Purpose Input/Outputs (GPIOs) ........................................................... 4078.1 Signal Description ....................................................................................................... 4078.2 Functional Description ................................................................................................. 4128.2.1 Data Control ............................................................................................................... 4138.2.2 Interrupt Control .......................................................................................................... 4148.2.3 Mode Control .............................................................................................................. 4158.2.4 Commit Control ........................................................................................................... 4158.2.5 Pad Control ................................................................................................................. 4168.2.6 Identification ............................................................................................................... 4168.3 Initialization and Configuration ..................................................................................... 4168.4 Register Map .............................................................................................................. 4178.5 Register Descriptions .................................................................................................. 419

9 External Peripheral Interface (EPI) ..................................................................... 4629.1 EPI Block Diagram ...................................................................................................... 4639.2 Signal Description ....................................................................................................... 464



9.3 Functional Description ................................................................................................. 4669.3.1 Non-Blocking Reads .................................................................................................... 4679.3.2 DMA Operation ........................................................................................................... 4689.4 Initialization and Configuration ..................................................................................... 4689.4.1 SDRAM Mode ............................................................................................................. 4699.4.2 Host Bus Mode ........................................................................................................... 4739.4.3 General-Purpose Mode ............................................................................................... 4849.5 Register Map .............................................................................................................. 4929.6 Register Descriptions .................................................................................................. 493

10 General-Purpose Timers ...................................................................................... 53710.1 Block Diagram ............................................................................................................ 53810.2 Signal Description ....................................................................................................... 53810.3 Functional Description ................................................................................................. 54110.3.1 GPTM Reset Conditions .............................................................................................. 54210.3.2 Timer Modes ............................................................................................................... 54210.3.3 DMA Operation ........................................................................................................... 54810.3.4 Accessing Concatenated Register Values ..................................................................... 54910.4 Initialization and Configuration ..................................................................................... 54910.4.1 One-Shot/Periodic Timer Mode .................................................................................... 54910.4.2 Real-Time Clock (RTC) Mode ...................................................................................... 55010.4.3 Input Edge-Count Mode ............................................................................................... 55010.4.4 Input Edge Timing Mode .............................................................................................. 55110.4.5 PWM Mode ................................................................................................................. 55210.5 Register Map .............................................................................................................. 55210.6 Register Descriptions .................................................................................................. 553

11 Watchdog Timers ................................................................................................. 58411.1 Block Diagram ............................................................................................................ 58511.2 Functional Description ................................................................................................. 58511.2.1 Register Access Timing ............................................................................................... 58611.3 Initialization and Configuration ..................................................................................... 58611.4 Register Map .............................................................................................................. 58611.5 Register Descriptions .................................................................................................. 587

12 Analog-to-Digital Converter (ADC) ..................................................................... 60912.1 Block Diagram ............................................................................................................ 61012.2 Signal Description ....................................................................................................... 61112.3 Functional Description ................................................................................................. 61312.3.1 Sample Sequencers .................................................................................................... 61312.3.2 Module Control ............................................................................................................ 61412.3.3 Hardware Sample Averaging Circuit ............................................................................. 61612.3.4 Analog-to-Digital Converter .......................................................................................... 61712.3.5 Differential Sampling ................................................................................................... 62112.3.6 Internal Temperature Sensor ........................................................................................ 62312.3.7 Digital Comparator Unit ............................................................................................... 62412.4 Initialization and Configuration ..................................................................................... 62812.4.1 Module Initialization ..................................................................................................... 62812.4.2 Sample Sequencer Configuration ................................................................................. 62912.5 Register Map .............................................................................................................. 62912.6 Register Descriptions .................................................................................................. 631


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13 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 69013.1 Block Diagram ............................................................................................................ 69113.2 Signal Description ....................................................................................................... 69113.3 Functional Description ................................................................................................. 69313.3.1 Transmit/Receive Logic ............................................................................................... 69413.3.2 Baud-Rate Generation ................................................................................................. 69413.3.3 Data Transmission ...................................................................................................... 69513.3.4 Serial IR (SIR) ............................................................................................................. 69513.3.5 ISO 7816 Support ....................................................................................................... 69613.3.6 Modem Handshake Support ......................................................................................... 69713.3.7 LIN Support ................................................................................................................ 69813.3.8 FIFO Operation ........................................................................................................... 69913.3.9 Interrupts .................................................................................................................... 70013.3.10 Loopback Operation .................................................................................................... 70113.3.11 DMA Operation ........................................................................................................... 70113.4 Initialization and Configuration ..................................................................................... 70113.5 Register Map .............................................................................................................. 70213.6 Register Descriptions .................................................................................................. 704

14 Synchronous Serial Interface (SSI) .................................................................... 75414.1 Block Diagram ............................................................................................................ 75514.2 Signal Description ....................................................................................................... 75514.3 Functional Description ................................................................................................. 75614.3.1 Bit Rate Generation ..................................................................................................... 75714.3.2 FIFO Operation ........................................................................................................... 75714.3.3 Interrupts .................................................................................................................... 75714.3.4 Frame Formats ........................................................................................................... 75814.3.5 DMA Operation ........................................................................................................... 76514.4 Initialization and Configuration ..................................................................................... 76614.5 Register Map .............................................................................................................. 76714.6 Register Descriptions .................................................................................................. 768

15 Inter-Integrated Circuit (I2C) Interface ................................................................ 79615.1 Block Diagram ............................................................................................................ 79715.2 Signal Description ....................................................................................................... 79715.3 Functional Description ................................................................................................. 79815.3.1 I2C Bus Functional Overview ........................................................................................ 79815.3.2 Available Speed Modes ............................................................................................... 80015.3.3 Interrupts .................................................................................................................... 80115.3.4 Loopback Operation .................................................................................................... 80215.3.5 Command Sequence Flow Charts ................................................................................ 80315.4 Initialization and Configuration ..................................................................................... 81015.5 Register Map .............................................................................................................. 81115.6 Register Descriptions (I2C Master) ............................................................................... 81215.7 Register Descriptions (I2C Slave) ................................................................................. 825

16 Inter-Integrated Circuit Sound (I2S) Interface .................................................... 83416.1 Block Diagram ............................................................................................................ 83516.2 Signal Description ....................................................................................................... 83516.3 Functional Description ................................................................................................. 836



16.3.1 Transmit ..................................................................................................................... 83816.3.2 Receive ...................................................................................................................... 84216.4 Initialization and Configuration ..................................................................................... 84416.5 Register Map .............................................................................................................. 84516.6 Register Descriptions .................................................................................................. 846

17 Controller Area Network (CAN) Module ............................................................. 87117.1 Block Diagram ............................................................................................................ 87217.2 Signal Description ....................................................................................................... 87217.3 Functional Description ................................................................................................. 87317.3.1 Initialization ................................................................................................................. 87417.3.2 Operation ................................................................................................................... 87517.3.3 Transmitting Message Objects ..................................................................................... 87617.3.4 Configuring a Transmit Message Object ........................................................................ 87617.3.5 Updating a Transmit Message Object ........................................................................... 87717.3.6 Accepting Received Message Objects .......................................................................... 87817.3.7 Receiving a Data Frame .............................................................................................. 87817.3.8 Receiving a Remote Frame .......................................................................................... 87817.3.9 Receive/Transmit Priority ............................................................................................. 87917.3.10 Configuring a Receive Message Object ........................................................................ 87917.3.11 Handling of Received Message Objects ........................................................................ 88017.3.12 Handling of Interrupts .................................................................................................. 88217.3.13 Test Mode ................................................................................................................... 88317.3.14 Bit Timing Configuration Error Considerations ............................................................... 88517.3.15 Bit Time and Bit Rate ................................................................................................... 88517.3.16 Calculating the Bit Timing Parameters .......................................................................... 88717.4 Register Map .............................................................................................................. 89017.5 CAN Register Descriptions .......................................................................................... 891

18 Ethernet Controller .............................................................................................. 92218.1 Block Diagram ............................................................................................................ 92318.2 Signal Description ....................................................................................................... 92418.3 Functional Description ................................................................................................. 92518.3.1 MAC Operation ........................................................................................................... 92518.3.2 Internal MII Operation .................................................................................................. 92918.3.3 PHY Operation ............................................................................................................ 92918.3.4 Interrupts .................................................................................................................... 93118.3.5 DMA Operation ........................................................................................................... 93218.4 Initialization and Configuration ..................................................................................... 93218.4.1 Hardware Configuration ............................................................................................... 93218.4.2 Software Configuration ................................................................................................ 93318.5 Register Map .............................................................................................................. 93418.6 Ethernet MAC Register Descriptions ............................................................................. 93618.7 MII Management Register Descriptions ......................................................................... 962

19 Universal Serial Bus (USB) Controller ............................................................... 98319.1 Block Diagram ............................................................................................................ 98419.2 Signal Description ....................................................................................................... 98419.3 Functional Description ................................................................................................. 98619.3.1 Operation as a Device ................................................................................................. 98619.3.2 Operation as a Host .................................................................................................... 991


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19.3.3 OTG Mode .................................................................................................................. 99519.3.4 DMA Operation ........................................................................................................... 99719.4 Initialization and Configuration ..................................................................................... 99819.4.1 Pin Configuration ......................................................................................................... 99819.4.2 Endpoint Configuration ................................................................................................ 99919.5 Register Map .............................................................................................................. 99919.6 Register Descriptions ................................................................................................. 1010

20 Analog Comparators .......................................................................................... 112220.1 Block Diagram ........................................................................................................... 112320.2 Signal Description ..................................................................................................... 112320.3 Functional Description ............................................................................................... 112420.3.1 Internal Reference Programming ................................................................................ 112520.4 Initialization and Configuration .................................................................................... 112620.5 Register Map ............................................................................................................ 112720.6 Register Descriptions ................................................................................................. 1128

21 Pulse Width Modulator (PWM) .......................................................................... 113621.1 Block Diagram ........................................................................................................... 113721.2 Signal Description ..................................................................................................... 113821.3 Functional Description ............................................................................................... 114121.3.1 PWM Timer ............................................................................................................... 114121.3.2 PWM Comparators .................................................................................................... 114121.3.3 PWM Signal Generator .............................................................................................. 114321.3.4 Dead-Band Generator ............................................................................................... 114321.3.5 Interrupt/ADC-Trigger Selector ................................................................................... 114421.3.6 Synchronization Methods .......................................................................................... 114421.3.7 Fault Conditions ........................................................................................................ 114521.3.8 Output Control Block .................................................................................................. 114621.4 Initialization and Configuration .................................................................................... 114621.5 Register Map ............................................................................................................ 114721.6 Register Descriptions ................................................................................................. 1150

22 Quadrature Encoder Interface (QEI) ................................................................. 121322.1 Block Diagram ........................................................................................................... 121322.2 Signal Description ..................................................................................................... 121422.3 Functional Description ............................................................................................... 121522.4 Initialization and Configuration .................................................................................... 121722.5 Register Map ............................................................................................................ 121822.6 Register Descriptions ................................................................................................. 1219

23 Pin Diagram ........................................................................................................ 123624 Signal Tables ...................................................................................................... 123824.1 100-Pin LQFP Package Pin Tables ............................................................................. 123924.1.1 Signals by Pin Number .............................................................................................. 123924.1.2 Signals by Signal Name ............................................................................................. 125124.1.3 Signals by Function, Except for GPIO ......................................................................... 126124.1.4 GPIO Pins and Alternate Functions ............................................................................ 127024.1.5 Possible Pin Assignments for Alternate Functions ....................................................... 127324.2 108-Ball BGA Package Pin Tables .............................................................................. 127624.2.1 Signals by Pin Number .............................................................................................. 1276



24.2.2 Signals by Signal Name ............................................................................................. 128824.2.3 Signals by Function, Except for GPIO ......................................................................... 129924.2.4 GPIO Pins and Alternate Functions ............................................................................ 130824.2.5 Possible Pin Assignments for Alternate Functions ....................................................... 131124.3 Connections for Unused Signals ................................................................................. 1314

25 Operating Characteristics ................................................................................. 131626 Electrical Characteristics .................................................................................. 131726.1 Maximum Ratings ...................................................................................................... 131726.2 Recommended Operating Conditions ......................................................................... 131726.3 Load Conditions ........................................................................................................ 131826.4 JTAG and Boundary Scan .......................................................................................... 131826.5 Power and Brown-Out ............................................................................................... 132026.6 Reset ........................................................................................................................ 132126.7 On-Chip Low Drop-Out (LDO) Regulator ..................................................................... 132226.8 Clocks ...................................................................................................................... 132226.8.1 PLL Specifications ..................................................................................................... 132226.8.2 PIOSC Specifications ................................................................................................ 132326.8.3 Internal 30-kHz Oscillator Specifications ..................................................................... 132326.8.4 Main Oscillator Specifications ..................................................................................... 132426.8.5 System Clock Specification with ADC Operation .......................................................... 132526.8.6 System Clock Specification with USB Operation .......................................................... 132526.9 Sleep Modes ............................................................................................................. 132526.10 Flash Memory ........................................................................................................... 132526.11 Input/Output Characteristics ....................................................................................... 132626.12 External Peripheral Interface (EPI) .............................................................................. 132626.13 Analog-to-Digital Converter (ADC) .............................................................................. 133226.14 Synchronous Serial Interface (SSI) ............................................................................. 133326.15 Inter-Integrated Circuit (I2C) Interface ......................................................................... 133526.16 Inter-Integrated Circuit Sound (I2S) Interface ............................................................... 133626.17 Ethernet Controller .................................................................................................... 133726.18 Universal Serial Bus (USB) Controller ......................................................................... 134026.19 Analog Comparator ................................................................................................... 134026.20 Current Consumption ................................................................................................. 134126.20.1 Nominal Power Consumption ..................................................................................... 134126.20.2 Maximum Current Consumption ................................................................................. 1341

A Register Quick Reference ................................................................................. 1343B Ordering and Contact Information ................................................................... 1399B.1 Ordering Information .................................................................................................. 1399B.2 Part Markings ............................................................................................................ 1399B.3 Kits ........................................................................................................................... 1399B.4 Support Information ................................................................................................... 1400

C Package Information .......................................................................................... 1401C.1 100-Pin LQFP Package ............................................................................................. 1401C.1.1 Package Dimensions ................................................................................................. 1401C.1.2 Tray Dimensions ....................................................................................................... 1403C.1.3 Tape and Reel Dimensions ........................................................................................ 1403C.2 108-Ball BGA Package .............................................................................................. 1405


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C.2.1 Package Dimensions ................................................................................................. 1405C.2.2 Tray Dimensions ....................................................................................................... 1407C.2.3 Tape and Reel Dimensions ........................................................................................ 1408



List of FiguresFigure 1-1. Stellaris LM3S9D92 Microcontroller High-Level Block Diagram ............................... 49Figure 2-1. CPU Block Diagram ............................................................................................. 73Figure 2-2. TPIU Block Diagram ............................................................................................ 74Figure 2-3. Cortex-M3 Register Set ........................................................................................ 76Figure 2-4. Bit-Band Mapping ................................................................................................ 97Figure 2-5. Data Storage ....................................................................................................... 98Figure 2-6. Vector Table ...................................................................................................... 104Figure 2-7. Exception Stack Frame ...................................................................................... 106Figure 3-1. SRD Use Example ............................................................................................. 120Figure 4-1. JTAG Module Block Diagram .............................................................................. 181Figure 4-2. Test Access Port State Machine ......................................................................... 184Figure 4-3. IDCODE Register Format ................................................................................... 190Figure 4-4. BYPASS Register Format ................................................................................... 191Figure 4-5. Boundary Scan Register Format ......................................................................... 191Figure 5-1. Basic RST Configuration .................................................................................... 195Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 195Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 196Figure 5-4. Power Architecture ............................................................................................ 199Figure 5-5. Main Clock Tree ................................................................................................ 201Figure 6-1. Internal Memory Block Diagram .......................................................................... 300Figure 7-1. DMA Block Diagram ......................................................................................... 347Figure 7-2. Example of Ping-Pong DMA Transaction ........................................................... 354Figure 7-3. Memory Scatter-Gather, Setup and Configuration ................................................ 356Figure 7-4. Memory Scatter-Gather, DMA Copy Sequence .................................................. 357Figure 7-5. Peripheral Scatter-Gather, Setup and Configuration ............................................. 359Figure 7-6. Peripheral Scatter-Gather, DMA Copy Sequence ............................................... 360Figure 8-1. Digital I/O Pads ................................................................................................. 412Figure 8-2. Analog/Digital I/O Pads ...................................................................................... 413Figure 8-3. GPIODATA Write Example ................................................................................. 414Figure 8-4. GPIODATA Read Example ................................................................................. 414Figure 9-1. EPI Block Diagram ............................................................................................. 464Figure 9-2. SDRAM Non-Blocking Read Cycle ...................................................................... 472Figure 9-3. SDRAM Normal Read Cycle ............................................................................... 472Figure 9-4. SDRAM Write Cycle ........................................................................................... 473Figure 9-5. Example Schematic for Muxed Host-Bus 16 Mode ............................................... 479Figure 9-6. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 481Figure 9-7. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 482Figure 9-8. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH

= 0, RDHIGH = 0 ............................................................................................... 482Figure 9-9. Host-Bus Write Cycle with Multiplexed Address and Data and ALE with Dual

CSn .................................................................................................................. 483Figure 9-10. Continuous Read Mode Accesses ...................................................................... 483Figure 9-11. Write Followed by Read to External FIFO ............................................................ 484Figure 9-12. Two-Entry FIFO ................................................................................................. 484Figure 9-13. Single-Cycle Write Access, FRM50=0, FRMCNT=0, WRCYC=0 ........................... 488


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Figure 9-14. Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, RDCYC=1,WRCYC=1 ........................................................................................................ 488

Figure 9-15. Read Accesses, FRM50=0, FRMCNT=0, RDCYC=1 ............................................ 489Figure 9-16. FRAME Signal Operation, FRM50=0 and FRMCNT=0 ......................................... 489Figure 9-17. FRAME Signal Operation, FRM50=0 and FRMCNT=1 ......................................... 489Figure 9-18. FRAME Signal Operation, FRM50=0 and FRMCNT=2 ......................................... 490Figure 9-19. FRAME Signal Operation, FRM50=1 and FRMCNT=0 ......................................... 490Figure 9-20. FRAME Signal Operation, FRM50=1 and FRMCNT=1 ......................................... 490Figure 9-21. FRAME Signal Operation, FRM50=1 and FRMCNT=2 ......................................... 490Figure 9-22. iRDY Signal Operation, FRM50=0, FRMCNT=0, and RD2CYC=1 ......................... 491Figure 9-23. EPI Clock Operation, CLKGATE=1, WR2CYC=0 ................................................. 492Figure 9-24. EPI Clock Operation, CLKGATE=1, WR2CYC=1 ................................................. 492Figure 10-1. GPTM Module Block Diagram ............................................................................ 538Figure 10-2. Timer Daisy Chain ............................................................................................. 544Figure 10-3. Input Edge-Count Mode Example ....................................................................... 546Figure 10-4. 16-Bit Input Edge-Time Mode Example ............................................................... 547Figure 10-5. 16-Bit PWM Mode Example ................................................................................ 548Figure 11-1. WDT Module Block Diagram .............................................................................. 585Figure 12-1. Implementation of Two ADC Blocks .................................................................... 610Figure 12-2. ADC Module Block Diagram ............................................................................... 611Figure 12-3. ADC Sample Phases ......................................................................................... 615Figure 12-4. Doubling the ADC Sample Rate .......................................................................... 616Figure 12-5. Skewed Sampling .............................................................................................. 616Figure 12-6. Sample Averaging Example ............................................................................... 617Figure 12-7. ADC Input Equivalency Diagram ......................................................................... 618Figure 12-8. Internal Voltage Conversion Result ..................................................................... 619Figure 12-9. External Voltage Conversion Result with 3.0-V Setting ......................................... 620Figure 12-10. External Voltage Conversion Result with 1.0-V Setting ......................................... 620Figure 12-11. Differential Sampling Range, VIN_ODD = 1.5 V ...................................................... 622Figure 12-12. Differential Sampling Range, VIN_ODD = 0.75 V .................................................... 622Figure 12-13. Differential Sampling Range, VIN_ODD = 2.25 V .................................................... 623Figure 12-14. Internal Temperature Sensor Characteristic ......................................................... 624Figure 12-15. Low-Band Operation (CIC=0x0 and/or CTC=0x0) ................................................ 626Figure 12-16. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ................................................. 627Figure 12-17. High-Band Operation (CIC=0x3 and/or CTC=0x3) ................................................ 628Figure 13-1. UART Module Block Diagram ............................................................................. 691Figure 13-2. UART Character Frame ..................................................................................... 694Figure 13-3. IrDA Data Modulation ......................................................................................... 696Figure 13-4. LIN Message ..................................................................................................... 698Figure 13-5. LIN Synchronization Field ................................................................................... 699Figure 14-1. SSI Module Block Diagram ................................................................................. 755Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 759Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 759Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 760Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 760Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 761Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 762Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 762



Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 763Figure 14-10. MICROWIRE Frame Format (Single Frame) ........................................................ 764Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 765Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 765Figure 15-1. I2C Block Diagram ............................................................................................. 797Figure 15-2. I2C Bus Configuration ........................................................................................ 798Figure 15-3. START and STOP Conditions ............................................................................. 799Figure 15-4. Complete Data Transfer with a 7-Bit Address ....................................................... 799Figure 15-5. R/S Bit in First Byte ............................................................................................ 800Figure 15-6. Data Validity During Bit Transfer on the I2C Bus ................................................... 800Figure 15-7. Master Single TRANSMIT .................................................................................. 804Figure 15-8. Master Single RECEIVE ..................................................................................... 805Figure 15-9. Master TRANSMIT with Repeated START ........................................................... 806Figure 15-10. Master RECEIVE with Repeated START ............................................................. 807Figure 15-11. Master RECEIVE with Repeated START after TRANSMIT with Repeated

START .............................................................................................................. 808Figure 15-12. Master TRANSMIT with Repeated START after RECEIVE with Repeated

START .............................................................................................................. 809Figure 15-13. Slave Command Sequence ................................................................................ 810Figure 16-1. I2S Block Diagram ............................................................................................. 835Figure 16-2. I2S Data Transfer ............................................................................................... 838Figure 16-3. Left-Justified Data Transfer ................................................................................ 838Figure 16-4. Right-Justified Data Transfer .............................................................................. 838Figure 17-1. CAN Controller Block Diagram ............................................................................ 872Figure 17-2. CAN Data/Remote Frame .................................................................................. 874Figure 17-3. Message Objects in a FIFO Buffer ...................................................................... 882Figure 17-4. CAN Bit Time .................................................................................................... 886Figure 18-1. Ethernet Controller ............................................................................................. 923Figure 18-2. Ethernet Controller Block Diagram ...................................................................... 923Figure 18-3. Ethernet Frame ................................................................................................. 925Figure 18-4. Interface to an Ethernet Jack .............................................................................. 933Figure 19-1. USB Module Block Diagram ............................................................................... 984Figure 20-1. Analog Comparator Module Block Diagram ....................................................... 1123Figure 20-2. Structure of Comparator Unit ............................................................................ 1125Figure 20-3. Comparator Internal Reference Structure .......................................................... 1125Figure 21-1. PWM Module Diagram ..................................................................................... 1138Figure 21-2. PWM Generator Block Diagram ........................................................................ 1138Figure 21-3. PWM Count-Down Mode .................................................................................. 1142Figure 21-4. PWM Count-Up/Down Mode ............................................................................. 1142Figure 21-5. PWM Generation Example In Count-Up/Down Mode .......................................... 1143Figure 21-6. PWM Dead-Band Generator ............................................................................. 1144Figure 22-1. QEI Block Diagram .......................................................................................... 1214Figure 22-2. Quadrature Encoder and Velocity Predivider Operation ...................................... 1216Figure 23-1. 100-Pin LQFP Package Pin Diagram ................................................................ 1236Figure 23-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................. 1237Figure 26-1. Load Conditions ............................................................................................... 1318Figure 26-2. JTAG Test Clock Input Timing ........................................................................... 1319Figure 26-3. JTAG Test Access Port (TAP) Timing ................................................................ 1319


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Figure 26-4. Power-On Reset Timing ................................................................................... 1320Figure 26-5. Brown-Out Reset Timing .................................................................................. 1320Figure 26-6. Power-On Reset and Voltage Parameters ......................................................... 1321Figure 26-7. External Reset Timing (RST) ............................................................................ 1321Figure 26-8. Software Reset Timing ..................................................................................... 1321Figure 26-9. Watchdog Reset Timing ................................................................................... 1322Figure 26-10. MOSC Failure Reset Timing ............................................................................. 1322Figure 26-11. SDRAM Initialization and Load Mode Register Timing ........................................ 1327Figure 26-12. SDRAM Read Timing ....................................................................................... 1327Figure 26-13. SDRAM Write Timing ....................................................................................... 1328Figure 26-14. Host-Bus 8/16 Mode Read Timing ..................................................................... 1329Figure 26-15. Host-Bus 8/16 Mode Write Timing ..................................................................... 1329Figure 26-16. Host-Bus 8/16 Mode Muxed Read Timing .......................................................... 1330Figure 26-17. Host-Bus 8/16 Mode Muxed Write Timing .......................................................... 1330Figure 26-18. General-Purpose Mode Read and Write Timing ................................................. 1331Figure 26-19. General-Purpose Mode iRDY Timing ................................................................. 1331Figure 26-20. ADC Input Equivalency Diagram ....................................................................... 1333Figure 26-21. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing

Measurement .................................................................................................. 1334Figure 26-22. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............... 1334Figure 26-23. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................... 1335Figure 26-24. I2C Timing ....................................................................................................... 1336Figure 26-25. I2S Master Mode Transmit Timing ..................................................................... 1336Figure 26-26. I2S Master Mode Receive Timing ...................................................................... 1337Figure 26-27. I2S Slave Mode Transmit Timing ....................................................................... 1337Figure 26-28. I2S Slave Mode Receive Timing ........................................................................ 1337Figure 26-29. External XTLP Oscillator Characteristics ........................................................... 1340Figure C-1. Stellaris LM3S9D92 100-Pin LQFP Package Dimensions ................................... 1401Figure C-2. 100-Pin LQFP Tray Dimensions ........................................................................ 1403Figure C-3. 100-Pin LQFP Tape and Reel Dimensions ......................................................... 1404Figure C-4. Stellaris LM3S9D92 108-Ball BGA Package Dimensions .................................... 1405Figure C-5. 108-Ball BGA Tray Dimensions ......................................................................... 1407Figure C-6. 108-Ball BGA Tape and Reel Dimensions .......................................................... 1408



List of TablesTable 1. Revision History .................................................................................................. 42Table 2. Documentation Conventions ................................................................................ 46Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ................................ 76Table 2-2. Processor Register Map ....................................................................................... 77Table 2-3. PSR Register Combinations ................................................................................. 82Table 2-4. Memory Map ....................................................................................................... 90Table 2-5. Memory Access Behavior ..................................................................................... 93Table 2-6. SRAM Memory Bit-Banding Regions .................................................................... 95Table 2-7. Peripheral Memory Bit-Banding Regions ............................................................... 95Table 2-8. Exception Types ................................................................................................ 101Table 2-9. Interrupts .......................................................................................................... 102Table 2-10. Exception Return Behavior ................................................................................. 107Table 2-11. Faults ............................................................................................................... 108Table 2-12. Fault Status and Fault Address Registers ............................................................ 109Table 2-13. Cortex-M3 Instruction Summary ......................................................................... 111Table 3-1. Core Peripheral Register Regions ....................................................................... 114Table 3-2. Memory Attributes Summary .............................................................................. 117Table 3-3. TEX, S, C, and B Bit Field Encoding ................................................................... 120Table 3-4. Cache Policy for Memory Attribute Encoding ....................................................... 121Table 3-5. AP Bit Field Encoding ........................................................................................ 121Table 3-6. Memory Region Attributes for Stellaris Microcontrollers ........................................ 121Table 3-7. Peripherals Register Map ................................................................................... 122Table 3-8. Interrupt Priority Levels ...................................................................................... 149Table 3-9. Example SIZE Field Values ................................................................................ 177Table 4-1. JTAG_SWD_SWO Signals (100LQFP) ................................................................ 181Table 4-2. JTAG_SWD_SWO Signals (108BGA) ................................................................. 182Table 4-3. JTAG Port Pins State after Power-On Reset or RST assertion .............................. 183Table 4-4. JTAG Instruction Register Commands ................................................................. 188Table 5-1. System Control & Clocks Signals (100LQFP) ...................................................... 192Table 5-2. System Control & Clocks Signals (108BGA) ........................................................ 192Table 5-3. Reset Sources ................................................................................................... 193Table 5-4. Clock Source Options ........................................................................................ 200Table 5-5. Possible System Clock Frequencies Using the SYSDIV Field ............................... 202Table 5-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 202Table 5-7. Examples of Possible System Clock Frequencies with DIV400=1 ......................... 203Table 5-8. System Control Register Map ............................................................................. 207Table 5-9. RCC2 Fields that Override RCC Fields ............................................................... 229Table 6-1. Flash Memory Protection Policy Combinations .................................................... 304Table 6-2. User-Programmable Flash Memory Resident Registers ....................................... 308Table 6-3. Flash Register Map ............................................................................................ 309Table 7-1. DMA Channel Assignments .............................................................................. 348Table 7-2. Request Type Support ....................................................................................... 350Table 7-3. Control Structure Memory Map ........................................................................... 351Table 7-4. Channel Control Structure .................................................................................. 351Table 7-5. DMA Read Example: 8-Bit Peripheral ................................................................ 361Table 7-6. DMA Interrupt Assignments .............................................................................. 362


Table of Contents

Table 7-7. Channel Control Structure Offsets for Channel 30 ................................................ 363Table 7-8. Channel Control Word Configuration for Memory Transfer Example ...................... 363Table 7-9. Channel Control Structure Offsets for Channel 7 .................................................. 364Table 7-10. Channel Control Word Configuration for Peripheral Transmit Example .................. 365Table 7-11. Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 366Table 7-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive

Example ............................................................................................................ 367Table 7-13. DMA Register Map .......................................................................................... 369Table 8-1. GPIO Pins With Non-Zero Reset Values .............................................................. 408Table 8-2. GPIO Pins and Alternate Functions (100LQFP) ................................................... 408Table 8-3. GPIO Pins and Alternate Functions (108BGA) ..................................................... 410Table 8-4. GPIO Pad Configuration Examples ..................................................................... 416Table 8-5. GPIO Interrupt Configuration Example ................................................................ 417Table 8-6. GPIO Pins With Non-Zero Reset Values .............................................................. 418Table 8-7. GPIO Register Map ........................................................................................... 418Table 8-8. GPIO Pins With Non-Zero Reset Values .............................................................. 430Table 8-9. GPIO Pins With Non-Zero Reset Values .............................................................. 436Table 8-10. GPIO Pins With Non-Zero Reset Values .............................................................. 438Table 8-11. GPIO Pins With Non-Zero Reset Values .............................................................. 441Table 8-12. GPIO Pins With Non-Zero Reset Values .............................................................. 448Table 9-1. External Peripheral Interface Signals (100LQFP) ................................................. 464Table 9-2. External Peripheral Interface Signals (108BGA) ................................................... 465Table 9-3. EPI SDRAM Signal Connections ......................................................................... 470Table 9-4. Capabilities of Host Bus 8 and Host Bus 16 Modes .............................................. 474Table 9-5. EPI Host-Bus 8 Signal Connections .................................................................... 475Table 9-6. EPI Host-Bus 16 Signal Connections .................................................................. 477Table 9-7. EPI General Purpose Signal Connections ........................................................... 486Table 9-8. External Peripheral Interface (EPI) Register Map ................................................. 492Table 10-1. Available CCP Pins ............................................................................................ 538Table 10-2. General-Purpose Timers Signals (100LQFP) ....................................................... 539Table 10-3. General-Purpose Timers Signals (108BGA) ......................................................... 540Table 10-4. General-Purpose Timer Capabilities .................................................................... 541Table 10-5. Counter Values When the Timer is Enabled in Periodic or One-Shot Modes .......... 542Table 10-6. 16-Bit Timer With Prescaler Configurations ......................................................... 543Table 10-7. Counter Values When the Timer is Enabled in RTC Mode .................................... 544Table 10-8. Counter Values When the Timer is Enabled in Input Edge-Count Mode ................. 545Table 10-9. Counter Values When the Timer is Enabled in Input Event-Count Mode ................ 546Table 10-10. Counter Values When the Timer is Enabled in PWM Mode ................................... 547Table 10-11. Timers Register Map .......................................................................................... 552Table 11-1. Watchdog Timers Register Map .......................................................................... 587Table 12-1. ADC Signals (100LQFP) .................................................................................... 611Table 12-2. ADC Signals (108BGA) ...................................................................................... 612Table 12-3. Samples and FIFO Depth of Sequencers ............................................................ 613Table 12-4. Differential Sampling Pairs ................................................................................. 621Table 12-5. ADC Register Map ............................................................................................. 629Table 13-1. UART Signals (100LQFP) .................................................................................. 692Table 13-2. UART Signals (108BGA) .................................................................................... 692Table 13-3. Flow Control Mode ............................................................................................. 698



Table 13-4. UART Register Map ........................................................................................... 703Table 14-1. SSI Signals (100LQFP) ...................................................................................... 756Table 14-2. SSI Signals (108BGA) ........................................................................................ 756Table 14-3. SSI Register Map .............................................................................................. 767Table 15-1. I2C Signals (100LQFP) ...................................................................................... 797Table 15-2. I2C Signals (108BGA) ........................................................................................ 797Table 15-3. Examples of I2C Master Timer Period versus Speed Mode ................................... 801Table 15-4. Inter-Integrated Circuit (I2C) Interface Register Map ............................................. 811Table 15-5. Write Field Decoding for I2CMCS[3:0] Field ......................................................... 817Table 16-1. I2S Signals (100LQFP) ...................................................................................... 836Table 16-2. I2S Signals (108BGA) ........................................................................................ 836Table 16-3. I2S Transmit FIFO Interface ................................................................................ 839Table 16-4. Crystal Frequency (Values from 3.5795 MHz to 5 MHz) ........................................ 840Table 16-5. Crystal Frequency (Values from 5.12 MHz to 8.192 MHz) ..................................... 840Table 16-6. Crystal Frequency (Values from 10 MHz to 14.3181 MHz) .................................... 841Table 16-7. Crystal Frequency (Values from 16 MHz to 16.384 MHz) ...................................... 841Table 16-8. I2S Receive FIFO Interface ................................................................................. 843Table 16-9. Audio Formats Configuration .............................................................................. 845Table 16-10. Inter-Integrated Circuit Sound (I2S) Interface Register Map ................................... 846Table 17-1. Controller Area Network Signals (100LQFP) ........................................................ 873Table 17-2. Controller Area Network Signals (108BGA) ......................................................... 873Table 17-3. Message Object Configurations .......................................................................... 879Table 17-4. CAN Protocol Ranges ........................................................................................ 886Table 17-5. CANBIT Register Values .................................................................................... 886Table 17-6. CAN Register Map ............................................................................................. 890Table 18-1. Ethernet Signals (100LQFP) ............................................................................... 924Table 18-2. Ethernet Signals (108BGA) ................................................................................ 924Table 18-3. TX & RX FIFO Organization ............................................................................... 927Table 18-4. Ethernet Register Map ....................................................................................... 934Table 19-1. USB Signals (100LQFP) .................................................................................... 985Table 19-2. USB Signals (108BGA) ...................................................................................... 985Table 19-3. Remainder (MAXLOAD/4) .................................................................................. 997Table 19-4. Actual Bytes Read ............................................................................................. 997Table 19-5. Packet Sizes That Clear RXRDY ........................................................................ 998Table 19-6. Universal Serial Bus (USB) Controller Register Map ............................................ 999Table 20-1. Analog Comparators Signals (100LQFP) ........................................................... 1123Table 20-2. Analog Comparators Signals (108BGA) ............................................................. 1124Table 20-3. Internal Reference Voltage and ACREFCTL Field Values ................................... 1126Table 20-4. Analog Comparators Register Map ................................................................... 1127Table 21-1. PWM Signals (100LQFP) ................................................................................. 1139Table 21-2. PWM Signals (108BGA) ................................................................................... 1140Table 21-3. PWM Register Map .......................................................................................... 1147Table 22-1. QEI Signals (100LQFP) .................................................................................... 1214Table 22-2. QEI Signals (108BGA) ..................................................................................... 1215Table 22-3. QEI Register Map ............................................................................................ 1218Table 24-1. GPIO Pins With Default Alternate Functions ...................................................... 1238Table 24-2. Signals by Pin Number ..................................................................................... 1239Table 24-3. Signals by Signal Name ................................................................................... 1251


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Table 24-4. Signals by Function, Except for GPIO ............................................................... 1261Table 24-5. GPIO Pins and Alternate Functions ................................................................... 1270Table 24-6. Possible Pin Assignments for Alternate Functions .............................................. 1273Table 24-7. Signals by Pin Number ..................................................................................... 1276Table 24-8. Signals by Signal Name ................................................................................... 1288Table 24-9. Signals by Function, Except for GPIO ............................................................... 1299Table 24-10. GPIO Pins and Alternate Functions ................................................................... 1308Table 24-11. Possible Pin Assignments for Alternate Functions .............................................. 1311Table 24-12. Connections for Unused Signals (100-Pin LQFP) ............................................... 1314Table 24-13. Connections for Unused Signals (108-Ball BGA) ................................................ 1315Table 25-1. Temperature Characteristics ............................................................................. 1316Table 25-2. Thermal Characteristics ................................................................................... 1316Table 25-3. ESD Absolute Maximum Ratings ..............................................