the cortex-m3 embedded systems: lm3s9b96 microcontroller – system control refer to chapter 6 in...
TRANSCRIPT
The Cortex-M3 Embedded Systems:
LM3S9B96 Microcontroller – System Control
Refer to Chapter 6 in the reference book“Stellaris® LM3S9B96 Microcontroller - DATA SHEET”
High-Level Block Diagram
System Control
System control configures the overall operation of the device and provides information about the device. reset control NMI operation power control clock control low-power modes
Reset Sources
The LM3S9B96 microcontroller has six sources of reset Power-on reset (POR)
The internal POR circuit monitors the power supply voltage VDD and generates a reset signal to all of the internal logic including JTAG when the power supply ramp reaches a threshold value.
External reset input pin (RST) assertion The external reset pin (RST) resets the microcontroller
including the core and all the on-chip peripherals except the JTAG TAP controller
Internal brown-out (BOR) detector brown-out detection circuit that triggers if the power
supply VDD drops below a brown-out threshold voltage
Reset Sources
Software-initiated reset The entire microcontroller including the core can be
reset by software by setting the SYSRESETREQ bit in the Cortex-M3 Application Interrupt and Reset Control register
On-chip peripherals can be individually reset by software via three registers (see the SRCRn registers)
A watchdog timer reset condition violation A watchdog timer can be configured to generate an
interrupt to the microcontroller on its first time-out and to generate a reset on its second time-out
MOSC failure The LM3S9B96 microcontroller provides a main
oscillator verification circuit that generates an error condition if the oscillator is running too fast or two slow
After the processor exits reset, it will read two words from memory: Address 0x00000000: default value of R13 (MSP)
Address 0x00000004: If the data at 0x00000004 is not 0xFFFFFFFF, load the
Reset vector (the starting address of startup program) Otherwise, the core executes the ROM Boot Loader
Cortex-M3: Reset Sequence
ResetAddress=
0x00000000Address=
0x00000004Address=
Reset Vector
Fetch InitialSP Value
Fetch ResetVector
InstructionFetch
Time
Power Control
Within the MCU, an integrated LDO regulator is used to provide power to the majority of the MCU's internal logic Voltage output can be
programmed between 2.25 V and
2.75 V
Clock Control
Fundamental Clock Sources Precision Internal Oscillator (PIOSC): on-chip clock
source, 16MHz + 1%, used by the microcontroller during POR
Main Oscillator (MOSC): an external crystal is connected across the OSC0 input and OSC1 output pins; if PLL is being used, crystal frequency range from 3.579545 MHz to 16.384 MHz (inclusive); if not, between 1 MHz and 16.384 MHz
Internal 30-kHz Oscillator: on-chip clock source, 30kHz + 50%, used during Deep-Sleep power-saving modes
The internal system clock can be derived from all above clock sources and the output of PLL and PIOSC divided by four (4MHz + 1%)
Clock Configuration
The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2) registers provide control for the system clock
Source of clocks in sleep and deep-sleep modes
System clock derived from PLL or other clock source
Enabling/disabling of oscillators and PLLClock divisorsCrystal input selection
Register 7: Run-Mode Clock Configuration (RCC), offset 0x060
Register 7: Run-Mode Clock Configuration (RCC), offset 0x060
Register 7: Run-Mode Clock Configuration (RCC), offset 0x060
Register 7: Run-Mode Clock Configuration (RCC), offset 0x060
Register 7: Run-Mode Clock Configuration (RCC), offset 0x060
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070
when the USERCC2 bit is set, allowing the extended capabilities of the RCC2 register to be used
Main Clock Tree
Configuration on PLL
The PLL is configured using direct register writes to the RCC/RCC2 register
The steps required to successfully change the PLL-based system clock are: 1. Bypass the PLL and system clock divider by setting the
BYPASS bit and clearing the USESYS bit in the RCC register 2. Select the crystal value (XTAL) and oscillator source
(OSCSRC), and clear the PWRDN bit in RCC/RCC2. 3. Select the desired system divider (SYSDIV) in RCC/RCC2
and set the USESYSDIV bit in RCC 4. Wait for the PLL to lock by polling the PLLLRIS bit in the
Raw Interrupt Status (RIS) register 5. Enable use of the PLL by clearing the BYPASS bit in
RCC/RCC2
System Control
For power-savings purposes, the RCGCn, SCGCn, and DCGCn registers control the clock gating logic for each peripheral or block in the system while the microcontroller is in Run, Sleep, and Deep-Sleep mode, respectively. Run mode: the microcontroller actively executes code. The
processor and all of the peripherals that are currently enabled by the RCGCn registers operate normally.
Sleep mode: (entered by executing a WFI (Wait for Interrupt) instruction), peripherals enabled by the SCGCn (when auto-clock gating is enabled) registers are clocked, but the processor and the memory subsystem are not clocked.
Deep Sleep mode: (entered by first writing the Deep Sleep Enable bit in the NVIC system control register and then executing a WFI instruction), only peripherals enabled by the DCGCn (when auto-clock gating is enabled) registers are clocked.
Register 27: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100
Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. All functional modules are disabled after reset.
Register 30: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104
Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. All functional modules are disabled after reset.
Register 33: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108
Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. All functional modules are disabled after reset.