Status of TRD Pre-trigger System

K. Oyama, T. Krawutschke, A. Rausch, J. Stachel,

P. von Walter, R. Schicker and M. Stockmeier

for the T0, V0, and TRD Collaborations

Sep. 26, 2005

TRD Status Meeting in Cheile Grădiştei, Romania

Sep. 26, 2005 2

TRD pre-trigger = wakeup signal sent to TRD MCMs.

It is generated from T0, V0 and TOF detector signals using special boxes (not shoeboxes anymore).

T0: Timing detector and M.B. trigger. V0: Vertex detection and M.B. trigger. TOF: cosmic trigger and some physics triggers in low multiplicity environments.

detailed talk by R.Schicker Since timing is crucial, the system is placed inside L3 magnet.

The pre-trigger system should have the functionalities:

generate pre-trigger coincidence signal of T0, V0 and TOF detectors. get TTC optical signal from CTP and insert pre-trigger into TTC stream. provide TTC optical signals to 18 TRD super-modules. generate control signals for FSM in MCMs (new).

The TRD Pre-trigger System

Sep. 26, 2005 3

CLK

L1 trigBefore Shoebox

After Shoebox L1 trigpre-trig

T0

(anti-)coincidence

TTCex

bi-phase-markdecode

bi-phase-markencode

L0, L1, …

To use TTCvi in the magnet is avoided because we would need VME bus and VME bus master, and TTCvi delay inside is large.

TRD

pre-triggersystem

L1, L2,…

+ pre-trigger

+ FSM control

outside magnet

inside magnet

Basic Concept of Implementation

V0

TOF

CTP

Sep. 26, 2005 4

The Timing Diagram of the Pre-trigger and Data Flow

T0 or V0 PMT

Front End Boxes A

Final Coincidenceand BPM encoding

Coincidence for Side A

TTCex and TTCtx

TTCrx

MCM SM

CTP

TOF FEE

TOF Trigger Box

Wakeup

Tim

e

@ 160 ns by Eugenio

cable along z (10 m) and phi (10 m)

inside TRDSuper Module

= 30 nscoincidenceby R.Schicker

cable (would be short)

100

ns

5 ns

= 15 nsPMT response time

= 25 nsdelay and coincidence

= 25 ns

= 80 ns

= 15 ns

= 50 ns

= 150 nsdecoding & wake-up (slow clock latch)

= 50 ns coin. logic

5 ns

5 ns

50 n

s12

ns

1 ns

PASA = 50 ns (shaping time = 120 ns)

15 n

s

Programmable Delay

Filter

= 100 to 600 ns

ADC Pipeline = 150 ns

= 200 ns

Event Buffer

cable (40 m fiber)

200

ns20

0 ns

cable (40 m fiber)

@ 137 ns@ 295 ns

@ 1015 ns

@ 716 ns

3.5 m air

1 m cable

1 m cable

10 m through inner bar (7m) and radial

@ 391ns

CB-C10

0 ns

20 m fiber (to the farthest chamber)@ 491ns

25 n

sCB-A

Interaction

pretrigger for CTP

L0

Sep. 26, 2005 5

T0-CT0-A

A Cinner bar

(7m) TRD

FEB

CB-A

Position of Pre-trigger Components

CB-C

FEB

FEB

FEBFEB

FEBFEB

FEB

FEBFEB

CB-TOFTOF signals

Sep. 26, 2005 6

Detailed Arrangement of Pre-trigger Components

Sep. 26, 2005 7

T0/V0Preamp

fromdetector

to T0 and V0 rackpre-amp power

top viewside view

term

inat

ion

diff

eren

tial s

igna

l

optionalfor redundancy

~VME size

Front-end Box with T0 and V0 Pre-Amplifiers

JTAG

CLK, Trig

Control500 ps delay PECL discriminator

FPGA

Independent power for pre-amp and digital part.Design is 99 % ready for prototyping. T0/V0 people are now fixing power connector for pre-amplifier, then we can produce.

Sep. 26, 2005 8

input from the PMT

x1 feed-through outputx10 output

power

differentialoutput to TRD pre-trigger system

30 ps resolution was achieved in the test beam experiment.High ground and power stability are required.Power is given from different source with out pre-trigger system.Using inductance but still works in the B=0.5 T.

Design is final.55mm x 55mm.Three SMA connectors.0.5 W/ch.

T0 and V0 Pre-amplifier Module

Sep. 26, 2005 9

Prototype Control Board with DCS

Tobias Krawutschke already started design of FPGA on the DCS.

Sep. 26, 2005 10

Control Box Crates

CB-TOF(C side, with TOF trigger and TTC functionality)

CB-A and CB-C

576 bits 144 cablesfrom TOF system

main backup main backup

Sep. 26, 2005 11

Proposal and Requirement for LV Distribution

Sep. 26, 2005 12

Prototype of control board came, and we started testing it. Prototype design of front-end board is 99 % finished and it will be available

soon.

Action items:

Final space, and power requirement should be approved. Cooling question is still open. Radiation tests: we will have all components soon, and then just do.

Conclusions

Sep. 26, 2005 13

Main Control BoardMain Control Board

DCS

-delay-control

-threshold

ptre-trig from side A DCS (LVD)

pre-trig to side C DCS (LVD)

TTC input (opt.)

Pre-Trigger to CTP (opt. or LVD)

Ethernet (cat5).

JTAG to local boxes (LVD)

TTC ECL out to F.O. module (ECL)

TTC F.O. 2

TTC F.O. 1

DCS

d=210 mm

h=27

0 m

m

w=110 mm

TTC F.O. can be TTCex or TTCex.DCS module is a VME size board + KIP DCS on it.DCS module has also coincidence of pre-trigger of side A and C.

CLK/Control to local boxes (LVD)

Triggers from local boxes (LVD)

Sep. 26, 2005 14

- System may have malfunctioning due to radiation, B field, and normal problems.

- We loose entire TRD data if we loose the pre-trigger system.

- We can consider to have duplication of all digital part (without analog part).

Duplicated part (System II) is identical to System I and run independently.

Two optical fibers should go to each TRD super-module and merged inside, it is possible (study by Marc).

System I

System II

Fault ToleranceFault Tolerance

Sep. 26, 2005 15

Timing Constraint CTP must receive trigger from TRD in 6 us.