spiroc readout for pebs

Waclaw Karpinski 128.09.2009

SPIROC READOUT FOR PEBS

W. KarpinskiI. Physikalisches Institut

Geneva, 28 January 2009


Outline

• SPIROC global overview

• Description of the Readout Board for 128 channels

• First measurements

• Summary

SPIROC main characteristics • SPIROC : Silicon Photomul. Integrated Readout Chip

- 36 channels- two gains (1:10) - positive input pulse- DAC on each input- Charge measurement from 1pe to 2000 pe (at SiPm gain 1 x 106 el)

- Time measurement with the accuracy of 100 ps- Autotrigger on 1/3 pe- complex digital part to transfer the data to DAQ- Chips daisy-chained- Chip size: 4.2mm x 7.2mm- Package QFP-240- 0.35µm SiGe technology from AMS

28.09.2009 Waclaw Karpinski 3

SPIROC : One channel schematic


IN test 25 -175ns

25-175ns

Gain selection

4-bit threshold adjustment

10-bit DAC

10ns

DAC output

HOLD

Slow Shaper

Slow Shaper

Fast Shaper

Time measurement

Charge measurement

TDC ramp

300ns/5 µs

12-bit Wilkinson

ADC

Trigger

Depth 16

Depth 16

Depth 16

Common to the 36 channels

8-bit DAC

0-4.5V

Low gain Preamplifier

High gain Preamplifier

Analog memory

15pF

1.5pF

0.1pF-1.5pF

Conversion

100 µs

READ

Variable delay

0.1pF-1.5pF

IN

Discri

Gain

Flag TDC

28.09.2009 Waclaw Karpinski 5DAQASIC

Chip ID register 8 bits

gain

Trigger discri Output

Wilkinson ADC Discri output

gain

Trigger discri Output

Wilkinson ADC Discri output

..…

OR36

EndRamp (Discri ADC Wilkinson)

36

36

36

TM (Discri trigger)

ValGain (low gain or high Gain)

ExtSigmaTM (OR36)

Channel 1

Channel 0

ValDimGray 12 bits

…

Acquisition

readout

Conversion ADC

+

Writing RAM

RAM

FlagTDC

ValDimGray

12

8

ChipID

Hit channel register 16 x 36 x 1 bits

TDC rampStartRampTDC

BCID 16 x 8 bits

ADC rampStartrampb (wilkinson

ramp)

16

16ValidHoldAnalogb

RazRangN

16ReadMesureb

Rstb

Clk40MHz

SlowClock

StartAcqt

StartConvDAQb

StartReadOut

NoTrig

RamFull

TransmitOn

OutSerie

EndReadOut

Chipsat

Waclaw Karpinski

Chip for SiPM : SPIROC

6

36 8bit

5V DAC

Dual DACBandgap

three 36*16 Analog

memories

36 PreampShaperdiscri

36 Wilkinson

ADC

SRAMReadout

28.09.2009

ILC beam structure


Acquisition

1ms (.5%)

A/D conv..5ms (.25%)

DAQ.5ms (.25%)

1% duty cycle

IDLE MODE

99% idle cycle

198ms (99%)

time

Time between two trains: 200ms (5 Hz)

Time between two bunch crossing: 337 ns

Train length 2820 bunch X (950 µs)

• two orders of magnitude saved on the power consumption• the anticipated power consumption 25 µW/channel

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Pulse at analog output as a function of shaping time

28.09.2009

25ns 50ns 75ns 125ns 175ns

injected charge =18.7 x 106 el. , High-Gain, CFB=100 fF

SPIROC in CQFP-240

Preset Value vs Measured Value 25 ns 55 ns 50 ns 75 ns 75 ns 95 ns 100 ns 110 ns 125 ns 125 ns 150 ns 140 ns 175 ns 150 ns

Test board designed by Orsay group


0.0 50.0 100.0 150.0 200.0 250.00.0

100.0

200.0

300.0

400.0

500.0

600.0T=25ns, HG Cfb=100fF Polynomial (T=25ns, HG Cfb=100fF)

injected charge [106electrons]

HIGH GAIN

[mV

]Pulse Amplitude on SPIROC Output

0.0 200.0 400.0 600.0 800.0 1000.0 1200.0 1400.0 1600.0 1800.0 2000.00.0

100.0

200.0

300.0

400.0

500.0

600.0

700.0T=25ns, LG, Cfb=off T=25ns, LG, Cfb=100fF

injected charge [106electrons]

LOW GAIN

• Two gain ranges: High and Low• In each range gain adjustable with feedback capacitors• 4 bits resolution: Cfb = 0.1fF, 02fF, 04fF,0.8fF• dynamic range in the high gain: from spe to 200 pe (at SiPm gain 1 x 106 el)

• in low gain range energy measurement up to ~2000 pe

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SPIROC & Hamamatsu SiPm S10362-11-100C (gain ~2x106)Vbias =70.2 V, I=0,60 µA Shaping Time = 25 ns (preset value)High Gain Feedback Cap. = 100 fF

S/N = 7.7 +/- 0.2

28.09.2009

Single photoelectron spectrum



SPIROC & Hamamatsu SiPm S10362-11-100C (gain ~2x106)Vbias =70.2 V, I=0,60 µA Shaping Time = 25 ns (set value )High Gain Feedback Cap. = 200 fF

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S/N = 6.6 +/- 0.2

28.09.2009





S/N = 5.4 +/- 0.3


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Readout board HPE_SPIROC-128

• analog, multipexed readout of 128 channels • 4 Spiroc chips, 32 channels per chip • chips mounted on a pluggable chip carrier• interface to the DAQ compatible with TDR • download of slow control parameters via USB or SPI interface

Interface to TDR

US

B I

nte

rfa

ceS

PI

Inte

rfa

ceS

PIR

OC

16 mm

13 m

m


• SPIROCs slow control register consist of 702 bits. • The data for up to 8 SPIROCS stored in the UFM block of the Altera MAXII CPLD• The data stored in the UFM Block can be modified from higher DAQ using SPI or USB Interface.

• After power up the data will be automatically downloaded from CPLD to the SPIROC

• After downloading the state machine automatically compares the data stored in the CPLD and in the SPIROC chips, simultaneously counts the number of errors and stores the result in 8 registers and 8 error flags For simplicity LED are implemented to indicate the status of the error flags• CPLD decodes also the control signals sent from TDR

• allows channel selection without higher DAQ . The channel number is transferred via SPI or USB Interface

Functionality of the CPLD

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Graphical Interface to modify Control Parameters

28.09.2009

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First Result• the readout board operational• 12 chips assembled on the chip carriers• yield of the chips ~50%• if register outputs not used yield ~ 85%

28.09.2009

SPIROC# slow control register register output analog output

1 ok ok no function

2 ok ok no function

3 ok ok no function

4 ok ok no function

5 ok no function ok

6 ok no function ok

7 ok ok ok

8 no function no function no function

9 ok ok ok

10 ok no function ok

11 ok ok ok, ch10 low gain

12 ok ok ok

analog outputs broken during commissioningbecause of bag in the bonding program

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Slow control register

28.09.2009

• Problem with the length of slow control register:

inside the chip, there are 703 flip-flops

on the test board form Orsay the tests show that one flip-flop is missing, only 702 bits programmable

on our tests boards we see only 701bits The behavior is stable and the same for all measured chips

due to the chip designer the reason are some fan-out issues

on the data and the clock paths of the slow control register. .


Analog Output

sdev=3.3mV

sdev=3.3mV sdev=8.4mV

sdev=3.9mV

Test pulse response; High gain, Cfb=100fF, shaping time 25 ns

• for small signals standard deviation of base line and signal peak the same

• for large signals standard deviation of signal peak significantly higher than of the base line• this behavior is not observed on test board from Orsay

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0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.00.0

500.0

1000.0

1500.0

2000.0

2500.0

3000.0

3500.0

4000.0

0.0

10.0

20.0

30.0

40.0

50.0

60.0

70.0

80.0

90.0

100.0

Linearity of SPIROC Chip 12

Channel 03Channel 11Channel 19Channel 27Std. Dev. Ch. 03Std. Dev. Ch. 11Std. Dev. Ch. 19Std. Dev. Ch. 27

Charge [ 106 el ]

Puls

e M

ax.

[A

DC

counts

]

Std

. D

evia

tion

[AD

C C

ounts

]28.09.2009

• high gain, Cfb=100fF, T=25ns• for small signals: spe/noise= 10• for large signals: spe/noise= 2• Gain uniformity: RMS 1%• all tested chips show similar behavior

Analog Output


• Spectra taken with both readout boards: Aachen and Orsay under the same conditions: o High gain, Cfb=100fF, T=25nso Hamamatsu SiPm S10362-11-100Co Vbias =70.2 V, I=0,60 µA

• no significant differences in gain and noise performance between the readout boards

Aachen readout board

Orsay readout board



0

2

4

6

8

10

12

0

500

1000

1500

2000

2500

3000

3500

4000

4500

0 200 400 600 800 1000 1200 1400 1600 1800

Std.

Dev

iati

on [

AD

C Co

unts

]

Puls

e M

ax.

[AD

C co

unts

]

Charge [ 106 el ]

Linearity of SPIROC Chip 12Low Gain, 100pF, 25ns

Channel 03

Channel 11

Channel 19

Channel 27

Std. Dev. Ch. 03

Std. Dev. Ch. 11

Std. Dev. Ch. 19

Std. Dev. Ch. 27

Analog Output

• low gain, Cfb=1.5pF, T=25ns• noise independent of the signal amplitude• gain uniformity: RMS 7%

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0.00

100.00

200.00

300.00

400.00

500.00

600.00

700.00

800.00

900.00

1000.00

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

AD

C Va

lue

Channel

Pedestal Measurement of SPIROC Chip 12

12.00

12.50

13.00

13.50

14.00

14.50

15.00

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Std

Dev

Channel

Standard Deviation of Pedestal Measurement

28.09.2009

Multiplexed Readout

Pedestal uniformity:Avg = 789 mV

RMS = 11.4 mV

equal noise of all channels

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INPUT DAC

28.09.2009

36 DACs, one per channel8 bit, 2.5V rangeLSB ~10mVvery low power consumption ~1µWcan absorb up to 10 µA leakage current from SiPmlinearity: ± 2%


Power Consumption

• Total Power Consumption ~ 390 mW/chip →10.8mW/ch• Breakdown of the power consumption:

– preamplifier+shaper = 4 mW/channel– SCA = 5.6 mW/channel– auxiliary parts (not consciously used) =2.2

mW/channel • Not acceptable for Tracker !• Investigation of possibilities leading to significant

reduction of power consumption necessary • backup solution: VA32-75 or its successesor


Analog Output Impedance

• SPIROC has not a high impedance analog output

• the analog outputs can not be connected in daisy chain directly

• one possibility is to implement an analog multiplexer

between the SPIROC outputs

SPIROC-Summary


SPIROC

signal polarity positive

number of channels 36

dynamic range High / Low Gain 30 300 [pC]

gain Hamamatsu SiPms Tracker/ECAL 9*105 2.75*105

dynamic range SPIROC + SIPMs Tracker/ECAL 208 6808 [pe]

noise Spiroc w/o detector 14 [fC]

noise Spiroc w/o detector 0.1 [pe]

shaping time 50 - 150 [ns]

power supply 3.5 [V]

power consumption 10.8 mW/channel

readout frequency 5 [MHz]

die size 7.3 x 4.3 x 0.6 [mm]

input impedance high [Ohm]

gain adjustment 4 bits in High & Low Gain


Summary

• charge measurement from 1 pe to 2000 pe (at SiPm gain of 1 x 106 ) in two linear scales

• S/N of 10 w/o noise contribution from the detector, however on Aachen readout board additional jitter of the signal peak observed for input signals larger than 15 pe (at highest gain)

• good pedestal and gain uniformity between channels on one chip

• Ultra low power, 8bit input DAC for SiPM gain adjustment on each channel, resolution and range adjustable. on Aachen readout board the resolution=10 mV, range=2.5 V

• yield of the chip production low ~50%, (~ 85% )

• high power consumption 10,8 mW/channel ! to much for PEBS Fiber Tracker• investigation of options leading to significant reduction of the power consumption necessary


Backup Transparences

SPIROC main features• Internal input 8-bit DAC (0-5V) for individual SiPM gain

adjustment• Energy measurement : 14 bits

2 gains (1-10) + 12 bit ADC 1 pe 2000 pe (300pC)Variable shaping time from 25ns to 175ns pe/noise ratio : 10

• Auto-trigger on 1/3 pe (50fC)pe/noise ratio on trigger channel : 24Fast shaper : ~10ns

• Time measurement : 12-bit Bunch Crossing ID12 bit TDC step~100 ps

• Analog memory for time and charge measurement : depth = 16• Individually addressable calibration injection capacitance• Embedded bandgap for voltage references• Embedded 10 bit DAC for trigger threshold and gain selection• Multiplexed analog output • 4k internal memory and Daisy chain readout


Input preamp

• Bi-gain low noise preampLow noise charge preampcapacitively coupled = voltage preamp

• High gain - 15 pF coupling capacitor

• Low gain - 1.5pF coupling capacitor

MAX : 2000 pe ( at SiPm gain 1 x 106)

=300pC

•Gain adjustable with 4 bits common to all preamps : Cf=0.1, 0.2, 0.4, 0.8 pF

•Positive input pulse

•Power specified: 2 mW (unpulsed) measured: 4 mW


15pF 0.1pF-1.5pF

+HV

Si PM

8-bit DAC

ASICHigh voltage on the

cable shieldi

ng

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VA75-32 Chip

32

cell

bit

-regis

ter

32

x A

nalo

gu

e M

ux.

32

cell

bit

-regis

ter

32

cell

bit

-regis

ter

32

x A

nalo

gu

e M

ux.

28.09.2009

VA32-75 Chip -Summary VA32-75

signal polarity bipolar


dynamic range 36 [fC]

gain Hamamatsu SiPms (Tracker) 9*105

dynamic range VA32-75+SiPms Tracker 0.25 [pe]

shaping time 75 - 150 [ns]

noise 8*10-2 [fC]

noise w/o SiPm (dynamic range 30 pe) 0.24 [pe]

noise w SiPm (dynamic range 30 pe) 0.30 [pe]

nois w/o SiPm (dynamic range 100 pe) 0.42 [pe]

S/N w SiPm (dynamic range 100 pe) 2.2

power supplies +2, -2 [V]

power consumption 1.6 mW/channel


die size 3.4 x 3.4 x 0.6 [mm]


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VA during beam test

S/N=6.08

28.09.2009

HARDROC

HARDROC has been designed to read out the CALICE RPC DHCAL technical

prototype.28.09.2009 35 Waclaw Karpinski

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HARDROC main features

Full power pulsing

Digital memory: Data saved during bunch train.

Only one serial output @ 1 or 5MHz

Store all channels and BCID for every hit. Depth = 128 bits

Data format : 128(depth)*[2bit*64ch+24bit(BC

ID)+8bit(Header)] = 20kbits

BASICALLY : MAROC with internal RAM and time counting

28.09.2009

HARDROC Summary

HARDROC

signal polarity negative


dynamic range 15 [pC]

gain IRST SiPms 1*106

dynamic range for IRST 94 [pe]

minimum shaping time 75 - 150 [ns]

noise 8 [fC]

S/N w/o SiPm 0.05

S/N with SiPm 0.21

power supplies 3.5 [V]

power consumption 2 mW/channel


die size 4 x 4 x 0.6 [mm]

input impedance 50 - 100 [Ohm]

gain adjustement 4 bit


Slow shaper & SCA

• Slow shaper from HaRDROCVariable peaking time 3 bits common to all channelsspecified : 25-175 ns

• Backup : analog S&HHold capacitor : 0.5 pFNeeds external hold signalMultiplexed analog output @ 5MHz

• SCA= multiple S&HDepth = 16Droop < 1 mV/msHold signal generated internally with

adjustable delay28.09.2009 Waclaw Karpinski 38

Slow Shaper

Depth 16

Analog memory

y = 2,8821x + 13,401

R2 = 0,9997

0

50

100

150

200

250

0 10 20 30 40 50 60 70

DTC code

de

lay

(n

s)

Waclaw Karpinski 39

ILC beam structure

28.09.2009

Acquisition

1ms (.5%)

A/D conv..5ms (.25%)

DAQ.5ms (.25%)

1% duty cycle

IDLE MODE

99% idle cycle

199ms (99%)

time

Time between two trains: 200ms (5 Hz)

Time between two bunch crossing: 337 ns

Train length 2820 bunch X (950 µs)

Two orders of magnitude saved on the power consumption

Acquisition A/D conversion DAQ

When an event occurs :• Charge is stored in

analogue memory• Time is stored in

digital (Bunch crossing ID) memory

• Trigger is automatically rearmed at next bunch crossing ID

Depht of memory is 16

The data (charge) stored in the analogue memory are sequentially converted in digital and stored in a SRAM.An event in RAM is :• The Bunch Crossing

ID• The charge• The shaper gain• The status of the

trigger

The events stored in the RAM are outputted through a serial link when the chip gets the token allowing the data transmission.When the transmission is done, the token is transferred to the next chip.256 chips can be read out through one serial link

Waclaw Karpinski 40

Read out : token ring

28.09.2009

Acquisition A/D conv. DAQ IDLE MODEChip 0

Chip 1 Acquisition A/D conv. DAQ IDLE MODEIDLE

Chip 2 Acquisition A/D conv. IDLE MODEIDLE

Chip 3 Acquisition A/D conv. IDLE MODEIDLE

Chip 4 Acquisition A/D conv. IDLE MODEIDLE DAQ

Chip 0 Chip 1 Chip 2 Chip 3 Chip 4

5 ev

ents

3 ev

ents

0 ev

ent

1 ev

ent

0 ev

ent

Data bus

spiroc readout for pebs

Documents

gain ranges

c gain

spiroc output low gain

range gain adjustable

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ff spiroc

bunch x