solving ai problems with memristors a case study for optimal...

18th Panhellenic Conference on Informatics

Harokopio University Greek Computer Society

Special Session on

Hardware Design Tools and Technologies

Solving AI problems with memristors

A case study for optimal “bin packing”

Democritus University of Thrace School of Engineering

Department of Electrical & Computer Engineering Section of Electronics & Information Systems’ Technology

Laboratory of Electronics

D. Stathis, I. Vourkas, and G. Ch. Sirakoulis

Athens, October 2-4

02/10/2014 Georgios Ch. Sirakoulis - Associate Professor at Democritus Univ. of Thrace 2

Presentation Outline 1. Background

•Definition of the bin packing problem •Basics of Cellular Automata in brief •Memristor-the 4th fundamental circuit element: basic properties

2. Memristor-based bin packing •Algorithm description •Circuit-level implementation •CA considerations

3. Simulation results •Scenario description •Verification of the circuit design through simulation

4. Conclusions & Remarks


The “bin packing” problem

“Bin Packing” is a classic problem where a collection of objects of different volumes must

be packed into a finite number of fixed-size containers (bins)

Pack everything into as few bins

as possible

It is a combinatorial NP-hard problem with many variations (e.g. linear, 2D, or 3D packing) which find application in several every-day practical problems • Optimal solutions can be produced with

heuristic algorithms • “First-Fit” approximation algorithm provides a fast solution

• Required time complexity is O(nlogn), where n is the number of elements to be packed

• In real applications the sizes to be packed may all be known in advance … • Better results are achieved by packing the largest objects first • “First-Fit decreasing” algorithm

The focus of this presentation is on the optimal solution of NP-hard AI problems via a novel circuit-level approach which we first prove for “Bin Packing”


Basics of Cellular Automata

A CA requires: • A regular lattice of cells covering a

portion of a d-dimensional space; • A set c(r,t)={c1(r,t), c2(r,t),…,cm(r,t)} of

Boolean variables attached to each site r of the lattice giving the local cell’s state at the time t;

• A rule R={R1, R2, …, Rm} which specifies the time evolution of the states c(r,t)

• The neighborhood of cell r • Boundary conditions

Evolution rule

Next state

Other cell states

Current state

CA are models of physical systems where space and time are discrete and interactions are local

1-D Vs. 2-D

cj(r, t+1) = Rj(c(r, t), … c(r+δq, t)) r + δκ : the cells belonging to a given

neighborhood of cell r


CA Properties & Capabilities

They have found successful application in several real computational problems

CA have sufficient expressive dynamics to represent phenomena of arbitrary complexity • Memory (i.e. cell’s state) and processing

unit (i.e. local rule) are inseparably related to a CA cell

• Emergent computation : global behavior emerging from the collective effect of simple and locally interactive components

When CA-based models are implemented in hardware (HW)… • Circuit design reduces to the design of a

single cell and the overall layout results regular

• The models are executed fast by exploiting the parallelism of the CA

CA constitute an inherently massively parallel computing paradigm of high efficiency and robustness

Memristor: the 4th Element


Memory resistors – MEMRISTORS

• Originally postulated by Leon Chua in 1971

• The discovery of the first “modern” memristor by HP Labs in 2008 has drawn great attention of both academia and industry

• To date, memristor represents a technology breakthrough which creates new opportunities for realization of innovative circuits

• Applications: Non-volatile memory, adaptive filters, signal processing, Logic/computing, …


Threshold-based Memristive Dynamics

I. Vourkas, and G. Ch. Sirakoulis, “A Novel Design and Modeling Paradigm for Memristor-based Crossbar Circuits,” IEEE Trans. Nanotechnol., vol. 11, no. 6, pp. 1151-1159, Nov. 2012

Commonly observed I-V types

Threshold-based Model Response

Device variability


Composite memristive dynamics A positive/negative voltage applied to the top terminal with respect to the bottom terminal (denoted by the black thick

line) tends to decrease/increase the memristance GOFF

GON

G. Papandroulidakis, I. Vourkas, N. Vasileiadis, and G. Ch. Sirakoulis, “Boolean Logic Operations and Computing Circuits Based on Memristors,” IEEE Trans. Circ. Syst. II, Exp. Briefs (2014), in press

Fine-resolution multi-state switches • When n identical memristors of the same

polarity are connected in parallel, the overall conductance range is n × [GON, GOFF]

• Connecting n such parallel groups in series increases the cumulative voltage threshold n × while maintains the range of the total conductance equal to (1/n) × (n × [GON, GOFF]) = [GON, GOFF]


Memristor-based “bin packing” General setup of the circuit which sequentially implements the “First Fit”

The 2-d array consists of a “chain” of vertically-placed 1-d CA arrays representing separate equally-sized bins

Main properties: • The CA neighborhood of the ith cell in each

bin includes the top and bottom adjacent cells

• Fixed boundary conditions are applied to the last cells of every 1-d CA to denote the bottom

• All the1-d CA are identical and the total number of their cells equals bin_size+1

• Each new packet is introduced to the array from the top cell of the first bin

• The top cells of the rest of the bins do not receive inputs directly from outside


Algorithm description Flow chart showing the work flow during the bin-packing

For every recently introduced packet all bins function as 1-d CA under a common evolution rule which consists of three phases: set, reset, and read • A new packet enters only when the previous packet is packed • The entire system stops only when all packets are packed • The parameters which characterize the state of the ith CA cell at time moment t are:

• Packet_Size_on_Grid (PSoGit): size of the assigned packet

• Space_Used (SUit): total utilized space inside the bin

• Switch (SWit): flag which can be either ‘1’ or ‘0’


Algorithm description (2) Comments: All cells initially have {PSoG, SU, SW} = ‘0’. Every new packet … 1. puts its size to the PSoG parameter of the

top cell of the leftmost bin 2. moves along each bin until it finally

settles in an empty cell 3. Whenever another packet is in the cell

below it, it checks if there is enough space left in this bin by consulting the SU parameter of the next cell

• If it fits in the bin it remains in the current position and updates its SU

• if it does not fit in the bin it continues the search in the next bin

• If the packet reaches the last cell of a bin is settles there and updates its SU

• All cells along the bottom boundary receive constant inputs from below.


Circuit-level implementation: Set stage In this stage of the rule the new state of

the cell is computed

• PSoG and SU values are encoded in the state of two multi-state switches

• The three parallel devices have VSET,1 < VSET,2 < VSET,3 but equal memristance ranges [RON, ROFF]

• A voltage whose amplitude falls between VSET,1 and VSET,2 sets device 1 in RON. If between VSET,2 and VSET,3 it switches device 1 & 2 to RON, etc.

• A single memristor is used for the SW flag.

• Three current-controlled DC voltage sources are used to store the next state of the cell, both for internal use as well as to define cell’s output.

• A voltage adder and three switches are used to define the voltage that will be applied to each composite device, according to the current state and the states of the adjacent cells

• A comparator is used to check if there is enough space inside the particular bin for the current packet.


Circuit-level implementation: Reset stage In this stage all the memristors inside

the cell are reset (i.e. set to ROFF)

• Since gradual resetting is not important, we assume a common negative threshold for all memristors, i.e. VRESET.

• This stage consists in the “conditional” application of a single negative voltage pulse of appropriate amplitude above |VRESET | to the multi-threshold devices in order to reset the state of all memristors.

• The application of such voltage is controlled by three switches which operate according to the CA rule.


Circuit-level implementation: Read stage The read stage is when the recently

calculated state of the cell is stored and the outputs of the cell are defined

• The state of the composite devices is read by applying a positive voltage VREAD of low amplitude which does not exceed any of the thresholds

• For each composite device there is a current-to-voltage converter whose external gain is modified according to the state of the memristors

• The output of the converter will be approximately given by n×VREAD, where n is the number of memristors that are in RON

• Each cell state parameter is related to a corresponding DC voltage source and all of them are adjusted accordingly to hold the next cell state which is also its output

• Flag SW is read via a voltage divider using a series resistor; its value defines whether or not the PSoG value will be passed to the top of the next bin

• Overall four simulations took place for a particular set of ten packets of various sizes and ten bins when the packets are processed either (a) in arbitrary or (b) descending order.

• In our simulations we used a threshold-type model of a voltage-controlled memristor

• The number of parallel memristors in the composite devices was selected in order to have maximum packet size of three units and maximum bin size of either three or four units.

• Depending on the state of the memristors, the applied read voltage produces four different voltage levels via the inverting amplifiers

• The duration of the set and the reset stage was selected after experimentation with the memristor model and is enough for the memristors to completely switch their states.


Simulation Scenario Details


Simulation Results

• Colors {R, G, B} correspond to {3, 2, 1} packet sizes • Bin capacity: three units • Both results are nearly-optimal resulting in the same number of used bins • Starting with the largest objects first leads to better utilization of the available space!


Simulation Results (2)

• Colors {R, G, B} correspond to {3, 2, 1} packet sizes • Increased Bin capacity: four units • The impact of the sorting process: one less bin occupied while the total space utilization is better • Increasing the bin capacity significantly lowers the necessary computational time when

the candidate packets are sorted, whereas it has no significant effect for mixed entries.

Concluding Remarks


This work presented a Cellular Automata (CA)-inspired circuit-level early approach to the solution of the classic “bin packing” problem (BPP) capable of executing computation within memory using memristors and memristive compositions The First Fit algorithm does not require knowledge of the state of all the bins but instead it only locally examines each bin which is in line with the CA definition One of the advantages of this approach is that it is a hardware implementation of the known algorithm which uses the memristor as its basic memory element Using composite multi-threshold memristive devices enables tuning their conductance in a robust manner exploiting their threshold-type switching behavior. Then the state of the devices can easily be read through an inverting op. amp. that is used as a variable gain amplifier. Future work… Architectural improvements and modifications to the algorithm which will facilitate parallel processing of the candidate packets, leading to faster computations compared to published 1-d BPP benchmark data sets and classic CA designs

End of presentation

Thank you!

Questions ???

Georgios Ch. Sirakoulis Associate Professor

Democritus University of Thrace Dept. of Electrical and Computer Engineering

http://gsirak.ee.duth.gr


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