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Digital mixer with current steering DAC Cătălin BRÎNZEI, Florin CONSTANTINESCU, Iulian URSAC

“Politehnica”University Bucharest, Spl. Independenţei 313, 060042,Romania

Abstract. A new approach of a fully differential transmitter for a multi-standard communication system is proposed in this paper. The main components consist of a digital multiplier combined with a DAC (digital-to-analog converter). This architecture has some important advantages given by the digital blocks such as the low power consumption, speedy operation, robustness and portability over a wide range of technologies.

1 Introduction

A frequency mixer combined with a DAC (digital-to-analog converter) is proposed and it is the main component of an almost all digital transmitter chain. The operands or signals in binary format which need to be multiplied are computed on the DSP level (base band) and are sent to a Wallace tree digital multiplier [1]. The output of the digital frequency mixer is an eight bit word and represents the multiplication of the input signals. The digital-to-analog converter uses as input the output of the digital multiplier and generates an analog voltage corresponding to the digital word. The main up-conversion at high frequency is performed by using a quadrature modulation employing two mixers. These two I and Q mixers are driven by a LO (Local Oscillator) signal and are embedded in the output of the current steering DAC and also share the same biasing current minimizing in this way the power consumption.

2 Block diagram and principle of operation

The most important advantages of this architecture are the low power consumption and low SFDR (Spurious Free Dynamic Range) which is around 67dB. The proposed mixer achieves a high spectral purity by using a minimal analog circuitry in the output represented by an optimized DAC. Because of this hybrid implementation, this circuit can be easily implemented in a digital CMOS technology enabling a low voltage and low power architecture.

Figure 1: Transmitter chain using a digital mixer and DAC, block diagram.

The performance of the entire chain is limited by the performance of the analog part so the

DAC will play an important role for this architecture. The chosen DAC topology is a segmented one and it is actually a hybrid between the binary weighted topology and the thermometric encoded topology. The most significant (MSB) five bits are thermometric coded since the variation of the

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current is significant and the other least significant three bits (LSB) are binary weighted coded since the variation of the current is smaller.

This architecture is preferred since it exhibits a good linearity looking to the static parameters, even if we encounter large process variations on wafer. The second advantage is the low area consumed on the die lowering the production cost. The optimum segmentation number showing a good linearity has been proved to be between four and seven [2]. We chose a five plus three segmented architecture (five thermometric coded bits and three binary weighted bits) so the converter has eight bits. Basically a current steering DAC is based on an array of matched current sources and the input digital word is divided in five MSB which control thirty-one unary weighted current sources using a binary to thermometer decoder and three LSB bits which control the binary weighted current sources.

The current cells are properly biased using simple current mirrors and it is expected to use a supply which has a low voltage drop. These kinds of supply blocks are usually present on mobile communication platforms and because of this the biasing schematic is relaxed for our digital mixer with DAC. The current cell consists in a simple open drain differential pair which is biased using a cascoded current source. The utilization of the cascodes is mandatory since the DAC‘s output impedance depends on the output impedance of the current source and this should be as high as possible to minimize the errors in the output.

Figure 2: DAC current cell

The basic current cell consists of a cascoded current mirror (transistor NM0) which is connected to the resistive output load using MOS switches (transistors NM3 and NM7). The transistor NM0 is stacked over another current source transistor which is placed on biasing block of the proposed DAC. The C input of the current cell represents a current input and that connection is routed from the current cell up to the biasing block location. Since the principle of the biasing current transfer is implemented, the effects of parasitics extracted from the layout of each cell is minimized and the design becomes more robust. For example the output impedance of the current source which is high from the biasing block will be in series with the parasitic resistance of the wire which is quite low and it gives an overall impedance where the output impedance of the current source is the dominant factor. For synchronization purposes a flip-flop is used which drives the MOS switches [4]. Since the thermometric coded unary current sources occupy a significant area on chip it is possible that, due to different lengths for routing, the commutation timing of the switches varies randomly and because of this a clocked latch (differential flip-flop –dff) is implemented near the switches. The commutation decision is made on the positive edge of the clock (CK) signal which represents actually the DAC update frequency. The current reference generated on the biasing side is chosen to be 20uA and is doubled by the M0 transistor (Fig. 3) and

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used as biasing for DAC’s current cells. The 40uA current is the value of a unary current cell controled by the MSB side of the DAC which uses a thermometric decoder.

3 Power consumption and W/L sizes of the current sources and switches

For the architectures using steering MOS current sources the power consumption is given mainly by the analog part and hence by the sum of all thirty one unit current sources. The analytical expression of the power consumption is given below:

(2 1)* * 25nPtotal I VD= − (1) The index n represents the total number of bits which is eight in this case. I shows the unit current source value of 40uA for the unary MSB and 5uA for the binary weighted LSB. VD25 is the voltage supply of the analog part.

Figure 3: Biasing block

The maximum power consumption is determined by:

255*5 *2.5 1275 *2.5 3.18Ptotal uA uA V mW= = = (2)

Considering the process parameter given by the technology being 2* 320 /nK Cox uA Vμ= = results that the form factor W/L of the current source is

approximatively around four. For a channel length of L=450nm results a W of 2um. Using the transistor equation in saturation, the analytical sizing method is given below:

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* * *( ) ; 0.5; 2002

2** 320 / ; 40 ; ~ 4*( )

GS TH GS TH

GS TH

Cox WI V V V V mVL

W IK Cox uA V I uAL K V V

μ

μ

= − = =

= = = = =−

(3)

The drain-source resistance of the switch is calculated for the transistor in triode region:

11 ( )2

DSGS TH

I Rout WV Cox V VL

μ

∂= =

∂ − (4)

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Due to speed requirements a minimum value for L (120nm) should be considered but W cannot be too high since this will increase the parasitic capacitance and errors due to the charge injection in the output will increase [3]. It has been appreciated that 2um is a good choice for the width of the MOS switch. The output current needs to charge and discharge the load capacitor from the output of the DAC, which is relatively big considering that all the basic current cells are summed in the output and the parasitic capacitor is significant. The estimated total capacitor value in the output node is 2.5pF and the needed current to charge and discharge it is determined by:

* , 1.275 , 2.5 , 1.3

* 2.54 393MAX

VI C I mA C pF V VT

V CT nS Freq MHzI

Δ= = = Δ =

ΔΔ

Δ = = − > = (5)

It can be determined that the maximum operation speed is 393MHz when the load resistance is 500Ω. The operation speed can be increased by the future implementation of the concept of RF DAC which means that an additional up conversion mixer, which employs the same biasing current as the main DAC, is placed in the output.

4 Simulation results

DAC transfer function All possible digital codes to the input of the DAC have been successively applied and the analog

voltage has been determined at the output.

Figure 4: DAC Output with and without binary weighted bits active

Static performance parameters INL and DNL

The most important static error parameters for a DAC are the INL („Integral Non Linearity”) and DNL („Differential Non Linearity”) and have been computed based on the simulations results obtained with SPECTRE.

A Spurious Free Dynamic Range of 67dB has been obtained while using a maximum current consumption Imax of 1.275mA. The maximum power consumption Pmax is 3.18mW and the DNL and INL are 0.41 LSB and 0.48 LSB respectively.

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Figure 5: INL, DNL and transfer function for a segmented DAC

Digital multiplier

The schematic of the digital multiplier implemented with CMOS gates is given below and represents a detail of the digital mixer block shown in Figure 1.

Figure 6: Digital multiplier

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Output spectrum for the digital mixer

Figure 7:Output spectrum

5 Conclusions

The working frequency for the proposed implementation is estimated (up to 400MHz) as much higher than that reported in [5]. The output bandwidth may increase to cover more standards like GSM, Bluetooth if a RF DAC is implemented in the output. The shown architecture has some common aspects with some low speed architectures described

in literature but those were not used for the transmission chain at high frequency. An important contribution consists by using of some special techniques in design to overcome the effect of the parasitics from layout. The SFDR parameter which is 67 dB shows a good spectral purity for the proposed architecture

and if we compare to [5] where an SFDR of 52dB is reported we can conclude that this solution is suitable for GSM and blootooth applications. Static parameters INL=0.48LSB and DNL=0.41LSB are showing good performances. The performances shown above including the low power consumption due to the use of the

digital circuitry are very attractive and we can predict that the analog mixing will be replaced soon by the digital one in all consumer electronic devices. References [1] N. Rahman, R. Yun, 8x8 Booth-Encoded Wallace Tree Multiplier, Tufts University, Dept.of

Electrical and Computer Engineering, 2011. [2] Hugo Hernandez, Wilhelmus Van Noije, Elkim Roa, Design strategy of current source in current

steering, Integrable Systems Laboratory – Polytechnic School of San Paulo University, 2011. [3] Jacob Wikcner, Studies on CMOS digital-to-analog converters, Linköping Studies in Science and

Technology, 2001. [4] Sam Blackman, A Low Power, 8-bit, 200 MHz Digital-to-Analog Converter, College of Engineering

University of California, Berkeley, 1999. [5] P. Sotiriadis, W. Ling, Almost All-Digital Sinewave-Product Generation for Frequency Synthesis

Applications, Frequency Control Symposium, Joint with the 22nd European Frequency and Time forum. IEEE International, 2009.