small signal amplifiers - bjt · 2013-11-12 · small signal condition when the input signal (v in...
TRANSCRIPT
Small Signal Amplifiers - BJT
Definitions
Small Signal Amplifiers
Dimensioning of capacitors
1
Small signal condition
When the input signal (vin and, iin) is small so that output signal (vout and,
iout) is confined in the active region of the output characteristics of the device,
the device is operating in a condition of small signal.
More specifically, the condition of small signal are verified when the variations in
output are so small that the parameter values of the device can be regarded as
constant.
In these conditions, the amplifiers can be analyzed using the small-signal
models of the BJT. The small signal conditions occur, in general, for the first
stages constituting an amplification system.
Linearity
In conditions of the small signal, the amplifier can be considered linear. The
output signal is proportional to the input signal. This property derives from
the fact that the components of the circuit are described by linear equations.
If the system is linear applies the principle of superposition.
Amplitude and phase distortion
So that a waveform is not altered across the amplifier is necessary that each of
its sinusoidal component is equally modified in amplitude and phase.
Definitions (1)
2
Transfer function or network function
Complex function that describes the relationship between the output signal and the input
signal. It is defined in the Laplace domain (s) or in the frequency domain (s = jw)
Amplitude and phase response
Real functions obtained by specifying amplitude and phase of the transfer function with s = jw.
Describe the variation of modulus and phase when the frequency changes.
Gain and phase shift of an amplifier
In the case of an amplifier transfer function is also called amplification (or gain) and can be
expressed in magnitude and phase. Relatively to the various electrical quantities considered for
entry and exit there are various definitions of gain
Definitions (2)
;L
v
in
VA
VVoltage
amplification
;L
i
in
IA
I
Current
amplification
;L
G
in
IA
VTransconductance
amplification
;L
R
in
VA
I
Transresistance
amplification
RL Vs
RS IL
+
Vin
-
Iin
+
VL
-
3
;out
out
out
VZ
I
Output Impedance
It is the impedance viewed from the output port. This impedance can be interpreted as
the Thevenin impedance at the output port.
;in
in
in
VZ
I
Input impedance
It is the impedance viewed by the source of the input signal.
Definitions (3)
RL Vs
RS IL
+
Vin
-
Zin
Iin
+
VL
-
RS Iout
+
Vout
-
Zout
4
BJT
VCC
R 1
R 2
R C
Rs
Vs
C1
R E
+
Vin
-
+ V L -
C2
R L
BJT
VCC
R 1
R 2
Rs
Vs
C1
R E
+
Vin
-
+
VL
-
C2
RL
BJT
VCC
R1
R C
Rs
Vs
C1
R E
+
Vin
-
+
V L
-
C2
RL
C3
R2
Common Collecttor Conf. Common Base Conf.. Common Emitter Conf.
Three configurations can be considered
Definitions (4)
CBC CEC CCC
Av
Ai
Rin
Rout
1
fe C L C L
Eie fe E
h R // R R // R
Rh h R
1 P ie fe E PR // h h R R
CR
inv
L
RA
R
1
1
1fe E L
ie fe E L
h R // R
h h R // R
1P ie fe E L PR // h h R // R R
in inv
L L
R RA
R R
1
ie P SE
fe
h R // R
h
R //
//fe
C L
ie
hR R
h
CR
//1
ieE
fe
hR
h
1
fein Cv
L C L fe
hR RA
R R R h
1 2PR R // R
Electronics: a systems approach by N. Storey 5
hfeib ib
hie
vout
R1//
R2
+
-
vin
+
-
RE
RC//
RL
hfeib ib
hie
vout
R1//
R2
+
-
vin +
-
RC
RE//
RL
hfeib ib
hie
vout +
-
vin
+
-
RE
RC//
RL
Common Base C.
Common Emitter C.
Common Collecttor C.
Definitions (5)
6
7
hfeib ib
hie
vce
+
- vbe
+
- vout
R2
+
-
vin
+
-
RE
RC
RL
R1
The voltage supply (VCC) for the signal
is equivalent to a short circuit
Capacitors in the mid-band
are equivalent to a short
circuit
hfeib ib
hie
vout
R1//
R2
+
-
vin
+
-
RE
RC//
RL
equivalent
circuit
1 2 1 21
1
in ie fe E P
out b fe C L in b ie fe E
R R // R // h h R R // R R
v i h R // R v i h h R
1
fe C L C Loutv
in Eie fe E
h R // R R // RvA
v Rh h R
1out inLi v
inin C L C L
in
v RiA A
vi R // R R // R
R
Common Emitter C.
8
hfeib ib
hie
vce
+
- vbe
+
-
vout
R2
+
-
vin
+
- RE
RC
RL
R1
The voltage supply (VCC)
for the signal is equivalent
to a short circuit
Capacitors in the mid-band
are equivalent to a short
circuit
equivalent
circuit
1 2 1 21
1 1
in ie fe E L P
out b fe C L in b ie fe C L
R R // R // h h R // R R // R R
v i h R // R v i h h R // R
1out in inLi v
inin C L C L C L
in
v R RiA A
vi R // R R // R R // R
R
Common Collettor C.
hfeib ib
hie
vout
R1//
R2
+
-
vin +
-
RC
RE//
RL
1
1
1fe E Lout
v
in ie fe E L
h R // R
h h R // R
vA
v
Coupling capacitor
The amplifier is used to provide voltage and current levels adequate to drive the
load connected to the output. The use of a single BJT is sometimes not sufficient
to achieve this result.
This limitation can be overcome by connecting in cascade several amplifiers,
so that the signal emitted by the source is increased by each amplifier constituting
the cascade. Each individual amplifier is called stage.
• Capacitors are used to connect one stage to another, they are referred coupling
capacitors.
• The coupling capacitors have the function of providing insulation in DC so that
the bias of one stage does not affect that of the next stage.
• These capacitors have to pass the AC signal from one stage to another with
minimum distortion.
Definitions (6)
+
VL
-
RL
IL
Zout
Vs
RS
+
Vin
-
Zin
Iin
9
Gain variation with frequency
Because of the introduced reactive elements and the parasitic reactive
elements the response of the amplifier is function of frequency.
By-pass capacitors
These capacitors are connected in parallel to a resistor, so AC signals on the
resistor are short circuited. In this way the AC and DC circuits are different.
1
fe C L
V
ie fe E
h R // RA
h h R
fe C L
V
ie
h R // RA
h
Definitions (7)
BJ
T
RE C3
BJ
T
Re
R3
C3
BJT
R 3
R E
C3
For example, in the case of CEC, a by-
pass capacitor on RE allows to obtain a
higher voltage gain.
For the capacitor by-pass the following configurations can be used :
10
Freq.
Freq.
Mid-band • To simplify the study, it is useful to assume that there is a range of frequencies
(bandwidth) in which all the reactive effects are negligible.
• Therefore in this range, gain (A0), input and output impedances are real quantities (Rin Rout).
• Three different frequency ranges (low, medium and high frequencies) can be considered.
• Three different frequency ranges correspond to three different dynamic circuits.
0l u
AA f A f
2
l u 0 dBdB dBA f A f A 3dB
Electronics: a systems approach by N. Storey (13.7)
Cut-off frequencies
The mid-band is delimited by two frequencies, the
lower cut-off frequency fl (determined by coupling
and by-pass capacitors) and the upper cut-off
frequency fu (determined by the junction capacitance
and the parasitic effects).
The cutoff frequencies are defined by:
Definitions (8)
11
( );
0
L in LL Lj jL
v
in in in
in
V VVA e e
V V V
Mid-band
;
;
L
v
in
L
v
in
VA
V
VA
V
Common Emitter C.
Common Collector C.
Definitions (9)
12
RL
IL
+
Vin
-
Zin
Iin
+
VL
-
Zout
Vs RS
Observation
• When the small signal conditions are verified the bias conditions are not
influenced by signals present, and the full analysis can be divided into two
sub-analysis: DC and AC.
• The AC analysis is often made by assuming the existence of the intermediate
band and analyzing the circuit in this band, where the reactive effects can be
neglected.
• Therefore, it is important to know the cutoff frequencies that define the mid-band.
Syntesis of a small signal stage
In general, a synthesis process, without the computer aid is carried out taking
into account the behavior of the circuit in DC and in AC and estimating the effect of
the capacitors on the cut-off frequencies. At last, the synthesis, of a stage which
works at small signal, can be realized in the following steps:
1. Synthesis of the bias network.
2. Change of the bias network to meet the design specifications.
3. Choice of the capacitors to obtain the request lower cutoff frequency.
Definitions (10)
13
Small signal amplifiers
14
common collector stage
To design an amplifier, that by means of a suitable RL value, ensure a specific
current gain and voltage amplification equal to one.
The circuit solution is the:
LI
in
IA
I
1. Synthesize the bias network (R1, R2, RE) .
2. Select the RL value which ensures the desired current gain.
3. Choose the appropriate values for C1 and C2 which ensure the lower cutoff
frequency given in the project specifications.
Synthesis steps
BJT
R2
R1
RL
C1
C2
Vs
RS
VCC
Iin
IL
RE
+
Vin
-
+
VL
-
15
Bias network for the CCC 3 resistors
3 relations
BJT
VCC
R1
R2 VE
VB
RE
Rbase
1 2
21// 2 ( ) ( )
1 2CC BQ BEQ E BEQ E
CC BEQ E
BEQ E
RV R R I V V V V
R R
V V VR R
V V
I2
Synthesis of bias network for the CCC
Synthesis steps: 1
16
( )CC CE E CQ BQV V R I I 1)
2
2
2
2
10 10
1
10 10
11 R
10
1R
10
CQ CQ
BQ BQ
FE FE
BEQbase E
BQ BQ
BEQ
FE E
BQ
FE E
I II I I
h h
VR VR
I I
Vh
I
I
R h
2)
3)
CC CEQ
E
C
V VR
I
2
2
2
1
10
10
FE E
BE E BE EFE
C
R h R
V V V VR h
I I
1 2
CC BEQ E
BEQ E
V V VR R
V V
3) RE is obtained by:
4) R2 is obtained by:
5) R1 is obtained by:
Synthesis steps of bias network:
Synthesis steps: 1
1) Choose the supply voltage VCC and the transistor working point: IC, VCE.
2) From the datasheet VBEon and hFE values can be obtained.
18
VBEon =0.66 V
hFE =210
20 101
10
V Vk
mA
2
210 121 15
10
kk R k
Or:
1
9 3415 13 12
10 66
.k k R k
.
RL is obtained by the circuit analysis.
Synthesis steps: 2
1 21 2
1 2
1 1 1 1
P
P E Lfein
I V
L L L I P E Lfe
R RR R // R
R R
R // hie h R // RRA A
R R R A R h R // R
1 1E L
fe
L I P E L
R Rh
R A R R R
1
1L
fe
E
I
fe
E
P
R
R
R
h
A
h
R
1
L
fe P
I fe
Rh R
A h
L
P
I
RR
A
If hfeRE>>RP or hfeRE> 10RP
If hfeRE> 10RP and hfe>10AI
19
6 666 6 8680
10 10L
R. k . k
To perform the AI and Rin measurements :
; RT Lin L
T L
V VI I
R R
Mount the circuit introducing a test resistor RT
Measure VRT (using two probes)
Calculate Iin and IL
Calculate AI
Calculate Rin
1 2 6 8TR R // R . k
LI
in
IA
I
inin
in
VR
I
BJT
R2
R1
RL
C1
C2
Vs
RS
VCC
Iin
IL
RE
RT +
Vin
-
+ VRT -
+
VL
-
20
common emitter stage
To design a stage which ensures, in the passband, the desired voltage
amplification.
If the load can be selected a possible solution is the:
LV
in
VA
V
BJT
VCC
R 1
R 2
R C
Rs
Vs
C1
R E
C3
+
Vin
-
+
V L
-
C2
R L
1. Synthesize the bias network (R1, R2, RC, RE) .
2. Select the RL value which ensures the voltage gain desired.
3. Choose the appropriate values for C1, C2 and C3 (C3 >> C1 and C2) which
ensure the lower cutoff frequency given in the project specifications
Synthesis steps
21
Synthesis of bias network for the CEC (and CBC)
4 resistors 4 relations
BJT
VCC
R1
R2
Rc
VE
RE
VB
Rbase
ICQ
2
2
2
2
10 10
11 R
10 10
1R
10
CQ CQ
BQ BQ
FE FE
BEQbase
FE E
BQ
FE E
I II I I
h h
VRR h
I
I
R h
I2
Synthesis steps: 1
22
( )CC C C CEQ E CQ BQV R I V R I I
10 20
CC
E
VV
1 2
21// 2 ( ) ( )
1 2CC BQ BEQ E BEQ E
CC BEQ E
BEQ E
RV R R I V V V V
R R
V V VR R
V V
1)
2)
3)
4)
2
2
2
1
10
10
FE E
BE E BE EFE
C
R h R
V V V VR h
I I
1 2
CC BEQ E
BEQ E
V V VR R
V V
3) RE is obtained by:
4) R2 is obtained by:
5) R1 is obtained by:
Synthesis steps of bias network:
Synthesis steps: 1
1) Choose the supply voltage VCC and the transistor working point: IC, VCE.
2) From the datasheet VBEon and hFE values can be obtained.
24
VBEon =0.66 V
hFE =210
1100
10
V
mA
2
210 1002 1 1 8
10. k R . k
Or:
1
18 441 8 20 22
1 66
.. k k R k
.
20
CCEE
CQ CQ
VVR
I I
CC CEQ E
C
CQ
V V VR
I
4) RC is obtained by:
9900
10
V
mA 820CR
hie
R1//R2
ib ib hfe
Vs
RS
ii
RL
1 1
fe C L fe
V
ie L ie V C
h R // R hA
h R h A R
BJT
VCC
R 1
R 2
R C
Rs
Vs
C1
R E
C3
+
Vin
-
+ V L -
C2
R L
RL is obtained by circuit analysis.
Synthesis steps: 2
25
common emitter stage with
emitter degeneration
To design a stage to ensure, in the passband, a voltage amplification
If the load is fixed a possible solution is the:
LV
in
VA
V
1. Synthesize the bias network (R1, R2, RC, RE). Same approach of the CEC.
2. Select the R3 value.
3. Choose the appropriate values for C1, C2 and C3 (C3 >> C1 and C2) which
ensure the lower cutoff frequency given in the project specifications.
Synthesis steps
BJT
VCC
R 1
R 2
R C
R 3
Rs
Vs
C1
R E
C3 +
Vin
-
+
V L
-
C2
R L
The emitter resistor is replaced with
RE//Series (C3-R3) to obtain different
impedance values in DC and AC.
26
hie
R1//R2
ib ib hfe
RE//R3 Vs
RS
ii
RL
BJT
VCC
R 1
R 2
R C
R 3
Rs
Vs
C1
R E
C3 +
Vin
-
+ V L -
C2
R L
3
3 3 33
3
1
1
1 1
fe C L VC L EV
E C L E Eie fe E
V
C L E
h R // R AR // R R RA
R // R R // R R // R R Rh h R // R
A
R R // R R
Synthesis steps: 2
27
1
3
1 10 10 0132 0 01 0 0032
758 100. - . .
R
3 330R