single fiber optical io on standard 0.35 um cmos

5

Single Fiber Optical IO on standard 0.35 um CMOS Nan Marie Jokerst Martin A. Brooke Duke University Department of Electrical and Computer Engineering email: [email protected]

Upload: livingston-aron

Post on 03-Jan-2016

19 views

Category:

Documents

2 download

Report

Download

Tags:

Embed Size (px):

DESCRIPTION

Single Fiber Optical IO on standard 0.35 um CMOS. Nan Marie Jokerst Martin A. Brooke Duke University Department of Electrical and Computer Engineering email: [email protected]. Home Interface Implementation Using a Single Fiber Bi-Directional Fiber Link. - PowerPoint PPT Presentation

TRANSCRIPT

Page 1: Single Fiber Optical IO on standard 0.35 um CMOS

Single Fiber Optical IO on standard 0.35 um CMOS

Nan Marie JokerstMartin A. Brooke

Duke UniversityDepartment of Electrical and Computer Engineering

email: [email protected]

Page 2: Single Fiber Optical IO on standard 0.35 um CMOS

HUB

Asymmetric or symmetricbandwidth link in each direction

Home Interface

Emitter stacked on top ofdetector for bi-directional link

•Co-located, stacked thin film emitters and detectors for bi-directional interface

•Single fiber between the hub and home

•Alignment tolerant for low cost packaging

Si CMOS Receiver and Transmitter Circuits

Thin film emitterThin filmdetector

Optical fiber

Previousresult for co-locatedemitter/detector pair

Home Interface Implementation Using a Single Fiber Bi-Directional Fiber Link

Page 3: Single Fiber Optical IO on standard 0.35 um CMOS

Si CMOS Rxand Tx Circuits

Thin film emitterThin filmdetector

Optical fiber

• The co-location of the emitter and detector enables single fiber bi-directional communication

• For asymmetric, low cost interconnection, detector

will run at 1 Gbps, and LED emitter at ~100 Mbps.

For faster emitter, edge emitter and mirror will be

used.

Co-Located Emitter and Photodetectorfor Single Fiber Bi-Directional Link

Page 4: Single Fiber Optical IO on standard 0.35 um CMOS

Transceiver: Laser Driver and TIA

RCE InGaAs LED50 m diameter with 30m aperture

I-MSM GaAs PD 150 m detector diameter

Page 5: Single Fiber Optical IO on standard 0.35 um CMOS

Measurements from Circuit With Integrated Stacked Devices

I-MSM photoreceiver eye diagram at 1Gbps

RCE LED optical transmitter eye-diagram at 40 Mbps (LEDs are slow)

ECE680: Physical VLSI DesignQli/ECE680/Chapter7 timing issue.pdf600 MHz – 0.35 micron CMOS t cycle = 1.67ns 600 MHz 0.35 micron CMOS t rise = 0.35ns t skew = 50ps Global clock waveform

The following are the bank’s service fees which are ... · Online Dispute $50* Online Transaction $0.35* ATM Transaction $0.35* Eftpos Transaction $0.35* EVERYDAY CARD BSP Eftpos

HIGH SPEED LVDS DIGITAL INPUT/OUTPUT …etd.lib.metu.edu.tr/upload/12618525/index.pdf · LVDS test çipi 0.35 µm CMOS teknolojisiyle üretildi. Çipin içinde iki tane verici, bir

250 MHz CMOS Rail-to-Rail IO OpAmp - MiXeDsIgNaL · PDF file250 MHz CMOS Rail -to-Rail IO OpAmp: ... At least 2 common-source gain stages in rail-to-rail IO ... Folded cascode circuit

A Single-Inductor 0.35-µm CMOS Energy-Investing ...users.ece.gatech.edu/rincon-mora/publicat/jrnls/jssc14_pz_inv.pdf · A Single-Inductor 0.35-µm CMOS Energy-Investing Piezoelectric

Future ASIC technologies in HEP Experiments · ASD GaAs Amplifier-shaper ~47000 CMA 0.18 µ CMOS Coincidence matrix ~3300 TGC TGC ASD Bipolar Amplifier-shaper ~81000 HpT 0.35 µ CMOS

PERSPEKTIVY ELEKTRONIKY · integrovaného obvodu předpověď dalšího vývoje slovy: ... parametry pro dané podmínky. ... Firma RCA realizovala první řadu CMOS IO (4000), ale

0.35 µm CMOS PROCESS ON SIX-INCH WAFERS, Baseline Report VI. · 2008. 12. 18. · CMOS BASELINE FABRICATION PROCESS A moderately more complex and improved Mix&Match version of the

Development of CMOS Pixel sensors (CPS) for vertex ... · State of the art (1) • IPHC-Strasbourg and collab. – CPS developped since ~ 1999 – Typical performances in AMS 0.35

h 0.35 trazo 0.25 (2)

[XLS]owmnahar.comowmnahar.com/nahar_polyfilm/pdf/0910.xlsx · Web view44.1 24.5 49 49 24.5 24.5 16.45 24.5 24.5 68.599999999999994 24.5 0.35 0.35 4.9000000000000004 24.5 24.5 0.35

Evaluation of the AMS 0.35 µm CMOS Technology for Use in ...amicsa.esa.int/2012/pdf/S5_07_Ramos_Martos_slides.pdf · Evaluation of AMS 0.35mm CMOS for ... Evaluation of the AMS 0.35

Mechanical Properties Measurements of 0.35-µm BiCMOS …Mechanical Properties Measurements of 0.35-µm BiCMOS MEMS Structures ... CMOS fabrication is fast, reliable, repeatable, economical,

Flash Storage Trends & Ecosystem - JEDEC1).pdf · • There are limitation on current CMOS IO, ~250MHz; ~533MHz for PoP • To improve performance CMOS IO, pincount must increase

XBMC Beginners Guide 0.35

A CMOS DVD VITERBI DETECTOR: SYSTEM DESIGN VLSI IMPLEMENTATION · coding constraints. An architecture irnplementing the detector is developed, as well as a 0.35 Pm, 3LM, CMOS implementation

Untitled-2 [maxsealinc.com] · 2017. 11. 3. · 0.28 0.28 0.28 0.35 0.35 0.35 0.43 0.43 0.43 CONSTRUCTION FEATURES Integral leak path Stainless steel blow-out proof plate Stem Guide

Trieste, 8-10 November 1999 CMOS technology1 Outline Introduction CMOS devices CMOS technology CMOS logic structures CMOS sequential circuits CMOS regular

MB90F867A (S) , MB90867A (S)...communication macros. With the new 0.35 µm CMOS technology, Fujitsu now offers 128 Kbytes on-chip FLASH-ROM program memory. An internal voltage booster

5 - 28 A Design of 0.35 m CMOS Multi-channel Shaper for

A Single-Inductor 0.35-µm CMOS Energy-Investing ...rincon-mora.gatech.edu/publicat/jrnls/jssc14_pz_inv.pdfTo comprehend the mechanics of the system, Section II explains how 13 the

0.35 µm CMOS PROCESS ON SIX-INCH WAFERS, Baseline …complex 0.35 µm twin-well, silicided, LOCOS, Mix&Match photo process was implemented. This process was based on the first 0.35

Integrated CMOS DC-DC Converter with Digital … point tracking system developed in 0.35 µm CMOS for use in the system depicted in Fig. 1. This MPPT system includes both power point

4Gbps CMOS Backplane Receiver with Adaptive Blind DFE...This thesis presents a serial backplane receiver with adaptive blind decision feed back equalization (DFE), designed in 0.35

Single Fiber Optical IO on standard 0.35 um CMOS Nan Marie Jokerst Martin A. Brooke Duke University Department of Electrical and Computer Engineering email:

AD8551/52 1.5MHZ Zero-Drift CMOS Rail-to-Rail IO Opamp ...file.elecfans.com/web1/M00/B3/6E/pIYBAF4... · The AD855X amplifier is single/dual supply, micro-power, zero-drift CMOS operational

Catabolic Response Profiles, Catabolic Uniformity and ...0 8.84 3 0.35 A 20 10.96 3 0.35 B 200 10.29 3 0.35 B 2000 10.30 3 0.35 B not affected by the application rate and there were

CMOS-C320 CMOS-C230 CMOS-C230W - KENWOODmanual.kenwood.com/files/B5A-0951-10.pdf · cmos-c320 ケンウッド専用スタンダードリアビューカメラ cmos-c230 cmos-c230w

Towards Gfps CMOS image sensors - eunevis.orgeunevis.org › wasc2017 › wp-content › uploads › 2017 › 05 › TurchettaWASC17.pdf5 Gbit/sec IO 10 bit accuracy 1μsec blanking

Evaluation of the AMS 0.35 µm CMOS Technology for Use in Space …microelectronics.esa.int/amicsa/2012/pdf/S5_07_Ramos... · 2012. 9. 5. · Ids vs. Vgs – NMOS/M (0-1Mrad) –

14 14 14 14 0.35 0.35 0.35 0.35 3.65 3.80 4.15 4.55 140 ... · 14 14 14 14 0.35 0.35 0.35 0.35 3.65 3.80 4.15 4.55 140 111 65 38 .0 .9 105/70 115/75 130/90 160/110 12 12 12 14 0.3

0.35 µm CMOS PROCESS ON SIX-INCH WAFERS, Baseline Report V. - EECS at UC Berkeley | · PDF file · 2007-02-090.35 µm CMOS PPROCESS ON SIX-INCH WAFERS Baseline Report V. A. Pongracz

E. ~Y-~ .:It. Fermilab Library/T0943_mou.pdf · Pixel prototypes, CAPl and CAP2. Both are based on the TSMC . 0.35~m . process that is a standard CMOS process (good reliability, high

Microelectronic Circuits for Energy Harvesting · Switch Control (Peak detector, zero crossing detector, active diode) Features 0.35 µm CMOS, 18 V input transistors ASIC powered

ORCA OR2CxxA (5.0 V) and OR2TxxA (3.3 V) Series Field ...noel.feld.cvut.cz/vyu/apo/amd/DS96-140.pdf · High-performance, cost-effective, low-power 0.35 µ m CMOS technology (four-input