2002 Proceedings of the 48th ATM, ISBN: 1-877862-81-9, Document No. 2011, Published on April 1, 2002

Simulation Improved Testing of Electronic Hardware

M. Osterman and A. Dasgupta -CALCE Electronic Products and System Center, University of Maryland, College Park, Maryland L. Tonnelier- EADS CCR, Suresnes Cedex, France ABSTRACT

Simulated guided testing is introduced as a process for evaluating the life expectancy of

electronic hardware and for developing and assessing the effectiveness of physical tests. An

avionic circuit card assembly is examined as a demonstration vehicle for the process.

Simulation techniques are used to assess effectiveness of physical tests on the avionic circuit

card assembly. The impact of component and material substitutions are examined. The

process is shown to provide the ability to relate physical tests to anticipated field conditions.

The time frame required to conduct a test to failure and to identify the life limiting features of

the circuit card assembly is determined.

Keywords: Virtual Qualification, Physics of Failure, Circuit Card Assemblies, Interconnect Failure INTRODUCTION As manufacturers of electronic products struggle to find new ways to accelerate product

maturity and reduce time-to-market, the use of simulation techniques to assess the

expected reliability of a product under field conditions has gained increased importance.

In particular, in the area of electronic packaging, where the rate of growth has limited the

effectiveness of traditional reliability approaches, simulation-guided testing has been

shown to be an effective approach for developing and fielding reliable products.

Simulation-guided testing involves virtual qualification and physical verification. The

process of simulated guided testing is in Figure 1. Virtual qualification is the application

of simulation techniques to determine the ability of a system to meet desired life-cycle

goals. By increasing life cycle load conditions in the virtual qualification process, the

1

effectiveness of physical tests and the time required to conduct tests can be assessed.

Physical verification is the process of defining and conducting physical tests on the

product, or a representative product, to demonstrate that the simulation adequately

modeled the anticipated use-induced failures. In recent years, the application of

simulation-guided testing as a method for assessing product reliability has been

demonstrated on a number of electronic systems (Osterman et. al. (1997), Osterman and

Stadterman (1999), Osterman and Stadterman (2000), and Cunningham et. al. (2001)).

CASE STUDY EXAMPLE

Like many other segments of the electronics industry, avionic designs have been

traditionally developed based on a design-build-test-fix (DBTF) process. With tighter

production schedules, DBTF can delay production if design deficiencies emerge during

the testing phase. In addition, the time and cost involved in fabricating and testing

multiple prototypes can be prohibitive. To reduce time and cost of development and to

improve design reliability, engineers from a major avionics manufacturer investigated

incorporating virtual qualification and physical verification in their development process.

In the following sections, the virtual qualification process as presented in Figure 1 is

demonstrated in the development of a circuit card assembly to be used in unmanned flight

system.

Design Capture

The information inputs for conducting virtual qualification are established by identifying

potential failures based on the anticipated geometries, materials, and loading conditions.

In general, the process entails reviewing the bill of materials, design drawings, and

manufacturer specification documents for parts and materials to be used in creating the

product.

In this study, a circuit card assembly, housed in an electronic rack that provides edge

supports, was the subjected to the virtual qualification process. The rack provides

2

physical support, an electrical interface for connecting the circuit card to other electronic

systems . The circuit card assembly (depicted in Figure 2), consists of a printed wiring

board (PWB), approximately 195 mm long and 95 mm wide. The PWB is to have 12

layers (signal/power/ground) constructed with FR4 and copper metalization with a total

thickness of 1.8 mm. To implement the necessary electrical functionality, the board

supports and electrically connects over 100 components.

The components include capacitors, resistors, packaged ICs, and other devices. Relevant

information about the components includes physical dimensions, material construction,

and power dissipation rates for the design. In this study, components of various sizes

were constructed of plastic, ceramic, and metal with interconnects for attachment to the

PCB. Component package types include a ball grid array, quad flatpacks, small outline

packages, thin small outline packages, leadless packages, and 1206 and 0805 resistors

and capacitors. The metallization of the PCB is made to match the pattern of each

component’s interconnect format. Solder material for this study was a commonly used

eutectic tin-lead alloy. Material properties of the components and board are summarized

in Table 1.

Table 1 Summary of Material Properties for CCA

Material CTE

(ppm/oC)

Modulus of

Elasticity

(GPa)

FR4 13-18 11-17

Plastic 16-22 14-30

Ceramic 4-8 200-390

Life-Cycle Load Characterization

Life-cycle load characterization is the process of defining the anticipated scenarios in

which the subject of the virtual qualification will be used. For this design, the electronic

rack is to be mounted in a flight system, and the anticipated dominant loads were

determined to be vibration due to the operation of the system and temperature excursions

3

due to operation and exposure to its surrounding environment. Vibration produces

repetitive mechanical stress within the board, the packages, and the package-to-board

interconnects that over time can lead to material fractures and electrical opens because of

cyclic fatigue. Because of the use of dissimilar materials in the construction of the

electronic hardware, temperature excursions also produce mechanical stresses in

packages, board, and package-to-board interconnects, due to differences in thermal

expansions. As with vibration, temperature excursions produce mechanical stresses that

can lead to material failure. In examining the life-cycle loads, the focus was on

quantifying the vibration and thermal loading conditions.

Since vibration involves the cyclic motion of a structure, it is characterized by the

magnitude of cyclic-displacement, velocity, and acceleration. In complex situations,

vibration may be characterized in terms of frequency. Frequency is important because

structures respond to vibration energy based on their geometry, material construction, and

support structures. A common expression for vibration is the power spectral density

(PSD) curve, which plots the mean squared acceleration versus frequency. For this study,

three random vibration conditions and one shock condition are anticipated. The random

vibration loading conditions are presented as PSD curves depicted in Figures 3, 4, and 5.

Due to the nature of the application the exact load levels for the PSD curves are not

provided. The shock condition is anticipated to be a 120g 2-millisecond half-sine pulse.

With regards to temperature excursion, the circuit card assembly will be subjected to

temperature cycling due to its own operation and that of the entire flight system.

Reviewing the design requirements and the anticipated application, two temperature

profiles have been derived for the circuit card assembly. The first one (see Figure 6)

corresponds to a “cold environment” and the other one (See Figure 7) to a “hot

environment”, encountered during the flight.

Load Transformation

In order to quantify the time to failure of the circuit card assembly, it is necessary to

establish the stress levels in the assembly arising from the anticipated loading conditions.

4

This can be done through direct measurements on prototype mockups and/or by imposing

the life cycle loads on computer models of the actual product. In this study, simulation

models were developed based on the design capture and life cycle load characterization.

As discussed in the previous section, the circuit card assembly is expected to see both

temperature cycling and vibration loads. In the following sub-sections, the assessment of

the operational temperatures at potential failure sites and the mechanical response of the

CCA to vibration loading are discussed.

Thermal Analysis

In conducting the thermal analysis, the thermal energy dissipated by the board and the

components was assumed to be absorbed by the surrounding environment. Using

component information, the position of the components on the board, and the defined

board structure, a finite difference thermal analysis model was constructed. The total

power dissipated by the board based on the individual components was determined to be

approximately 4.4 watts. Based on application considerations, cooling was modeled as

natural convection from the top and bottom surfaces of the printed wiring board.

After multiple computational iterations to examine the effect of grid size, a maximum

temperature rise of approximately 32oC above ambient was established for a variety of

ambient temperatures. The hottest region of the board (the light region in Figure 8) was

found to coincide with an area where a high-heat dissipating microprocessor was located.

Analysis indicated that the operating case temperature of the processor would be

approximately 1oC above the board temperature. The simulation results were found to

have good agreement with direct temperature measurements of a prototype board. A

comparison of the experimental measurements and the simulation results is presented in

Figure 9. The results of the thermal simulations were used in subsequent evaluation of

the life expectancy of the circuit card assembly under its anticipated life cycle loads.

5

Vibration Analysis

With regards to vibration, the board is expected to be supported by wedgelock supports

on the left and right edge and a connector on the bottom. To increase the robustness of

the design to vibration, a stiffener is added to the top edge to provide extra strength along

the unsupported edge. A diagram of the support structure is depicted in Figure 10.

Under vibration loading conditions, the circuit card assembly is assumed to receive loads

through the support structures. The worst-case load is assumed to occur normal to the

support structure.

A dynamic analysis of the supported circuit card assembly indicates that the first natural

frequency will be approximately 220 Hz. The first mode shape of the circuit card

assembly is depicted in Figure 11. Experimental measurements of the first three

fundamental frequencies of a prototype circuit card assembly were taken and the

comparison with simulation results is presented in Table 2.

Table 2 Comparison of measured and simulated natural frequencies

Mode 1 Mode 2 Mode 3

1.6% 16.1% 4.8%

The overall displacement of the circuit card assembly normal to the supports is assessed

for each of the expected loading conditions. The displacement of the circuit card

assembly for loading condition 1 is presented in Figure 12. As observed in Figure 11, the

center of the unsupported edge has the largest displacement. Table 3 provides

approximated displacement for each of the four dynamic loading conditions.

Table 3: Board deflection obtained for conditions 1, 2, 3 and 4

Maximal displacement (µm) Condition 1 51 Condition 2 51 Condition 3 50

Shock 1100

6

The curvature of the board under the individual components, along with the natural

frequency of the assembly, and its overall displacement are provided as inputs for

vibration failure models.

Failure Risk Assessment

Based on the anticipated loading conditions, fatigue due to vibration and temperature

cycling was expected to be the most significant underlying failure mechanism. Fatigue

failure occurs due to repeated reversals of stress that produce fissures and cracks in a

material until a complete separation occurs. In general, fatigue failure models relate the

number of stress reversals to failure with an appropriate stress metric. For this

assessment, the vibration fatigue and shock failure assessment was based on an approach

similar to that of Steinberg (1991) and the thermal fatigue failure assessment was based

on an approach similar to the one presented by Engelmaier (1993).

The life cycle scenario for the circuit card assembly included 300 thermal cycles, 60

hours of random vibration, and the shock condition. Initial simulation of the shock

condition and temperature cycling identified a leadless clock oscillator as being likely to

fail. As a result of the initial assessments, the leadless clock oscillator was replaced with

a leaded package. After the initial assessment and design change, simulation of the

exposure of the design to shock, vibration, and temperature cycling were conducted. The

loading conditions were examined separately to identify life-limiting components. Figure

13 provides a ranked list of the first 15 components identified as life limiting under the

vibration loading condition. In Figure 13, the Failure Criteria represents days to failure.

From this assessment, it was observed that random vibration would not be a life limiting

condition. Figure 14 presents a ranked list of the first 6 components identified as life

limiting for the hot temperature cycling profile. In Figure 14, the Failure Criteria

represents relative time to failure for the listed parts. From this assessment of the updated

design, the 68 leaded ceramic quad flatpacks (CQFP), represented by U25 and U26, are

expected to result in failure of the design prior to completion of the required 300

temperature cycles.

7

Based on the thermal fatigue assessment, an alternative package format was examined for

the CQFP. To this end, U25 (later referred to as G1U) maintained its original package

and U26 (later referred to as G2U) was modeled with an alternative package. The

difference between G1U and G2U is in the lead geometry as depicted in Figures 15a and

15b, respectively. In this case, the lead presented in Figure 15b is more compliant than

the one presented in Figure 15a.

With the part substitution, simulation was conducted to determine the life improvement

expected using the G2U package and to develop accelerated testing conditions. To this

end, the following loading conditions were assessed and compared.

* Qualification profile: +25ºC (2h) / +70ºC (2h) - 3ºC/min

* VRT profile : -55ºC (15min) / +100ºC (15min) - 3ºC/min

The relative fatigue life of the G1U package and the G2U package is presented in Figure

16. It is immediately observed that the G2U package has a superior life expectancy and it

has been recommended as a replacement for the G1U package.

In addition to changing component substitutions, a redesign of the printed wiring board to

better match component CTEs was examined. In this case, a printed wiring board

(referred to as the Cu/In/Cu PWB) constructed of polyimide copper laminates and two

150 micron thick constraining copper/invar/copper cores was considered. Assuming the

layout remains the same, to provide the appropriate connectivity the board would need to

be 2.8 mm thick. Replacing the FR4 PWB with the updated proposed Cu/In/Cu PWB

model, a life assessment was made for the above-mentioned qualification and VRT

profiles.

Assessment of the CCA with the Cu/In/Cu PWB shows a marked improvement and in the

life of the ceramic components and acceptable shift in the life of the plastic components.

Returning to the comparison of the G1U and G2U package, it is observed that for the

8

qualification profile the number of cycle to failure for the G1U package on the Cu/In/Cu

PWB is more than 75 times higher than the same package on the FR4 PWB. For G2U,

the increase in life is over a factor of 100. As far as the VRT profile is concerned, the

cycles to failure is 25 times and 7 times higher, respectively, for G1U and G2U.

However, the number of cycle to failure obtained for G2U under the qualification profile

is probably overestimated. But, qualitatively speaking, G2U is more robust than G1U

and presents far less of a reliability risk. In addition, the CQFP packages of the clock

oscillator and the microprocessor (packaged as a ceramic ball grid array and referred to as

BGA) represent potential reliability risks. The life expectancies of oscillator and the

BGA for both the FR4 and the Cu/In/Cu PWBs are presented in Figure 17. In Figure 17,

it is observed that the life expectancy of the components is significantly increased with

the Cu/In/Cu PWB. In addition, the acceleration factor defined as

VRT

ionqualificat

NN

AF = (3)

is found to vary only slightly between the FR4 PWB and the Cu/In/Cu PWB.

Conclusion The application of virtual qualification has been demonstrated as a useful technique for

determining the life expectancy assessment of a circuit card design and a powerful tool

for evaluating the effect of component substitutions and material changes. The virtual

qualification of the circuit card assembly was used to develop and assess the

effectiveness of physical testing. Based on the virtual qualification, the temperature

cycling load condition was found to be the most damaging condition. Further, the time

frame required to conduct the test was determined for multiple loading conditions. In

assessing design changes to extend the life expectancy of the CCA, the use of a package

with a more compliant lead was shown to improve the robustness of the design. In

addition, substituting a Cu/In/Cu core PWB for a FR4 PWB was shown to increase the

reliability of the CCA while increasing the test time.

9

As presented in the case study, characterizing the electronic hardware, creating life-cycle

loading scenarios, assessing stress states produced by the anticipated loading scenarios,

and evaluating time-to-failure of the hardware based on established failure models are

effective methods for establishing the viability of a design as well as for improving the

design. Using this process, electronic hardware design can be qualified for an application

prior to building a physical prototype. In the case study, the overall virtual qualification

assessment process was conducted using the CalcePWA software, a product of the

University of Maryland’s CALCE Electronic Products and System Center. As research

into failures of electronic hardware continues, it can be expected that the ability to

anticipate failures and quantify product reliability through computer simulations will

continue to improve.

ACKNOWLEDGMENTS

The research for this paper was performed at the CALCE Electronic Product and Systems

Center of the University of Maryland. The Center provides a knowledge and resource

base to support the development of competitive electronic components, products and

systems. The Center is supported by more than 100 electronic product and systems

companies from all sectors, including telecommunications, computer, avionics,

automotive, and military manufacturers. In particular, the authors would like to express

their appreciation for the assistance provided by B. Foucher from EADS, D. Doucet from

EADS Missiles, P. Charpenel from Airbus and A. Timmis from MBD-UK

REFERENCES

Cunningham, J., Valentin, R., Hillman, C., Dasgupta, A. and Osterman, M. (2001). “A

Demonstration of Virtual Qualification for the Design of Electronic Hardware”,

ESTECH 2001 Proceeding. IEST, Phoenix, AZ, April 2001

Engelmaier, W. (1993). “Generic Reliability Figures of Merit Design Tools for Surface

Mount Solder Attachments”, IEEE Trans. CHMT, Vol. 16, No. 1, pp. 103-112.

10

Osterman, M., Stadterman, T., and Wheeler, R. (1997). “CAD/E Requirements and

Usage for Reliability Assessment of Electronic Products”, Advances in Electronic

Packaging 1997, EEP-Vol. 19-1, pp. 927-938.

Osterman, M. and Stadterman, T. (1999). “Failure-Assessment Software For Circuit-

Card Assemblies”, Proc. for the Annual Reliability and Maintainability Symposium, pp.

269-276.

Osterman, M. and Stadterman, T. (2000). “Reliability and Performance of PWB

Assemblies”, Chapter 9, High Performance Printed Circuit Boards, ed. C. Harper,

McGraw-Hill, New York.

Steinberg, D. S. (1991). Vibration Analysis for Electronic Equipment. John Wiley and Sons, New York.

11

Figure 1. Virtual Qualification Process (courtesy of CALCE Electronic Products and Systems Center (EPSC))

Figure 2: Schematic of Circuit Card Assembly from the Case Study Example

12

Test 1 : PSD curve

0 500 1000 1500 2000 2500 3000Frequency (Hz)

Leve

l (g^

2/H

z)

Figure 3 Random Vibration Condition 11

Test 2 : PSD curve

0 500 1000 1500 2000 2500 3000Frequency (Hz)

Leve

l (g^

2/H

z)

Figure 4 Random Vibration Condition 21

1 Due to the nature of the application the exact load levels for the PSD curves are not specified.

13

Test 3 : PSD curve

0 1000 2000 3000

Frequency (Hz)

Leve

l (g^

2/H

z)

Figure 5 Random Vibration Condition 31

Profile 1: Cold Profile

0 2 4 6 8 10 12 14 16

Time (hours)

Tem

pera

ture

(deg

ree

C)

Figure 6 Temperature Cycling Condition 1 (Duration of 1 cycle: 790 min.)2

1 Due to the nature of the application the exact load levels for the PSD curves are not specified. 2 Due to the nature of the application the exact load levels for the PSD curves are not specified.

14

Profile 2: Hot Profile

0 1 2 3 4 5 6 7

Time (hours)

Tem

para

ture

(deg

ree

C)

Figure 7 Temperature Cycling Condition 2 (Duration of 1 cycle: 285 min.)

Figure 8 Temperature profile on top layer of the printed wiring board (light region

indicates highest temperature)

15

Figure 9: Comparison of component temperatures based on experimental measurements and simulation

3 - Stiffener

Y 1 - Glide guide 1 - Glide guide

X Z

Figure 10: Structural Supports for

2 - Connector

dynamic responses assessment

16

Figure 11. Dynamic response of the circuit card assembly (mode shape 1 and

characteristic frequencies.)

Figure 12. Random mode displacement under random vibration condition 1 (light color

indicates maximum displacement)

17

Figure 13. Vibration Fatigue Ranking

Figure 14. Hot Profile Thermal Fatigue Ranking

0.3 mm

0.2 mm

Figure 15a. Lead shape of Type A Figure 15b. Lead shape of Type B

18

Figure 16. Cycle to failure of G1U - G2U, undergoing the qualification profile and the

VRT with a FR4-based board.

4 2

Figure 17. CTF of the BGA

AF = 4.

5

and the oscillator, under the qualification and VRT prof

AF = 3.

AF = 3.

AF = 4

iles

19