sic power mosfet gate oxide breakdown reliability current...
TRANSCRIPT
SiC Power MOSFET Gate Oxide Breakdown Reliability – Current Status
Kin P. CheungNational Institute of Standard & Technology
Gaithersburg, MD USA
Gate oxide TDDB--- more current shorter lifetime
SiCSiO2
TunnelingBarrier
SiCSiO2
TunnelingBarrier
Intrinsic Extrinsic
FN tunneling Trap-assisted tunneling
A. K. Agarwal, S. Seshadri, L. B. Rowland, EDL 18(12), 592(1997)
Pananakakis et al., JAP 78(4), 2635(1995)
R. Watersa and B. Van Zeghbroeck, APL 76(8), 1039(2000)
Other seen even worse:
4H-SiC
6H-SiC
Si
Lichtenwalner, D. J., B. Hull, et al., 2018 IRPS.
Gate dielectric on any substrate is inferior to thermally grown SiO2 on silicon!
Early results of SiO2 on SiC thoroughly confirmed the fear!
However ….
Things started to change about 10 years ago.
K. Matocha and R. Beaupre, Materials Science Forum Vols. 556-557 (2007) pp 675-678
250 Co, 4.5 MV/cm, 10 yr. 375 Co, 4.6 MV/cm, 10 yr.
L. Yu, K. P. Cheung, J. Campbell, J. S. Suehle and K. Sheng, 2008 IIRW FINAL REPORT, pp141-144
“Intrinsic” breakdown reliability has no problem!
-1
0
1
2
3
4
5
6
7
8
9
5 6 7 8 9 10 11
Log
(T63
%)
EOX (MV/cm)
150C
200C
250C
300C
McPherson
IEDM98 175C
9nm
McPherson
IEDM98 150
9nm
Suehle TED97
400C 22nm
Suehle TED97
400C (15nm)
-1
0
1
2
3
4
5
6
7
8
9
5 6 7 8 9 10 11
Log(T
63%
)
EOX (MV/cm)
150C
200C
250C
300C
McPherson
IEDM98 175C
9nm
McPherson
IEDM98 150
9nm
Suehle TED97
400C 22nm
Suehle TED97
400C (15nm)
-1
0
1
2
3
4
5
6
7
8
9
5 6 7 8 9 10 11
Log(T
63%
)
EOX (MV/cm)
150C
200C
250C
300C
McPherson
IEDM98 175C
9nm
McPherson
IEDM98 150
9nm
Suehle TED97
400C 22nm
Suehle TED97
400C (15nm)
Z. Chbili, J. Chbili, J. P. Campbell, J. T. Ryan, M. Lahbabi, D. E. Ioannou, K. P. Cheung, 2015 IIRW Final Report, pp. 91-94
300 Co, 6.5 MV/cm, 10 yr. (For 63% failure)
Its better than silicon!
How is that possible?
Breakdown is linked to tunneling current.
The physics of breakdown is known…. or is it?
Reliable tunneling current data as a function of temperature is missing.
for both Si and SiC.
Thermal-chemical model: Current does not play a role, and the kinetic equation is problematic.
Hydrogen release model: Hydrogen release as a function of tunneling current may differ between Si and SiCHow do released hydrogen generates defect is not known.
Anode-hole injection model: Anode-hole is created by the decay of interfacial plasmon, Si and SiC is different.How do hole injected from anode creates defect is not known.
J. S. Suehle and P. Chaparala, IEEE Trans. Electron Dev., 44(5), 801-808(1997).
Another possibility: Silicon data is not intrinsic.
20 devices per stress condition
SiC nMOS capacitors (40 x 250 um2) with 50 nm thermally grown SiO2
Z. Chbili, K.P. Cheung, J.P. Campbell, J. Chbili, M. Lahbabi, D.E. Ioannou, and K. Matocha, Materials Science Forum, 858, pp.615-618 (2016).
No extrinsic failure out of > 800 devices
-10
-5
0
5
10k Devices
Uniform Ditribution
ln(-
ln(1
-F))
10k Devices
Exponential Distribution
-10
-5
0
5
400 Devices
Uniform Distibrution
ln(-
ln(1
-F))
400 Devices
Exponential Distibrution
400 Devices
Normal Distibrution 3
100
101
102
103
104
105
106
107
-10
-5
0
5
50 Devices
Uniform Distibrution
ln(-
ln(1
-F))
TBD
(s)
100
101
102
103
104
105
106
107
50 Devices
Exponential Distibrution
TBD
(s)
100
101
102
103
104
105
106
107
50 Devices
Normal Distribution 3
TBD
(s)
10k Devices
Normal Distibrution
400 Devices
Normal Distibrution
100
101
102
103
104
105
106
107
50 Devices
Normal Distribution
TBD
(s)
10k Devices
Normal Distibrution 2
a) b) c) d)
a.1) b.1) c.1) d.1)
b.2)a.2) c.2) d.2)
a.3) b.3) c.3) d.3)
Fig. 4. Different “lucky defects” distributions with a density of defect of 108 cm-3: a) uniform distribution b) Normal distribution with defects concentrated within 10nm
from the interface c) Normal distribution with defects concentrated within 2nm around the interface d) exponential distribution of defects with defects mostly
concentrated close to the interface. For each defect profile, index x.1) shows the TDDB failure distribution of 10000 devices showing tails of early failures, index x.2)
shows the resulting TDDB distribution for 400 devices sample size which is similar to an HTOL stress, and index x.3) shows the TDDB distribution with 50 devices
sample size which is similar to a routine TDDB test at wafer level. The various distributions show that under sampling can lead to severely flawed conclusions. An
exponential distribution of defects results in a failure tail similar to what was observed experimentally.
...
..
.
.
..TAT
a)
+
+
b)
x
yz
Fig. 1. TDDB results on a total of 432 SiC DMOSFET
(200 μm x 200 μm) with a 50 nm thick oxide SiO2/SiC.
The collective data from several TDDB test fields (6.8
MV cm-1 to 10 MV cm-1) and temperatures (25 C to
275 C) were normalized to a breakdown time of 104 s.
Fig. 2. TAT probability is controlled by the probability
to tunnel into the defect (T1), and the probability to
tunnel out to the oxide conduction band (T2). The total
tunneling current resulting from TAT is at its maximum
when T1 = T2.
Fig. 3. Tunneling current in the presence of
traps: a) traps at the "lucky energy" resulting
in b) local increase in current.
101
102
103
104
105
-6
-4
-2
0
2
7.5%
Intrinsic failures
Extrinsic failures
ln(-
ln(1
-F))
TBD
(s)
-10
-5
0
5
10k Devices
Uniform Ditribution
ln(-
ln(1
-F))
10k Devices
Exponential Distribution
-10
-5
0
5
400 Devices
Uniform Distibrution
ln(-
ln(1
-F))
400 Devices
Exponential Distibrution
400 Devices
Normal Distibrution 3
100
101
102
103
104
105
106
107
-10
-5
0
5
50 Devices
Uniform Distibrution
ln(-
ln(1
-F))
TBD
(s)
100
101
102
103
104
105
106
107
50 Devices
Exponential Distibrution
TBD
(s)
100
101
102
103
104
105
106
107
50 Devices
Normal Distribution 3
TBD
(s)
10k Devices
Normal Distibrution
400 Devices
Normal Distibrution
100
101
102
103
104
105
106
107
50 Devices
Normal Distribution
TBD
(s)
10k Devices
Normal Distibrution 2
a) b) c) d)
a.1) b.1) c.1) d.1)
b.2)a.2) c.2) d.2)
a.3) b.3) c.3) d.3)
Fig. 4. Different “lucky defects” distributions with a density of defect of 108 cm-3: a) uniform distribution b) Normal distribution with defects concentrated within 10nm
from the interface c) Normal distribution with defects concentrated within 2nm around the interface d) exponential distribution of defects with defects mostly
concentrated close to the interface. For each defect profile, index x.1) shows the TDDB failure distribution of 10000 devices showing tails of early failures, index x.2)
shows the resulting TDDB distribution for 400 devices sample size which is similar to an HTOL stress, and index x.3) shows the TDDB distribution with 50 devices
sample size which is similar to a routine TDDB test at wafer level. The various distributions show that under sampling can lead to severely flawed conclusions. An
exponential distribution of defects results in a failure tail similar to what was observed experimentally.
...
..
.
.
..TAT
a)
+
+
b)
x
yz
Fig. 1. TDDB results on a total of 432 SiC DMOSFET
(200 μm x 200 μm) with a 50 nm thick oxide SiO2/SiC.
The collective data from several TDDB test fields (6.8
MV cm-1 to 10 MV cm-1) and temperatures (25 C to
275 C) were normalized to a breakdown time of 104 s.
Fig. 2. TAT probability is controlled by the probability
to tunnel into the defect (T1), and the probability to
tunnel out to the oxide conduction band (T2). The total
tunneling current resulting from TAT is at its maximum
when T1 = T2.
Fig. 3. Tunneling current in the presence of
traps: a) traps at the "lucky energy" resulting
in b) local increase in current.
101
102
103
104
105
-6
-4
-2
0
2
7.5%
Intrinsic failures
Extrinsic failures
ln(-
ln(1
-F))
TBD
(s)
-10
-5
0
5
10k Devices
Uniform Ditribution
ln(-
ln(1
-F))
10k Devices
Exponential Distribution
-10
-5
0
5
400 Devices
Uniform Distibrution
ln(-
ln(1
-F))
400 Devices
Exponential Distibrution
400 Devices
Normal Distibrution 3
100
101
102
103
104
105
106
107
-10
-5
0
5
50 Devices
Uniform Distibrution
ln(-
ln(1
-F))
TBD
(s)
100
101
102
103
104
105
106
107
50 Devices
Exponential Distibrution
TBD
(s)
100
101
102
103
104
105
106
107
50 Devices
Normal Distribution 3
TBD
(s)
10k Devices
Normal Distibrution
400 Devices
Normal Distibrution
100
101
102
103
104
105
106
107
50 Devices
Normal Distribution
TBD
(s)
10k Devices
Normal Distibrution 2
a) b) c) d)
a.1) b.1) c.1) d.1)
b.2)a.2) c.2) d.2)
a.3) b.3) c.3) d.3)
Fig. 4. Different “lucky defects” distributions with a density of defect of 108 cm-3: a) uniform distribution b) Normal distribution with defects concentrated within 10nm
from the interface c) Normal distribution with defects concentrated within 2nm around the interface d) exponential distribution of defects with defects mostly
concentrated close to the interface. For each defect profile, index x.1) shows the TDDB failure distribution of 10000 devices showing tails of early failures, index x.2)
shows the resulting TDDB distribution for 400 devices sample size which is similar to an HTOL stress, and index x.3) shows the TDDB distribution with 50 devices
sample size which is similar to a routine TDDB test at wafer level. The various distributions show that under sampling can lead to severely flawed conclusions. An
exponential distribution of defects results in a failure tail similar to what was observed experimentally.
...
..
.
.
..TAT
a)
+
+
b)
x
yz
Fig. 1. TDDB results on a total of 432 SiC DMOSFET
(200 μm x 200 μm) with a 50 nm thick oxide SiO2/SiC.
The collective data from several TDDB test fields (6.8
MV cm-1 to 10 MV cm-1) and temperatures (25 C to
275 C) were normalized to a breakdown time of 104 s.
Fig. 2. TAT probability is controlled by the probability
to tunnel into the defect (T1), and the probability to
tunnel out to the oxide conduction band (T2). The total
tunneling current resulting from TAT is at its maximum
when T1 = T2.
Fig. 3. Tunneling current in the presence of
traps: a) traps at the "lucky energy" resulting
in b) local increase in current.
101
102
103
104
105
-6
-4
-2
0
2
7.5%
Intrinsic failures
Extrinsic failures
ln(-
ln(1
-F))
TBD
(s)
-10
-5
0
5
10k Devices
Uniform Ditribution
ln(-
ln(1
-F))
10k Devices
Exponential Distribution
-10
-5
0
5
400 Devices
Uniform Distibrution
ln(-
ln(1
-F))
400 Devices
Exponential Distibrution
400 Devices
Normal Distibrution 3
100
101
102
103
104
105
106
107
-10
-5
0
5
50 Devices
Uniform Distibrution
ln(-
ln(1
-F))
TBD
(s)
100
101
102
103
104
105
106
107
50 Devices
Exponential Distibrution
TBD
(s)
100
101
102
103
104
105
106
107
50 Devices
Normal Distribution 3
TBD
(s)
10k Devices
Normal Distibrution
400 Devices
Normal Distibrution
100
101
102
103
104
105
106
107
50 Devices
Normal Distribution
TBD
(s)
10k Devices
Normal Distibrution 2
a) b) c) d)
a.1) b.1) c.1) d.1)
b.2)a.2) c.2) d.2)
a.3) b.3) c.3) d.3)
Fig. 4. Different “lucky defects” distributions with a density of defect of 108 cm-3: a) uniform distribution b) Normal distribution with defects concentrated within 10nm
from the interface c) Normal distribution with defects concentrated within 2nm around the interface d) exponential distribution of defects with defects mostly
concentrated close to the interface. For each defect profile, index x.1) shows the TDDB failure distribution of 10000 devices showing tails of early failures, index x.2)
shows the resulting TDDB distribution for 400 devices sample size which is similar to an HTOL stress, and index x.3) shows the TDDB distribution with 50 devices
sample size which is similar to a routine TDDB test at wafer level. The various distributions show that under sampling can lead to severely flawed conclusions. An
exponential distribution of defects results in a failure tail similar to what was observed experimentally.
...
..
.
.
..TAT
a)
+
+
b)
x
yz
Fig. 1. TDDB results on a total of 432 SiC DMOSFET
(200 μm x 200 μm) with a 50 nm thick oxide SiO2/SiC.
The collective data from several TDDB test fields (6.8
MV cm-1 to 10 MV cm-1) and temperatures (25 C to
275 C) were normalized to a breakdown time of 104 s.
Fig. 2. TAT probability is controlled by the probability
to tunnel into the defect (T1), and the probability to
tunnel out to the oxide conduction band (T2). The total
tunneling current resulting from TAT is at its maximum
when T1 = T2.
Fig. 3. Tunneling current in the presence of
traps: a) traps at the "lucky energy" resulting
in b) local increase in current.
101
102
103
104
105
-6
-4
-2
0
2
7.5%
Intrinsic failures
Extrinsic failures
ln(-
ln(1
-F))
TBD
(s)
1%
10%
10,000 devices 10,000 devices
50 devices 50 devices
a1
a2
b1
b2
Small sample size is very misleading.
-5
-4
-3
-2
-1
0
1
2
-5
-4
-3
-2
-1
0
1
2
1 10 100 1000 10000 100000
LN(-
LN(1
-F))
LN(-
LN(1
-F))
Stress Time [s]
T63: 500s, b: 0.5
T63: 50000s, b: 15
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
16000 26000 36000 46000 56000
LN(-
LN(1
-F))
LN(-
LN(1
-F))
Stress Time [s]
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
16000 26000 36000 46000 56000
LN(-
LN(1
-F))
LN(-
LN(1
-F))
Stress Time [s]
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
16000 26000 36000 46000 56000
LN(-
LN(1
-F))
LN(-
LN(1
-F))
Stress Time [s]
~9000s63%Extracting lifetime directly leads to
underestimation!
It may not be big enough to explain the result.
Intrinsic breakdown reliability of SiO2/SiC MOS system is proven.
Status
What about extrinsic failures?
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
1 10 100 1000 10000 100000
Ln(-
ln(1
-F))
Time to Breakdown [s]
Typical Weibull distribution for SiC/SiO2 TDDB
Improving wafer cleanliness improved the initial distribution which is worse than this
Further improvement in wafer cleanliness cannot improve beyond this.
The “luck defect” model
It explains further improvement must come from improving the oxide growth process itself.
Ogier, J. L. et al., Solid State Dev. Res. Conf., ESSDERC '95. pp 299 - 302
Lifetime is determined by the Extrinsic distributions.
-5
-4
-3
-2
-1
0
1
2
-5
-4
-3
-2
-1
0
1
2
1 10 100 1000 10000 100000
LN
(-LN
(1-F
))
LN
(-LN
(1-F
))
Stress Time [s]
T63: 500s, b: 0.5
T63: 50000s, b: 15
First extract the distributionThen do the projection.
Intrinsic failure (thick oxide): b > 15 Extrinsic failure (all oxide): b < 1
Breakdown population is a joint distribution of intrinsic and extrinsic distributions.
Failure fraction scaling: Active area scaling:
From characteristic failure time (t63) to 0.63% failure time:
b = 0.5 b = 15
T63/1.36T63/10000
From 100m x 100m test structure failure time to 10 cm2 product failure time:
2.15 times shorter10 billion times shorter
b
1
6363
P
TTP
A
A b
1
2
121
)1ln(
1ln
F
FFF
For intrinsic lifetime of thick oxide, t63@E of any size test device is adequate.
For extrinsic lifetime of any oxide, failure fraction and test device area must be accounted for.
The significance of Weibull slope b
Status
No extrinsic TDDB lifetime has been reported with proper extraction.
No TDDB result with sufficient device under test has been reported.
No standard reliability requirement has been established.
Extrinsic failure still dominates SiC MOSFET breakdown reliability
We are not out of the wood … yet.
(Encouraging ramp voltage test has been reported)
(Our TDDB result has too small an area)
(These represent two examples of dramatic improvement – no longer stuck)