session three

http://www.bized.co.uk

Copyright 2006 – Biz/ed

Prepared by Alaa Salah Shehata Mahmoud A. M. Abd El Latif Mohamed Mohamed Tala’t Mohamed Salah Mahmoud

Version 02 – October 2011

Session 3



-ALU mini project discussion

-Concurrent Statements

1-Assign Statement

2-Process

3-When-else

4-With-select

-Data Objects

1-Signals

2-Variables

3-Constants

3 Contents

2



ALU mini project discussion

3

Session 3

Sel Operation

0000 Y<= a

0001 Y<= a+1

0010 Y<= a-1

0011 Y<= b

0100 Y<= b+1

0101 Y<= b-1

0110 Y<= a+b

0111 Y<= a+b+cin

1000 Y<= not a

1001 Y<= not b

1010 Y<= a AND b

1011 Y<= a OR b

1100 Y<= a NAND b

1101 Y<= a NOR b

1110 Y<= a XOR b

1111 Y<= a XNOR b



Session 3

Concurrent Statements

4

Statements

Concurrent

Assignment

Process

When-Else

With-Select

Sequential

IF

CASE

FOR

WAIT



We can consider any system to be consisted of many blocks each has a

specific function and work together concurrently (in parallel) to form the

whole function.

As VHDL is a Hardware Description Language so the default statements in

VHDL are those who are executed in parallel.

These statements are called Concurrent statements.

Session 3

Concurrent Statements Concurrency

5



In this Example, the value of x depends on a AND b, whenever a/b changes x will

change accordingly

Similarly the value of y will always change whenever c/d changes

It might happen that the value of x changes at the same time the value of y changes Both changes happen concurrently

Session 3

Concurrent Statements Illustrating Example

6

BEGIN

x <= a AND b;

y <= c AND d;

e <= x AND y;

END ;

These assignment statements are concurrent, they can be written in any order

Think as Hardware

a

b

c

d

x

y

e



Assignments relating outputs to inputs

Non Blocking Assignment <= is used

Assign statements can be written in any order.

architecture rtl of logic_gate is

begin

x <= a AND b;

y <= c OR b;

end rtl;

Session 3

Concurrent Statements 1- Assign Statements

7



Process allows writing sequential statements within concurrent environment

Process declaration <Process Name> : PROCESS (sensitivity list)

process declaration;

Begin

sequential statements ;

End PROCESS <Process Name> ;

Session 3

Concurrent Statements 2- Process

8

1

1 <Process Name> : Optional Label 2 PROCESS : Keyword 3 sensitivity list :

Signals inside it when make an event, the process trigger 4 process declaration 5 Begin : Keyword

6 Sequential statements

7 End : Process Suspend

2 3

5

6

4

7



Session 3

Concurrent Statements Transactions

9

Process (A,B)

begin

C <= A AND B ;

end process ;

The current value of A,B is read and the process is begun .

C <= A AND B ; causes a transaction

The value updated in C when the process suspend.

Transaction occurs when the process suspend

A B C

0 1 0

1 0 0

1 1 1



Session 3

Concurrent Statements Events

10

If the value of D is changed as a result of this transaction, an event occurs on this

signal.

Event occurs on signal when the value change

Process (A,B)

begin

C <= A AND B ;

end process ;

A B C

0 1 0

1 0 0

1 1 1



Session 3

Concurrent Statements Events vs Transactions

11

All signal assignment cause a transaction to be scheduled, but not every

transaction will result in an event on the target signal.

Note

Only an event on a given signal will cause a process to trigger if that signal is

included in its sensitivity list.

1-Signal A =0

2-Signal B changes to 0

3-process triggers on signal B event

4-Expression reevaluated

5-Transaction scheduled logic 0 on C

6-Process suspend

7-Tranasction applied to C

8-Value of C does not changed

9-No event on C only Transaction



• Find values of A,D and B

12

Session 2

Example 13

Process (A,B)

begin

A <= B + C ;

D <= B + E ;

B <= F + G ;

end process ;

Signal Value

E 3

C 2

F 4

B 1

G 5



Session 3

13

Process (A,B)

begin

A <= B + C ;

D <= B + E ;

B <= F + G ;

end process ;

Signal Value

E 3

C 2

F 4

B 1

G 5

Signal After first time this Process Trigger

After Process Suspend

Event

A 3 11

D 4 12

B 9 9



Session 3

Concurrent Statements Modeling Concurrency

14

A VHDL simulator is event driven

- At any single point of discrete simulation time:

(1) All processes execute until they suspend

(2) Signals are updated

(3) Events on those signals cause more processes to resume execution

This is referred to as a delta cycle



The event scheduler is the heart of the HDL behavioral environment

Each transaction is scheduled at its appropriate discrete time

Discrete time advances only when no more transactions are scheduled at the current time

Session 3

Concurrent Statements Modeling Concurrency

15



Session 3

Concurrent Statements Connecting Processes

16

Processes and other concurrent operations are seen to take place at the same point in

discrete simulation time



17

Session 3

Multiple Processes



18

a suspended process is activated when any of signal of sensitivity list

changes.

If we have multiple process and all is activated then all statement is

each process is executed sequentially .

all process in any architecture are executed concurrently with each

other.

Session 3

Concurrent vs Sequential



<target> <= <expression> when <condition>

else <expression> when <condition>


…

else <expression> ;

–LHS can be an internal signal or an output port

–RHS is an expression that operates on internal signal and/or input ports when the branch

condition is true

–Last “else” branch covers all missing conditions

Session 3

Concurrent Statements 3- when-else

19



• 4X1 Multiplexer using when-else

20

Session 3

Example 14



Architecture behave of mux_when is

Begin

F <= a when sel = "00" else

b when sel = "01" else

c when sel = "10" else

d when sel = "11" else

„Z‟;

-- This is one statement with semicolon at the end only

End behave ;

Session 3

4X1 MUX (when-else)

21



With <select_signal> select

<target> <= <expression> when <value>,

<expression> when <value>,

….

< expression> when others;

–<select_signal> can be an internal signal or an input port

–<target> can be an internal signal or an output port

–<value> constants representing one of possible <select_signal> values.

–“When others” is a must if not all values of <select_signal> are covered

Session 3

Concurrent Statements 4- With – select - when

22



• 4X1 Multiplexer using with-select-when

23

Session 3

Example 15



Architecture behave of mux_with is

Begin

With sel select

F <= a when "00",

b when "01",

c when "10",

d when "10",

„Z‟ when others;

-- needed to cover missing “sel” values

End behave ;

Session 3

4X1 MUX (With – select - when)

24



• Simulate 2X4 Decoder and 4X2 Encoder

Using When-else and With-Select-When

25

Session 3

lab 2



Session 3

26

With <select_signal> select

<target> <= <expression> when <value>,

<expression> when <value>,

….

< expression> when others;

------------------------------------------------------------------------------------

<target> <= <expression> when <condition>



…

else <expression> ;



Architecture behave of decoder2x4 is

Begin

F <= "0001" when a = "00" else

"0010" when a = "01" else

"0100" when a = "10" else

“1000" when a = "11" else

“ZZZZ";

End behave ;

Session 3

2x4 Decoder (when-else)

27



Architecture behave of encoder2x4 is

Begin

F <= “00" when a = “1000" else

"01" when a = “0100" else

"10" when a = “0010" else

"11" when a = “0001" else

“ZZ";

End behave ;

Session 3

4X2 Encoder (when-else)

28



Architecture behave of decoder4x2 is

Begin

With a select

F <= "0001" when "00",

"0010" when "01",

“0100" when "10",

“1000" when "11",

“ZZZZ" when others;

End behave ;

Session 3

2x4 Decoder (With – select - when)

29



Architecture behave of encoder2x4 is

Begin

with A select

F <= "00" when “1000",

"01" when "0100",

"10" when “0010",

"11" when “0001",

“ZZ" when others;

End behave ;

Session 3

4X2 Encoder (With – select - when)

30



Questions

Session-3

Session 3

31



32

Break

Be ready for the second part of this session

2:00 1:59 1:58 1:57 1:56 1:55 1:54 1:53 1:52 1:51 1:50 1:49 1:48 1:47 1:46 1:45 1:44 1:43 1:42 1:41 1:40 1:39 1:38 1:37 1:36 1:35 1:34 1:33 1:32 1:31 1:30 1:29 1:28 1:27 1:26 1:25 1:24 1:23 1:22 1:21 1:20 1:19 1:18 1:17 1:16 1:15 1:14 1:13 1:12 1:11 1:10 1:09 1:08 1:07 1:06 1:05 1:04 1:03 1:02 1:01 1:00 0:59 0:58 0:57 0:56 0:55 0:54 0:53 0:52 0:51 0:50 0:49 0:48 0:47 0:46 0:45 0:44 0:43 0:42 0:41 0:40 0:39 0:38 0:37 0:36 0:35 0:34 0:33 0:32 0:31 0:30 0:29 0:28 0:27 0:26 0:25 0:24 0:23 0:22 0:21 0:20 0:19 0:18 0:17 0:16 0:15 0:14 0:13 0:12 0:11 0:10 0:09 0:08 0:07 0:06 0:05 0:04 0:03 0:02 0:01 Start



Session 3

Data Objects

33



-Data Objects are the Value holders -VHDL offers different data objects: 1-Signals Used to model connections Signals can be: External Signals Internal Signals 2-Variables Used for computations 3-Constants Used to store values that can’t be changed during simulation time

Session 3

Data Objects

34



Signals Used to model connections, signals can be divided into two main types :

External Signals (Ports) Used as an interface for the Entity to the outside world

pass values in and out the circuit, between its internal units. Declared in Entity All PORTS of an ENTITY are signals by default

Internal Signals Used inside the Architecture to connect different logic parts

Declared in Architecture Represents circuit interconnects (wires)

Session 3

Data Objects 1-Signals

35



External Signal declaration

entity <entity_name> is

port (

<port_name> : <mode> <type>;

-----

<port_name> : <mode> <type>

);

End <entity_name> ; NAND_GATE ;

Internal Signal declaration

architecture <arch_name> of <entity_name> is

-- architecture declarations

signal <sig_name> : <sig_type>;

begin

End <arch_name> ;

Session 3


36

Example ENTITY AND_GATE IS port ( a,b : in BIT; C : out BIT

); END ENTITY AND_GATE ;

Example

SIGNAL control: BIT ;

SIGNAL y: STD_LOGIC_VECTOR(7 DOWNTO 0);



Assignment Operator

Assigned using “<=”

Non-Blocking Assignment

Example

inp_x <=“0000”;

sig_1 <=„1‟;

Behavior

Used in Concurrent or Sequential

Outside a process

its value is updated when their signal assignment is executed.

Inside a process

its value is updated after the process suspends

only last assignment to signal listed inside the process is effective .

Session 3


37



Objective

-Be familiar with signals declaration

-Using Signals inside and outside the process

38

Session 3

Example 16



A=1 ,B=1 ,C=1, D=2 C changes from 1 to 2

What is the values of A,B and C ?

Process (C,D)

Begin

A<=2;

B<=A+C;

A<=D+1;

C<=B+A;

End process;

39

A=

B=

C=

Session 3



A=1 ,B=1 ,C=1, D=2 C changes from 1 to 2

What is the values of A,B and C ?

Process (C,D)

Begin

A<=2;

B<=A+C;

A<=D+1;

C<=B+A;

End process;

40

A=3

B=3

C=2

Session 3



Objective

-Be familiar with signals declaration


41

Session 3

Exercise 2



42

Session 3

signal signal1: integer :=1; -- initial value



begin

process (………)

begin

……………

signal1 <= signal2;

signal2 <= signal1 + signal3;

signal3 <= signal2;

RESULT <= signal1 + signal2 + signal3;

……………

end process;

Find the value of result?



Session 3

43

-- All Signals have the uninitialized value ‘U’

-- Force A = '1' then force A='0' then A='1'

library IEEE;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_unsigned.all;

entity signal_lab is

port( A: in std_logic

);

End signal_lab;

Architecture behave of signal_lab is

Signal Z,G,F,X : STD_LOGIC;

begin

process (A)

Begin

Z <= A;

G <= '1';

F <= G;

X <= F;

G <= '0';

Z <= G;

end process ;

end behave;

A 1 0 1

Z ? ? ?

G ? ? ?

F ? ? ?

X ? ? ?



Session 3

44



library IEEE;





);

End signal_lab;



begin

process (A)

Begin

Z <= A;

G <= '1';

F <= G;

X <= F;

G <= '0';

Z <= G;

end process ;

end behave;

A 1 0 1

Z U 0 0

G 0 0 0

F U 0 0

X U U 0



Session 3

45



library IEEE;





);

End signal_lab;



begin

process (A)

Begin

Z <= A;

G <= '1';

F <= G;

X <= F;

end process ;

G <= '0';

Z <= G;

end behave;



Session 3

46



library IEEE;





);

End signal_lab;



begin

process (A)

Begin

Z <= A;

G <= '1';

F <= G;

X <= F;

end process ;

G <= '0';

Z <= G;

end behave;

Any statement written out side process is concurrent statement ,

It execute concurrently with process

G and Z has two values at same time value of A and value of G.



Variables are used for computations

Represent only local information

Declared inside a process

can only be used inside a PROCESS (in sequential code). Variable declaration

architecture behave of MPU is

begin

process(…)

variable x, y : std_logic ;

variable intbus : std_logic_vector(7 downto 0);

begin

.

. .

end process ;

.

.

end behave;

Session 3

Data Objects 2-Variables

47



Assignment Operator Assigned using “:=” Blocking Assignment

Example

var_x :=“0000”; var_1 :=„1‟;

Behavior

its value can not be passed out directly its update is immediate, so the new value is used in the next line of code. As long as signal and variable have same type they can be assign to each other .

Session 3

Data Objects 2-Variables

48



Objective

-Be familiar with variable declaration

-Using variable inside the process

49

Session 3

Example 17



process(……)

variable variable1: integer :=1;



begin

………

variable1 := variable2;

variable2 := variable1 + variable3;

variable3 := variable2;

RESULT <= variable1 + variable2 + variable3;

………..

end process;

Session 3

50



Objective

-Be familiar with variables declaration


51

Session 3

Exercise 3



Session 3

52

-- Force A = "001"

library IEEE;




port( A : in std_logic_vector(2 downto 0)

);

End signal_lab;


begin

process (A)

Variable Z,G,F,X : std_logic_vector(2 downto 0);

Begin

G := A + A;

F := G + A;

X := G + F;

Z := X + F;

end process ;

end behave;



made when we declare the variable or the function

using := signal sigbus : std_logic_vector(7 downto 0) := "01011110"; variable z : std_logic := '1'; variable varbus : std_logic_vector(3 downto 0) := "0001";

Session 3

Data Objects Initialization

53



Signals inside your design should have initial values

Synthesis tools ignore initial values specified for a variable or a signal in its declaration.

The best way for initialization is to initialize the signals when the reset is active.

If reset = „1‟ then

sig_1 <= „0‟ ;

sig_2 <= “00000”;

sig_3 <= “10101010”;

out_1 <= “00”

elsif ris……

………

Session 3

2-Initializations

54



Session 3

Data Objects Signal vs Variable

55

Signals Variables

Declaration Internal : Inside Architecture Declaration

Inside Process Declaration

External : Inside Port entity

Assignment Non-Blocking Assign <= Blocking Assign :=

Initialization := :=

Update After the process suspend Immediately

Scope Seen by the whole code Can be used in either type of code, concurrent or sequential.

Local onside process Can only be used inside a sequential code

UTILITY Represents circuit interconnects

(wires) Represents local information



-Ports are signals and declared at the top level (entity) -Within the architecture, local signals are declared -Within the process, local variables can be declared

Session 3

Data Objects Object Scope

56



A constant can have a single value of a given type and cannot be changed during the simulation. Constant Declaration constant <con_name> : <data_type>; := <con_value>;

Constants can be declared at the start of an architecture and can then be used anywhere within the architecture. Constants declared within a process can only be used inside that specific a Process. Example CONSTANT set_bit : BIT := '1';

Session 3

Data Objects 3-Constants

57



58

Session 3

Example 18

Objective

-General Example



Calculate the values of var1, sig1& Q

process (a,b)

variable var1: integer;

begin

var1 := a + b;

sig1 <= var1;

Q <= sig1;

end process;

59

Session 3

Exercise 4

Var1 sig1 Q

A=1 B=2

3 4 6

A=2 B=3

A=5 B=2

During process

During process

Process suspend

Process suspend



Session 3

60

Calculate the values of var1, sig1& Q

Var1 sig1 Q

A=1 B=2

3 4 6

A=2 B=3

5 4 6

5 5 4

A=5 B=2

7 5 4

7 7 5

During process

During process

Process suspend

Process suspend

process (a,b)

variable var1: integer;

begin

var1 := a + b;

sig1 <= var1;

Q <= sig1;

end process;



• Do one of the Previous Exercises on ModelSim

to sense the difference between signals and variables

61

Session 3

lab 4



Assignment

Session-3

Study the three sessions well

62

Session 3



Download Session 3 material

Session 3.pdf

Ask for the material through mail

[email protected]

Facebook group

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Session 3

63



Questions

Session-3

Session 3

64



Take Your Notes Print the slides and take your notes here

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Session 3

65



See You Next Session

Session 3

66

session three

Technology

assign statement

data objects1signals2