sequential logic post-activity discussion: an overview © 2014 project lead the way, inc.digital...
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Sequential LogicPost-Activity Discussion: An Overview
© 2014 Project Lead The Way, Inc.Digital Electronics
Sequential Logic
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This presentation will• Introduce the basics of combinational and
sequential logic.
• Present the logic symbol and function table for the “D” flip-flop.
• Review the design for a simple sequential logic circuit.
Combinational & Sequential Logic
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CombinationalLogic Gates
Inputs Outputs...
.
.
.
CombinationalLogic Gates
.
.Inputs Outputs
Memory Elements
(Flip-Flops)
.
.
Clock
CombinationalLogic
SequentialLogic
The “D” Flip-Flop
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Inputs Outputs
Preset Clear Clock Data-In
1 1 1 1 0 : Rising Edge of Clock
1 1 0 0 1 : Rising Edge of Clock
1 1 0 1 The output will stay the same.
0 1 X X 1 0
1 0 X X 0 1
0 0 X X 1 1 ILLEGAL CONDITION
0Q0Q
Q
Preset
Data-In
Clock
Clear
Q
Sequential Logic
• The “D” flip-flop is just one of several types of flip-flops that can be used to implement sequential logic designs.
• This presentation will look at the Divide-by-Two circuit.
• This sample flip-flop application can be implemented with “D” flip-flops. Unit 3 of this course will spend a significant amount of time exploring other flip-flops and their applications.
• The purpose of this introduction is to provide a basis of understanding for the sequential logic subsection of the Board Game Counter design. 5
Divide-by-Two Circuit: 1st Clock
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Pulse-In
Pulse-Out
Pulse-In
Pulse-Out
Preset = 1
Clear = 1
Preset = 1
Clear = 1
Logic ‘0’Logic ‘1’
Divide-by-Two Circuit: 2nd Clock
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Pulse-In
Pulse-Out
Pulse-In
Pulse-Out
Preset = 1
Clear = 1
Preset = 1
Clear = 1
Logic ‘0’Logic ‘1’
Divide-by-Two Circuit: 3rd Clock
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Pulse-In
Pulse-Out
Pulse-In
Pulse-Out
Preset = 1
Clear = 1
Preset = 1
Clear = 1
Logic ‘0’Logic ‘1’
The 3rd pulse is a repeat of the 1st, the 4th will be a repeat of the 2nd, etc.
Divide-by-Two CircuitPeriod & Frequency - Overview
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Preset
Pulse-In
Clear
Pulse-Out
Preset
Pulse-In
Clear
Pulse-Out
The period of Pulse-Out is twice the period of Pulse-In.
Since the period is twice, the frequency is divided in half.
Thus, this is a Divide-by-Two circuit.
Divide-by-Two CircuitPeriod & Frequency – The Numbers
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frequency) the (half : ƒ
ƒ
Out-Pulse of Frequency : T
ƒ
In-Pulse of Frequency : T
ƒ
period) the (twice : TT
Out-Pulse of Period : T
In-Pulse of Period : T
2
2
2
1
1
2
1
22
11
1
2
1
Preset
Pulse-In
Clear
Pulse-Out
Pulse-Out
Pulse-In
T1
T2
Divide-by-Two CircuitPreset & Clear
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Preset
Pulse-In
Clear
Pulse-Out
Preset
Pulse-In
Clear
Pulse-Out
CLEAR HOLDS THE OUTPUT
LOW
PRESET HOLDS THE
OUTPUT HIGH
Preset & Clear are active low signals.
Sequential Logic Design Example
The following is a review of the design and operation of a
sequential logic circuit using “D” flip-flops. This design is a
simple two-bit binary counter that counts from zero
(010=002) to three (310=112) and then repeats.
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Design Example: Circuit Design
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Design Example: Functional Test(1 of 3)
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Clock-In
B
A B IS HALF THE
FREQUENCY OF
CLOCK-IN.
THE FIRST FLIP-
FLOP IS CLOCKED
BY CLOCK-IN.
Design Example: Functional Test(2 of 3)
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Clock-In
B
A
A is half the frequency of B.
Note: A toggles on the falling edge of B, which is the rising edge of .
The second flip-flop is
clocked by the of
the first flip-flop.
Q
B
Design Example: Functional Test(3 of 3)
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Clock-In
B
A
“0”
0
0
“1”
0
1
“2”
1
0
“3”
1
1
“0”
0
0
Design Example: IC Component View
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3
2
1
4
5
6 11
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