Sequential CircuitSequential Circuit- Counter -- Counter -

INTRODUCTIONINTRODUCTION• A counter – a group of flip-flops connected together to perform counting operations.

• The number of flip-flops used and the way in which they are connected determine the number of states (modulus).

• Two broad categories according to the way they are clocked:

• Asynchronous counter

• Synchronous counter

ASYNCHRONOUS COUNTER: ASYNCHRONOUS COUNTER:

A 2-bit asynchronous binary counter.

•Don’t have fixed time relationship with each other.

•Triggering don’t occur at the same time.

•Don’t have a common clock pulse

The Timing diagramThe Timing diagram

Notice that :

• Main clock pulse only applied to FF0.

• Clock for next FF, taken from previous complemented output ( Q ).

• All inputs (J, K) are high (Vcc).

The Timing diagramThe Timing diagram

The Binary State SequenceThe Binary State Sequence

CLOCK PULSE Q1 Q0

Initially 0 0

1 0 1

2 1 0

3 1 1

4 (recycles) 0 0

0

1

1

0

1

1

0

00

0

Three-bit asynchronous binary counter and its timing Three-bit asynchronous binary counter and its timing diagram for one cycle. diagram for one cycle.

The Binary State Sequence for a 3-bit The Binary State Sequence for a 3-bit Binary CounterBinary Counter

CLOCK PULSE Q2 Q1 Q0

Initially 0 0 0

1 0 0 1

2 0 1 0

3 0 1 1

4 1 0 0

5 1 0 1

6 1 1 0

7 1 1 1

8 (recycles) 0 0 0

Propagation delays in a 3-bit asynchronous (ripple-Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter.clocked) binary counter.

Four-bit asynchronous binary counter and its timing Four-bit asynchronous binary counter and its timing diagram. diagram.

ASYNCHRONOUS DECADE COUNTER: ASYNCHRONOUS DECADE COUNTER:

• The modulus of a counter is the number of unique states that the counter will sequence through.

•The maximum possible number of states (max modulus) is 2n . Where n is the number of flip-flops.

•Counter can also be designed to have a number of states in their sequence that is less than the maximum of 2n. The resulting sequence is called truncated sequence.

•Counter with ten states are called decade counter.

•To obtain a truncated sequence it is necessary to force the counter to recycle before going through all of its possible states.

An asynchronously clocked decade counterAn asynchronously clocked decade counter

Read example 9-2 page 465!! Modulus 12

The 74LS93A 4-bit asynchronous binary counter logic diagram. (Pin numbers are in The 74LS93A 4-bit asynchronous binary counter logic diagram. (Pin numbers are in parentheses, and parentheses, and all all JJ and and KK inputs are internally connected HIGH inputs are internally connected HIGH.).)

Comprehending Engineers… Comprehending Engineers…

To the optimist, the glass is half full.To the optimist, the glass is half full.To the pessimist, the glass is half To the pessimist, the glass is half

empty.empty.To the engineers.. ?To the engineers.. ?

The glass is twice as big as The glass is twice as big as it needs to be.it needs to be.

SYNCHRONOUS COUNTER OPERATION SYNCHRONOUS COUNTER OPERATION A 2-bit synchronous binary counter.A 2-bit synchronous binary counter.

Timing details for the 2-bit synchronous counter Timing details for the 2-bit synchronous counter operation (the propagation delays of both flip-flops operation (the propagation delays of both flip-flops

are assumed to be equal).are assumed to be equal).

The Binary State SequenceThe Binary State Sequence

CLOCK PULSE Q1 Q0

Initially 0 0

1 0 1

2 1 0

3 1 1

4 (recycles) 0 0

0

0

0

1

1

0

1

1

0

0

A 3-bit synchronous binary counter. A 3-bit synchronous binary counter.

The Binary State Sequence for a 3-bit The Binary State Sequence for a 3-bit Binary CounterBinary Counter

CLOCK PULSE Q2 Q1 Q0

Initially 0 0 0

1 0 0 1

2 0 1 0

3 0 1 1

4 1 0 0

5 1 0 1

6 1 1 0

7 1 1 1

8 (recycles) 0 0 0

A 4-bit synchronous binary counter and timing diagram. A 4-bit synchronous binary counter and timing diagram. Points where the AND gate outputs are HIGH are indicated Points where the AND gate outputs are HIGH are indicated

by the shaded areas.by the shaded areas.

A 4-Bit Synchronous BCD Decade Counter. A 4-Bit Synchronous BCD Decade Counter.

The Binary State Sequence for BCD Decade CounterThe Binary State Sequence for BCD Decade Counter

CLOCK PULSE Q3 Q2 Q1 Q0

Initially 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 (recycles) 0 0 0 0

DESIGN OF SYNCHRONOUS COUNTERSDESIGN OF SYNCHRONOUS COUNTERS

General clocked sequential circuit. General clocked sequential circuit.

Steps used in the design of sequential circuitSteps used in the design of sequential circuit

1. Specify the counter sequence and draw a state diagram

2. Derive a next-state table from the state diagram

3. Develop a transition table showing the flip-flop inputs required for each transition. The transition table is always the same for a given type of flip-flop

4. Transfer the J and K states from the transition table to Karnaugh maps. There is a Karnaugh map for each input of each flip-flop.

5. Group the Karnaugh map cells to generate and derive the logic expression for each flip-flop input.

6. Implement the expressions with combinational logic, and combine with the flip-flops to create the counter.

State diagram for a 3-bit Gray code counter.State diagram for a 3-bit Gray code counter.

Next-state table for a 3-bit Gray code counter.Next-state table for a 3-bit Gray code counter.

Present State Next State

Q2 Q1 Q0 Q2 Q1 Q0

0 0 0 0 0 1

0 0 1 0 1 1

0 1 1 0 1 0

0 1 0 1 1 0

1 1 0 1 1 1

1 1 1 1 0 1

1 0 1 1 0 0

1 0 0 0 0 0

Transition Table for a J-K flip-flopTransition Table for a J-K flip-flop

Output Transitions Flip-flop Inputs

QN QN+1 J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

QN : present state

QN+1: next state

X: Don’t care

Karnaugh maps for present-state Karnaugh maps for present-state JJ and and KK inputs. inputs.

Three-bit Gray code counter. Three-bit Gray code counter.

Example: Design a counter with the irregular binary Example: Design a counter with the irregular binary count sequence as shown in the state diagram. Use J-K count sequence as shown in the state diagram. Use J-K

flip-flopsflip-flops

Next-state tableNext-state table

Present State Next State

Q2 Q1 Q0 Q2 Q1 Q0

0 0 1 0 1 0

0 1 0 1 0 1

1 0 1 1 1 1

1 1 1 0 0 1

Transition Table for a J-K flip-flopTransition Table for a J-K flip-flop

Output Transitions Flip-flop Inputs

QN QN+1 J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

K-MAPK-MAP

THE COUNTER CIRCUITTHE COUNTER CIRCUIT

Example : State diagram for a 3-bit up/down Example : State diagram for a 3-bit up/down Gray code counter.Gray code counter.

The 74HC163 4-bit synchronous binary counter. (The The 74HC163 4-bit synchronous binary counter. (The qualifying label CTR DIV 16 indicates a counter with qualifying label CTR DIV 16 indicates a counter with

sixteen states.)sixteen states.)

Timing example for a 74HC163.Timing example for a 74HC163.

The 74LS160 synchronous BCD decade counter. (The The 74LS160 synchronous BCD decade counter. (The qualifying label CTR DIV 10 indicates a counter with qualifying label CTR DIV 10 indicates a counter with

ten states.)ten states.)

Timing example for a 74LS160.Timing example for a 74LS160.

UP/DOWN SYNCHRONOUS COUNTERUP/DOWN SYNCHRONOUS COUNTER

A basic 3-bit up/down synchronous counter.A basic 3-bit up/down synchronous counter.

Timing Diagram Timing Diagram

The 74HC190 up/down synchronous decade counter.The 74HC190 up/down synchronous decade counter.

Timing example for a 74HC190.Timing example for a 74HC190.

JJ and and KK maps for Table 9-11. The UP/DOWN maps for Table 9-11. The UP/DOWN control input, control input, YY, is treated as a fourth variable., is treated as a fourth variable.

Three-bit up/down Gray code counter.Three-bit up/down Gray code counter.

CASCADE COUNTERSCASCADE COUNTERSTwo cascaded counters (all J and K inputs are HIGH).

A modulus-100 counter using two cascaded decade A modulus-100 counter using two cascaded decade counters.counters.

Three cascaded decade counters forming a divide-by-Three cascaded decade counters forming a divide-by-1000 frequency divider with intermediate divide- by-1000 frequency divider with intermediate divide- by-

10 and divide-by-100 outputs.10 and divide-by-100 outputs.

Example: Determine the overall modulus of the two Example: Determine the overall modulus of the two cascaded counter for (a) and (b)cascaded counter for (a) and (b)

For (a) the overall modulus for the 3 counter For (a) the overall modulus for the 3 counter configuration is 8 x 12 x 16 = 1536configuration is 8 x 12 x 16 = 1536

for (b) the overall modulus for the 4 counter for (b) the overall modulus for the 4 counter configuration is 10 x 4 x 7 x 5 = 1400configuration is 10 x 4 x 7 x 5 = 1400

A divide-by-100 counter using two 74LS160 decade A divide-by-100 counter using two 74LS160 decade counters.counters.

A divide-by-40,000 counter using 74HC161 4-bit binary A divide-by-40,000 counter using 74HC161 4-bit binary counters. Note that each of the parallel data inputs is shown counters. Note that each of the parallel data inputs is shown

in binary order (the right-most bit in binary order (the right-most bit DD00 is the LSB in each is the LSB in each

counter).counter).

Decoding of state 6 (110).Decoding of state 6 (110).

COUNTER DECODING

* To determine when the counter is in a certain states in its sequence by using decoders or logic gates.

A 3-bit counter with active-HIGH decoding of count 2 and A 3-bit counter with active-HIGH decoding of count 2 and count 7. count 7.

A basic decade (BCD) counter and decoder.A basic decade (BCD) counter and decoder.

Outputs with glitches from the previous decoder. Glitch Outputs with glitches from the previous decoder. Glitch widths are exaggerated for illustration and are usually only widths are exaggerated for illustration and are usually only

a few nanoseconds wide.a few nanoseconds wide.

The basic decade counter and decoder with strobing The basic decade counter and decoder with strobing to eliminate glitches.to eliminate glitches.

Strobed decoder outputs for the circuitStrobed decoder outputs for the circuit

Simplified logic diagram for a 12-hour digital clock. Simplified logic diagram for a 12-hour digital clock.

Logic diagram of typical divide-by-60 counter using Logic diagram of typical divide-by-60 counter using 74LS160A synchronous decade counters. Note that the 74LS160A synchronous decade counters. Note that the

outputs are in binary order (the right-most bit is the LSB).outputs are in binary order (the right-most bit is the LSB).

Logic diagram for hours counter and decoders. Note that on Logic diagram for hours counter and decoders. Note that on the counter inputs and outputs, the right-most bit is the the counter inputs and outputs, the right-most bit is the

LSB.LSB.

Functional block diagram for parking garage control.Functional block diagram for parking garage control.

Logic diagram for modulus-100 up/down counter for Logic diagram for modulus-100 up/down counter for automobile parking control.automobile parking control.

Parallel-to-serial data conversion logic.Parallel-to-serial data conversion logic.

Example of parallel-to-serial conversion timing for the Example of parallel-to-serial conversion timing for the previous circuitprevious circuit

THANK YOUTHANK YOU