section b: analogue electronicsee201/ee201_2007_2008_yr2_solutions.doc · web viewthe basis of a...

SOLUTIONS - SEMESTER TWO - 2008

MODULE: Digital Circuits and Systems (EE201)

COURSE: B.Eng. in Mechatronic EngineeringB.Eng. in Digital Media EngineeringB.Eng. in Electronic EngineeringB.Eng. in Information and Communications Engineering

YEARS: 2 (two)

EXAMINERS: Mr. David Bermingham

Dr. R. MillarDr. F. DevittDr. F. Owens

TIME ALLOWED: 2 hours

INSTRUCTIONS: Answer FOUR questions. All questions carry equal marks

___________________________________________________________________________________________EE201 - Digital Circuits and Systems - Semester Two - 2007/2008

page 1/18

QUESTION 1

A) Describe the structure and operation of a TTL NAND Gate which utilizes totem-pole outputs?Answer:

The basis of a TTL gate is the multiple emitter bipolar junction transistor used at the input to the gate. The logic signals pass through two layers of BJT gates, with transistors performing both the logic function and signal modification.A totem pole TTL NAND is constructed as follows….

When A and B are high (>2V) Q1 is Reverse Biased base emitter Current Flows through base of Q1 into base of Q2 (Q2B) Q2 is ON, pulling Q3B to GND Q4 in ON, pulling F to GND (0.4V)

When either A or B is low (<0.8V) Q1 is Forward biased base-emitter. Q1 is ON, discharging current in Q2B, switching Q2 OFF. Q3 is saturated, Pulling F to 5V (minus Voltage drop across

resistor & VCE of Q3 : ~3.1V) Q4 in OFF


page 2/18

If output was configured as open collector output, NAND gate would be unable to source current without a loading resistor. However, a totem-pole output configuration ensures that since only Q3 or Q4 can be on at any one time, we can both source and sink current from a following logic stage.

Totem Pole Properties Q3 and Q4 provide totem pole outputs Q3 pulls up and Q4 pulls down Faster than Pull-up Resistor Can Sink and Source current

B) In order to allow data bussing, totem pole outputs must be modified to allow tri-state operation. How is the circuit described in 1(a) modified to allow tri-state outputs?Answer:

Addition Input (En) is used to enable output=> Must be ‘1’ to stop Q1 from being switched OFF

EN A B Q1 Q2 Q3 Q4 F___________________________________________________________________________________________EE201 - Digital Circuits and Systems - Semester Two - 2007/2008

page 3/18

A B Q1 Q2 Q3 Q4 F0 0 ON OFF ON OFF 10 1 ON OFF ON OFF 11 0 ON OFF ON OFF 11 1 OFF ON OFF ON 0

0 0 0 ON OFF OFF OFF ~2.4V Hi-Z0 0 1 ON OFF OFF OFF ~2.4V Hi-Z0 1 0 ON OFF OFF OFF ~2.4V Hi-Z0 1 1 ON OFF OFF OFF ~2.4V Hi-Z1 0 0 ON OFF ON OFF 5V 11 0 1 ON OFF ON OFF 5V 11 1 0 ON OFF ON OFF 5V 11 1 1 OFF ON OFF ON 0V 0

The totem pole outputs allow for the output transistors to be both switched OFF. When in this state no current is sourced from the gate, as well as providing no sink capabilities.

C) Briefly describe why tri-state outputs might be required for shared bus digital system shown in figure 1a.Answer:

The digital system in figure 1a utilizes a shared memory bus system. All devices are memory mapped to the CPU memory address space. However, since only two devices may be connected at any point in time, we require a method of ‘removing’ idle devices from the data bus. Since totem pole outputs place a TTL output in either a driving (sourcing) or sinking state, the current loads would exceed the Unit Load for a TTL gate. By providing tri-state outputs we can ensure that devices not being accessed are removed from the data bus, providing neither drive nor sink capabilities.


page 4/18

QUESTION 2A) Design a 1-bit full adder capable of performing A + B + CIN. If 1nS NAND gates were used to construct a 32-bit ripple carry adder, how fast could the adder be switched?Answer:

Full single bit adder utilizes 3 inputs, A, B and carry in (C_IN). From this we produce a single output result (S) as well as a carry out bit (C_OUT)

The truth table and minimize K-Maps for a single adder bit are shown below

B A C_IN S C_OUT0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 1

1 0 0 1 01 0 1 0 1

1 1 0 0 11 1 1 1 1

The Sum bit of the adder can be reduced using XOR reduction to produce the following Boolean equation

The complete full adder circuit is shown below


page 5/18

The red line highlights the critical path of a full adder circuit, which has a NAND equivalence of 7 NAND delays (or 8 {depending on technology})

A 32-bit Ripple carry adder would therefore have a delay of 7-NAND gates per RCA cell up to the final RCA cell

The Sum would have a delay of 31*7 + 6223 Gates

The carry out signal would have a NAND delay of 32*7 224 Gates

At 1nS per gate the maximum frequency is 1/224.10-9 or 4.4MHz

B) What additional components are required to convert an 8-bit adder to a device capable of performing the same functions as the adder utilized in an ARM microprocessor, i.e. binary addition(with/without carry), subtraction (with/without carry) and reverse subtraction(with/without carry) ?Answer:

In order to compute subtraction we must be able to generate the equationA-B = A + (-B) + 1. To achieve inversion, a n-bit XOR inverter is placed at the input of B. Using a single control bit (nB), we can generate B when nB=0 and /B when nB is high.Since we must be able to perform A – B and B – A we also require an inverter on the A input, along with another control signal (nA).To save on gate resources it would be possible to OR the carry in, nA and nB. However this setup would not allow operations such as SUB with carry to be performed. To allow this operation we OR only the nA and nB signals, with the output of the operation XOR’ed (or Added) to the carry in signal.The final adder/subtractor is shown below


page 6/18

C) Describe the flags which are typically used for conditional operations within a CPU?Answer:Typically a CPU utilizes 4 status flags which allow conditional operations such as if, else, while, etc to be evaluated. All status flags are derived from ALU based operations and are fed back from the ALU to the instruction decoder.

The four status flags are 1) The carry out (C) bit. The most significant carry bit from either an

arithmetic add/subtract OR from the Rotate with extended operation.2) The zero bit (Z) bit which is generated when the ALU output result is

zero.3) The overflow bit which allows detection of a change in the sign bit of a

signed word.4) The negative bit which is the most significant bit of the ALU result

In terms of gate design, the carry-out and negative bit are easily extracted from the ALU since both are generated by the ALU internal logic. To detect a overflow we must implement the following equation for the most significant bit of A, B and the result R:

V = /R.A.B + R./A./B

The zero bit is implemented by XNORing all bits of the ALU result together, only when all of the result bits are clear will the Z bit be set.


page 7/18

QUESTION 3A) Briefly indicate the algorithm for designing a sequential logic circuit?Answer:

Algorithm: Obtain the description of circuit and create the State Diagram Determine the State Table Assign binary codes to each state and minimize the number of

states Determine the number of flip-flops needed and give a letter

symbol to each of them Choose the type of flip-flops Starting from State Table, derive the Excitation Table and the

Output Table Derive the minimized circuit output functions and flip-flop input

functions Draw the Logic Diagram

7 Marks

B) Design a sequential logic circuit whose output Z = 1 when the input X=1 for four consecutive clock cycles. Otherwise the output Z = 0. Use J-K Flip FlopsAnswer:

State Diagram


page 8/18

States CodingPresent State Code

A 0 0B 0 1C 1 0D 1 1

Flip FlopsThere is a need for two JK flip-flops. Let’s name them JKA

and JKB

State TablePresent

StateNext State Output

X=0 X=1 X=0 X=10 0 A B 1 10 1 A C 1 11 0 A D 1 11 1 A D 1 0

Excitation TableQA QB X Q’A Q’B JA KA JB KB Z0 0 0 0 0 0 x 0 x 10 0 1 0 1 0 x 1 x 10 1 0 0 0 0 x x 1 10 1 1 1 0 1 x x 1 11 0 0 0 0 x 1 0 x 11 0 1 1 1 x 0 1 x 11 1 0 0 0 x 1 x 1 11 1 1 1 1 x 0 x 0 0

Minimisations and EquationsJA

X\ QA QB 00 01 11 10


page 9/18

0 0 0 x x

1 0 1 x x

KAX\ QA QB 00 01 11 10

0 X x 1 1

1 X x 0 0

JBX\ QA QB 00 01 11 10

0 0 X x 01 1 X x 1

KBX\ QA QB 00 01 11 10

0x

1 1 x

X 1 0 x

ZX\ QA QB 00 01 11 10

0 1 1 1 11 1 1 0 1

Implementation


page 10/18

C) Using state reduction, indicate how the circuit cost of implementing the sequential circuit described in Table 1 could be reduced?Answer:

States E and H have equivalent transitions and outputs. We can remove state H and replace any transitions to H with E.

PresentState

Next State OutputX=0 X=1 X=0 X=1

A A B 0 0

B A C 0 0

C D F 0 1

D E C 0 1

E E F 0 1

F D H 0 0

H E F 0 1

From the updated table we can see that now states F and C are equivalent and we can remove state F.___________________________________________________________________________________________EE201 - Digital Circuits and Systems - Semester Two - 2007/2008

page 11/18

XQB

JA

KAX

X JB

XQA

KB

X

QB

ZQA

PresentState


A A B 0 0

B A C 0 0

C D E 0 0

D E C 0 1

E E F 0 1

F D E 0 0

No further reduction can be achieved since all state transitions and outputs differ.

PresentState


A A B 0 0

B A C 0 0

C D E 0 0

D E C 0 0

E E C 0 1

QUESTION 4

A) Describe the structure and operation of a floating gate MOSFET? Answer:

A floating gate MOSFET is constructed by placing an additional gate between the control gate and substrate as shown in the diagram below. This floating gate is completely insulated from all other components of the gate.


page 12/18

To program We must inject electrons into the FG

Apply large voltage between CG and Substrate Electrons tunnel into FG

To Erase We must remove electrons from FG

Reverse CG and Substrate Voltage Electrons tunnel back into substrate

For current to flow, the gate source voltage must be greater than VTH. Since a stored charge in the floating gate will modify the threshold voltage of the MOSFET we can detect if a charge is stored in the FG. By default a FG mosfet is inverted, i.e when a charge is stored in the FG no current will flow from source to drain during a read operation.

B) How are these floating gate transistors arranged to create NAND type FLASH memory systems?Answer:


page 13/18

To Read All non selecting page lines are set = 1 Select line 1 & 2 are set to 1

Connecting MOSFETs to BITLINE & GND

IF MOSFET stores a 1 Current will flow from BIT LINE to GND Pre charge Voltage on BIT LINE will change Sense logic will detect this change as 1

IF MOSFET stores a 0 Current is blocked from flowing to GND Pre Charge voltage will remain the same Sense logic will determine a 0

Device is expanded horizontally to construct large wordsMarks : 9

C) What are the major disadvantages with using floating gate transistors to create ROM circuits?Answer:

As gate insulator is thinned, the number of times it can be written is reduced. Flash might only have 10,000 write cycles

Entire block(or page) must be erased at one time in flash,(byte can be erased in EEPROM)

Requires additional higher programming voltage Charge Pump or Supply Pump

Marks : 2


page 14/18

QUESTION 5A) Describe how concept of pipelining, when applied to digital systems?Answer:Within a combinational circuit, the critical path will determine the maximum operating frequency of the circuit. The critical path of any circuit is defined by the setup and output times of the input and output registers, the wire delay associated with the circuit and the logic delay of the gates within the critical ___________________________________________________________________________________________EE201 - Digital Circuits and Systems - Semester Two - 2007/2008

page 15/18

path. Typically the logic delay comprises the majority of the delay and so pipelining is applied as a means of reducing this delay.

For the circuit shown above the delay would be dominated by the gate delay of the 2 adders and the 2:1 MUX. By placing another register half way between the input and output register it would be possible to double the operating frequency of the device. In the case of this circuit it would not be possible to place the register exactly halfway without breaking the MUX component. In this case we place the register as close to this position as possible

The pipelined circuit will operate faster than the non-pipelined system, however the circuit will require an additional clock cycle in order to complete one operation as so the pipeline must be kept full in order to ensure maximum performance.

B) How is pipelining applied within the ARM microprocessor?Answer:

During execution of an ARM Instruction1. Instruction Must be Fetched From Memory2. Decoded into the control signals


page 16/18

3. The operands must be fetched from the register bank4. The required function is performed in the ALU5. The result is written back to the Register File

If all of these tasks where performed in a single clock cycle Critical Path would be from Data IN Register -> Address

Register > Hundreds of Logic Gates between two registers

To speed things up ARM 7 CPU divides each instruction into 3 smaller tasks

FETCH : Instruction Fetched from memory

DECODE : Instruction Decode & Operand Fetch (From

Register Bank) EXECUTE:

Instruction Execute in ALU and Write result to register bank

Each pipeline stage operates independently of the other two stages, with an instruction fetched, decoded and executed on every cycle.A 3-stage pipeline such as this allows the ARM 7 architecture to operate at up to 100 MHz.


page 17/18

C) Determine the optimum position for a pipeline register in order to maximize performance of the circuit shown in figure 5aAnswer:

The critical path for the circuit is highlighted in red below. The delay across the entire circuit is 1 XOR Gate, 2 AND gates and 2 OR gates, along with any wire and register setup delays.

In CMOS NAND logic, the circuit above would have a delay ofXOR = 1 X 3 NAND = 3AND = 2 X 2 NAND = 4OR = 2 X 2 NAND = 4

= 11 NAND GatesThe optimum position for any pipeline register would be either 5 or 6 gates into the circuit, i.e before the first OR gate

The cost of the register is an additional latency cycle plus the gate cost of the 5-bit pipeline register.


page 18/18

section b: analogue electronicsee201/ee201_2007_2008_yr2_solutions.doc · web viewthe basis of a...

Documents