scheme of instruction and examination be iii...

With effect from academic year 2016-2017

SCHEME OF INSTRUCTION AND EXAMINATION

BE III YEAR

(ELECTRONCIS AND COMMUNICATION ENGINEERING)

SEMESTER – I

S.No. Code No. Subject Scheme of

Instruction Scheme of Examination

THEORY L/T D/P

Duration

in Hours

Max. Marks

Univ.

Exams

Sessionals

1 EC 301 Linear ICs and

Application 4 - 3 75 25

2 EC 302 Pulse and Digital Circuits 4 - 3 75 25

3 EC 303 Analog Communication 4 - 3 75 25

4 EC 304 Automatic Control

Systems 4 - 3 75 25

5 EC 305 Computer Organization

and Architecture 4 - 3 75 25

6 EC 306 Digital System Design with

VERILOG HDL 4 - 3 75 25

PRACTICALS

1 EC 331 Pulse, Digital and

Integrated Circuits Lab - 3 3 50 25

2 EC 332 VERILOG HDL Lab - 3 3 50 25

3 Industrial Visit

TOTAL 24 6 550 200

EC301 With effect from academic year 2016-2017

LINEAR INTEGRATED CIRCUITS AND APPLICATIONS

Instructions 4 Periods per week

Duration of University Examination 3 Hours

University Examination 75 Marks

Sessional 25 Marks

Unit-I

Differential Amplifiers: Classification, DC and AC analysis of single/dual input Balanced and

unbalanced output Configurations using BJTs. Level Translator.

Operational Amplifier: Ideal, Practical, General (741) bipolar Operational Amplifier, AC and

DC performance characteristics, Frequency Compensation, Open-loop and closed-loop

configurations, 741 Manufacturers data sheet– description, specifications, and package.

Unit 2:

Operational Amplifier Applications: Linear – adder, subtractor, integrator, differentiator, Voltage

to current converter - current to voltage converters, differential amplifiers, instrumentation

amplifiers based on two and three opamps.

Ideal and Practical Integrator, Differentiator, Log and antilog amplifier, Single supply operation

Commercial Instrumentation Amplifier AD623.Programmable Gain Amplifiers (PGA) – AD526

Unit 3:Operational Amplifier Applications Non- Linear:Comparator, Schmitt trigger, Precision

rectifier, Peak detector, Clippers, clampers, Sample-and-Hold circuits. Active Filters

Introduction – First order , Second order Active filters – LP, HP, BP,BR and All Pass. V to I and

I to V converters.

Unit 4:

Waveform Generators – Sine wave, saw tooth, Triangular wave, Voltage Controlled Oscillators,

PLL; V to F and F to V converters. Function Generator – XR2206.

Unit – V

Basic of Voltage Regulators, Linear regulators using opamp, IC Regulators 78xx and 723.

Data Converters: Introduction, basic Digital to Analog Converter techniques, Weighted Resistor

DAC, Inverted R-2R Ladder DAC. Analog to Digital Converter: Types; Parallel Comparator

ADC, Successive Approximation ADC and Dual Slope ADC. DAC and ADC specifications.

References:

1. David A Bell, “Operational Amplifiers and Linear ICs,” 3/e, Oxford Publications, 2011.

2. Ramakant A. Gayakwad, “Op-Amps and Linear Integrated Circuits,” 4/e, PHI, 2010.


PULSE AND DIGITAL CIRCUITS




Sessional 25 Marks

Objectives: Student will be able to

1. Analyze response of different inputs to RC low pass and high pass circuits

2. Design and analyze non-linear circuits like clippers and clampers

3. Design Bistable, Monostable and Astable Multivibrators using discrete components and

analyze voltage and current sweep circuits and identify methods to mitigate sweep errors.

4. Classify different ICs, calculate IC characteristics and analyze basic gates with DTL,

TTL, ECL, logic family and design their interfacing circuits

5. Build basic gates with MOS and CMOS logic family and design their interfacing circuits

UNIT I:

LINEAR WAVESHAPING: High pass, low pass RC circuits, their response for

sinusoidal, step, pulse, square and ramp inputs. RC network as differentiator and integrator,

attenuators, RL and RLC circuits and their response for step input.

UNIT II:

NON-LINEAR WAVE SHAPING:

Diode clippers, Transistor clippers, clipping at two independent levels, Transfer

ch a r ac t e r i s t i c s o f c l i p pe r s , E mi t t e r cou p l ed c l ip p er , Comp ar a t o r s ,

A p p l i c a t io ns o f vo l t age comparators, clamping operation, Clamping circuits

using diode with different inputs, Clamping circuit theorem, practical clamping

c i r cu i t s , T r an s f e r characteristics of clampers.

Transistor as a switch, Design of transistor switch, transistor-switching times.

UNIT III:

MULTIVIBRATORS: Design and Analysis of Bistable, Monostable, Astable Multivibrators and

Schmitt trigger using transistors,

TIME BASE GENERATORS: General features of a time base signal, Speed,

transmission and displacement errors. Analysis and Design of Sweep circuits using

UJT and SCR.

UNIT IV:

Manufacturer’s designations for integrated circuits, Integrated circuit package types, Pin

identifications and temperature ranges, IC characteristics, Logic Families: DTL, TTL logic

family, TTL series, output configuration: Open collector, Totem pole, Tri state logic. ECL logic

Family

UNIT V:

MOS logic Family (PMOS and NMOS), CMOS logic family and characteristics, CMOS

transmission gate (bilateral switch) and its applications,

CMOS open drain and high impedance output, CMOS inverter, NAND and NOR gates,

Interfacing CMOS and TTL, Comparison of TTL, CMOS and ECL logic families.

TEXT BOOKS:

1. Pulse, Digital and Switching Waveforms - J. Millman and H. Taub, McGraw-Hill, 1991.

2. Pulse, Switching and Digital Circuits, 5/e, - David A. Bell, Oxford University Press, 2015.

3. Fundamentals of Pulse and Digital Circuits- Ronald J. Tocci.

4. R P Jain, “Modern Digital Electronics” 3/e TMH 2003


ANALOG COMMUNICATION




Sessional 25 Marks

Unit-I

Linear Modulation schemes: Need for modulation, double side band suppressed carrier (DSB-

SC) modulation, conventional Amplitude Modulation (AM). Hilbert transform, properties of

Hilbert transform. Pre-envelop. Complex envelop representation of band pass signals, In-phase

and Quadrature component representation of band pass signals. Low pass representation of band

pass systems. Single side band (SSB) modulation and Vestigial-side band (VSB) modulation.

Modulation and demodulation of modulation schemes

Unit - II

Angle modulation schemes: Frequency Modulation (FM) and Phase modulation (PM), Concept

of instantaneous phase and frequency. Types of FM modulation: Narrow band FM and wide

band FM. FM spectrum in terms of Bessel functions. Direct and indirect (Armstrong's) methods

of FM generation. Balanced discriminator, Foster–Seeley discriminator and Ratio detector for

FM demodulation. Pre-Emphasis and De-Emphasis. Capture effect.

Unit-III

Transmitters and Receivers: Classification of transmitters. High level and low level AM

transmitters. FM transmitters. Principle of operation of Tuned radio frequency (TRF) and super

heterodyne receivers. Selection of RF amplifier. Choice of Intermediate frequency. Image

frequency and its rejection ratio Receiver characteristics: Double spotting, Tracking and

alignment, Automatic Gain Control.

Unit-IV

Noise Sources and types. Atmospheric noise, Shot noise and thermal noise. Noise temperature.

Noise in two-port network: noise figure, equivalent noise temperature and noise bandwidth.

Noise figure and equivalent noise temperature of cascade stages. Narrow band noise

representation. S/N ratio and Figure of merit calculations in AM, DSB-SC, SSB and FM

systems.

Unit-V

Analog pulse modulation schemes: Sampling of continuous time signals. Sampling of low pass

and band pass signals. Types of sampling. Pulse Amplitude Modulation (PAM) generation and

demodulation. Pulse time modulation schemes: PWM and PPM generation and detection.

Suggested Reading:

1. Simon Haykin, “Communication Systems,” 4/e, Wiley India, 2011.

2. B.P. Lathi, Zhi Ding, “Modern Digital and Analog Communicaton Systems”, 4/e, Oxford

University Press, 2016

3. Herbert Taub, Donald L. Shilling & Goutam Saha, “Principles of Communication

Systems,” 3/e, TMH, 2008.

4. P. Ramakrishna Rao, “Analog Communication,” 1/e, TMH, 2011.

5. A. Bruce Carlson and Paul B. Crilly, “Communication Systems,” 5/e, 2011.

6. Singh, R.P. and Sapre, S.D., “Communication Systems,” TMH, 2007


AUTOMATIC CONTROL SYSTEMS




Sessional 25 Marks

UNIT – I

Control System fundamentals and Components : Classification of control systems including Open and

Closed loop systems, Error sensing devices – potentiometers and Synchros. Mathematical modeling of

mechanical systems and their conversion into electrical systems. Block diagram representation, Block

diagram algebra and reduction and Signal flow graphs and Mason’s gain formula.

UNIT – II

Time Response : Transfer function and Impulse response, types of input. Transient response of second

order system for step input. Time domain specifications. Characteristic Equation of Feedback

control systems Types of systems, static error coefficients, error series,

Stability : Concept of Stability, Routh-Hurwitz criterion for stability, Root locus technique and its

construction.

UNIT – III

Frequency response plots : Bode plots, frequency domain specifications. Gain and Phase margin.

Principle of argument. Nyquist plot and Nyquist criterion for stability.

Compensation : Cascade and feedback compensation. Phase lag, lead and lad-lead compensators. PID

controller.

UNIT – IV

Discrete Control Systems : Digital control, advantages and disadvantages, Digital control system

architecture. The discrete transfer function. Sampled data system. Transfer function of sample data

systems. Analysis of Discrete data systems.

UNIT – V

State space representation : Concept of state and state variables. State models of liner time invariant

systems, State transition matrix, Solution of state equations. Controllability and Observability.

Suggested Reading:

1. Nagrath, I.J, and Gopal, M., “Control System Engineering”, New Age Publishers.

2. Ogata, K., “Modern Control Engineering”, PHI.

3. Gopal, Madam, “Digital control Engineering” New Age Publishers.


COMPUTER ORGANIZATION AND ARCHITECTURE




Sessional 25 Marks

Unit I

Register Transfer Language and Micro operation: Difference between Computer Organization

and Architecture, RTL notation, Common bus system using multiplexer and tri-state buffers.

Micro-operations: Data transfer, Arithmetic, Logical and Shift.

Basic Computer Organization and design: Computer registers, instruction and interrupt cycle and

Design of basic computer. Instruction formats and Addressing modes.

Unit II

Computer Arithmetic: Fixed and floating point numbers: Adders: Binary adder, BCD adder,

carry look ahead adder, twos complement adder/subtractor, Multiplication: Booth’s algorithms,

its HDL description and Array Multiplier. Division: Restoring and Non-restoring algorithms and

their HDL descriptions and Barrel shifter.

Unit III

Control Unit Design: Significance of Control unit, Hardwired Control unit design approach

(classical and one-hot methods). Case studies: CPU. Micro-programmed Control unit approach:

basic concept, micro-program sequencer.

Unit IV

Input Output and Memory Organization: Input-output interface, Modes of transfer: Programmed

I/O, Interrupt I/O and DMA, Priority Interrupt, Input-Output Processor (IOP): CPU-IOP

communication

Memory Organization: Memory hierarchy, Main memory: ROM, MROM, EPROM, EEROM,

flash memory, RAM types, associative memory (CAM), Cache memory, address mapping

techniques, replacement policies, virtual memory.

Unit V

Advances in Computer Organization: RISC, CISC, Parallel processing: Pipeline – Arithmetic

and Instruction, Pipeline Conflicts, Flyn’s classification, VLIW architecture.

Processor Performance enhancement strategies: Overlap, Scalar, Super-scalar, Super-pipeline,

Instruction Level Parallelism (ILP).

Suggested Reading:

1. Morris Mano M, Computer System Architecture, 3rd

edition, Prentice Hall India, 2007.

2. John P. Hayes, Computer Architecture and Organization, 3rd

edition, McGraw Hill, 1998.

3. William Stallings, Computer Organization and Architecture, Design for Performance, 7th

edition, Prentice Hall India, 2006.


Digital System Design with Verilog HDL




Sessional 25 Marks

Unit I

Introduction to HDLs, Overview of Digital Design with Verilog HDL, Basic Concepts, Data

types, System tasks and Compiler Directives. Gate level Modeling, Hierarchical structural

modeling. Dataflow modeling. Continuous Assignments, Timing and Delays. Programming

Language Interface,

Design of Arithmetic Circuits - Using Vectored Signals, Using a Generic Specification, Nets

and Variables, Arithmetic Assignment Statements, Representation of Numbers in Verilog Code,

Gate level and hierarchical modeling of 4-bit Binary and BCD adders and 8-bit Comparators.

Verification: Functional verification, simulation types, Design of stimulus block.

Unit II

Switch Level Modeling and examples. Behavioral Modeling: Structured Procedures, Procedural

Assignments, Timing Controls, and Conditional Statements, multi-way branching, Loops,

Sequential and Parallel blocks, Generate blocks. Tasks, and Functions.

Behavioral/dataflow modeling of basic MSI combinational logic modules: ALUs, Encoders,

Decoders, Multiplexers, Demultiplexers, Parity generator/checker circuits, Bus Structure,

Reaction Timer,

Static timing analysis, Logic synthesis and Register Transfer Level (RTL) Code.

Unit III

Behavioral/dataflow modeling of sequential logic modules: Latches, Flip Flops, counters and

shift registers.

Synchronous Sequential Circuits: Analysis and synthesis of synchronous sequential circuits:

Mealy and Moore FSM models for completely and incompletely specified circuits, State

Minimization - Partitioning Minimization Procedure, sequence detector. One-Hot Encoding.

Synthesizable Verilog HDL models fpr sequence detector using Moore and Mealy models,

Design of a Modulo-8 Counter using the Sequential Circuit Approach and its verilog

implementation. FSM as an Arbiter Circuit.

Unit IV

Algorithmic State Machines (ASMs): ASM chart, ASM block, simplifications and timing

considerations with design example. ASMD chart for binary multiplier and Verilog HDL code,

one hot state controller.

Asynchronous Sequential logic: Analysis procedure-Transition table, flow table, race conditions.

Hazards with design example of Vending-Machine Controller

Unit V

Memory Devices: Types of memories, RAM BJT cell and 6-T MOS RAM cell, organization of a

RAM, Expanding word size and capacity.

Introduction to ASIC’s: Full-custom, standard-cell and Gate array based ASICs. SPLDs: PROM,

PAL, GAL, PLA. FPGA and CPLD simplified architecture and applications. ASIC/FPGA

Design flow, CAD tools. Combinational circuit Design with Programmable logic Devices

(PLDs).

Suggested Reading:

1. Samir Palnitkar, “Verilog HDL A Guide to Digital Design and Synthesis,” 2nd

Edition, Pearson Education, 2006.

2. M. Morriis Mano, Michael D. Ciletti, “Digital Design”, 4th

edition, Pearson

Education.

3. Michael John Sebastian Smith, Application Specific Integrated Circuits, Pearson

Education Asia, 3rd

edition 2001.

Suggested Reference:

1. Michael D. Ciletti, Advanced Digital Design with the Verilog HDL”, PHI, 2005.

2. J. Bhasker, “A Verilog HDL Primer,” 2nd Edition, BS Publications, 2001.


PULSE, DIGITAL AND INTEGRATED CIRCUITS LAB




Sessional 25 Marks

Course Objectives:

1. Perform experiments based on operational amplifier to study its characteristics

2. Perform experiments and analyse the linear and non linear applications of op amps

3. Perform experiments on design of combinational logic circuits using digital ICs

4. Perform experiments on design of sequential logic circuits using digital ICs

Part-A

1. Clipper and Clamper circuits.

2. Measurement of parameters of Op-Amp. Voltage Follower, Inverting and Non Inverting

Amplifiers, Level Translators using Op-Amp.

3. Circuits: Summer, Integrator Differentiator using Op-Amp.

4. Active filters: LP, HP and BP filter design using Op-Amp.

5. Op-Amp Oscillators: Astable, Monostable.

6. Triangular and Square Wave generators, Schmitt Trigger using Op-Amp

7. Applications of 555 Timer.

Part-B

1. Design of Code converters, parity generator and checker circuits using logic gates.

2. Full adders, subtractors using logic gates and multiple bits IC Adder/ Subtractor and

arithmetic Circuits.

3. Mux - Demux applications.

4. Flip-Flop conversions and latches using gates and ICs.

5. Designing Synchronous, Asynchronous up/down counters using ICs.

6. Shift registers and ring counters using IC Flip-Flops & Standards IC counters.

7. Interfacing counters using seven-segment LED display unit.

General Note:

A total of not less that 12 experiments should be carried out during the semester with at least 6

experiments from each part.

Suggested Reading:

1. Ronald J Tocci, Widmer& G L Moss, “Digital Systems: Principles and Applications” PHI10/e,2009

2. D. Roy Chowdhury, B. Jain Shail, Linear Integrated Circuits, 4th Edition.


VERILOG HDL LAB




Sessional 25 Marks

List of Experiments:

Part A

Write the Code using VERILOG, Simulate and synthesize the following:

1. Arithmetic Units: Adders and Subtractors.

2. Encoders, Decoders, Priority Encoder and Comparator.

3. 8 – Bit Parallel Adder using four bit tasks and functions.

4. Arithmetic and Logic Unit with minimum of eight instructions.

5. D, SR and JK Flip flops.

6. Registers/Counters.

7. Sequence Detector using Mealy and Moore type state machines.

Note:

1. All the codes should be implemented appropriately using Gate level, Dataflow and

Behavioral Modelling.

2. All the programs should be simulated using test benches.

3. Minimum of two experiments to be implemented on FPGA/CPLD boards.

Part B

General Note: Mini Project cum Design exercise:

The student must design, develop code and test and design the following problems:

i) 8 bit CPU

ii) Generation of different waveforms using DAC

iii) RTL code for Booth’s algorithm for signed binary number multiplication

iv) MAC unit and DSP modules: FIR and IIR Filter

v) Synchronous and Asynchronous Data transfer, UART and Baud rate generator.

v) Design of 4 - bit thermometer to Binary Code Converter

scheme of instruction and examination be iii...

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