robert barnes utah state university department of electrical and computer engineering thesis...
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DYNAMICALLY RECONFIGURABLE SYSTOLIC ARRAY ACCELERATORS:A CASE STUDY WITH EKF AND DWT ALGORITHMS
Robert BarnesUtah State UniversityDepartment of Electrical and Computer EngineeringThesis Defense, November 13th 2008
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Outline
Introduction & Background System Design Results & Conclusions
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Motivation
Increasing Demands for Spacecraft Low Power
Fault Tolerant
Flexibility
High Performance Solution: FPGA
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General Goals
Flexible Extended Kalman Filter (EKF) System on an FPGA Adaptable to changing performance
requirements (scalable). System adaptable to other algorithms (DWT).
Outperform RAD750 PowerPC
Explore applications of dynamic reconfiguration.
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Kalman Filter
To navigate in space an autonomous spacecraft must accurately estimate its state from noisy measurements.
The filter is very flexible Estimate a system’s state from only a single
sensor Estimate the bias in sensors Determine an unknown system model Predict a future states
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Faddeev Algorithm
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Extended Kalman Filter
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Discrete Wavelet Transform Algorithm
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Systolic Arrays
A network of simple processing elements (PE) which rhythmically process and pass data to nearest neighbours to process larger complex tasks.
Features: Modularity Regularity Locality Synchronous Pipelined Data Reuse
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Partial Dynamic Reconfiguration
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Configuration Layout
Figure Source: Jeff Carver
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Other Reconfiguration Methods
JBits Interface to make changes to the Bitstream
Modular Design Flow Early Access Design Flow
Improved Modular Design Flow
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Scaling Methods
Soft scaling Using conditional variable loops and conditional
statements, software can easily be made to scale to different parameters.
Static Hardware Scaling Using MUXes a hardware architecture can be
designed where data can be re-routed to different hardware cores.
Reconfigurable Hardware Scaling Using partial dynamic reconfiguration the physical
size of the systolic array can be scaled.
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Outline
Introduction & Background System Design Results & Conclusions
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PolySAF
Polymorphic Systolic Array Framework (PolySAF)
Co-Processor
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SwitchBox
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Interface Hierarchy
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2D Fadeev Systolic Array
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Vertical Systolic Array
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Hardware/Software Mapping
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DWT Systolic Array
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Hybrid PDR
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Mapping & Scaling
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Outline
Introduction & Background System Design Results & Conclusions
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Floor Planning
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Floor Planning Sockets
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Sockets vs Problem Size vs Cycles
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Comparison with PowerPC
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Reconfiguration Performance
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Area Analysis
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Conclusions & Limitations
A polymorphic systolic array framework (PolySAF). Programmable switchboxes and protocol to allow dynamic scaling in the
array. Efficient EKF and DWT accelerators
Speedup of at least 4.18x and 6.61x over PowerPC for EKF and DWT. Integration of bitstream relocation and bitstream compression into a
practical system. 2.7x improvement in reconfiguration time.
A 44% improvement in BRAM usage.
The flexible and simple framework allows this design to host a broad range
of algorithms.
Dynamic reconfiguration is powerful, but it is not useful in every application.
The trade-offs must be weighed carefully.
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Questions?
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Publications
R. Barnes and A. Dasu, “Hardware/software Co-designed Extended Kalman Flter on an FPGA,” in The International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2008.
R. Barnes, A. Dasu, J. Carver, and R. Kallam, “Dynamically Reconfigurable Systolic Array Accelerators: A case study with EKF and DWT Algorithms,” Institution of Engineering and Technology (IET) Computers & Digital Techniques. In Review.
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Misc.
Hours: 4.33wks/month*16months*(>40hours/wk)
= ~2771hours
Embedded C: ~6,000
Verilog Code: ~3,222
Python: ~1015
Tools: EDK ISE Modelsim MatLab Xpower PlanAhead Eclipse Simics Python