rhino labs prese4th ntation at fpga camp, santa clara, ca
DESCRIPTION
Presentation by Guy Marom of Rhino Labs at the 4th FPGA Camp in Santa Clara. More details visit http://www.fpgacentral.com/fpgacamp or http://www.fpgacentral.comTRANSCRIPT
FPGA System Design
Challenges and SolutionsGuy Marom
April 6, 2011 1www.rhinolabsinc.com
Agenda
1. Who are we
2. FPGA system design challenges
3. Proposed Solution
4. Concluding remarks
April 6, 2011 2www.rhinolabsinc.com
Who we are
Rhino Labs is a leading supplier of
Integrated Compute Elements (iCE)
We are a Silicon Valley based
manufacture of highly integrated
compute elements
Target markets: networking, T&M,
medical, industrial
Product lines
FPGA based – Today‟s discussion
SoC based (ARM, MIPS64 multi
core solutions)
April 6, 2011 www.rhinolabsinc.com 3
Who we are
Front
Side
Bus
(FSB)
Hub
Interface
SS
SS
SS
SS
SSSS
C
C
C
C
C
C
C
C
C
C
4 PCI-X
busses
Low speed 33MHz
PCI bus
FPGA CPU
MC
H
Memory
Memory
Two (2)
DDR
(Double
Data Rate)
Memory
Busses
I
C
H
Vid
eo
P64H2 HI to PCI
bridge
P64H2 HI to PCI
bridge
Sub-systems
Rhino Labs Engages Customers from
Block diagrams to Certified FPGA
Based Systems
April 6, 2011 4www.rhinolabsinc.com
What is iCE:
Integrated Compute Element
April 6, 2011 5www.rhinolabsinc.com
DDR3
(1GB)
V-6
XC6VLX240T
Platform
flash
NOR flash
I2C EPROM
Clock gen
unit
USB Host/Peripheral
USB / UART
QUAD 10/100/1000
Ethernet
DVI Video
PCIeMGTsGPIOs
System ACEConfiguration I/F
10/100/1000 Ethernet
iCE modules integrates CPUs/FPGAs,
DDR3, Flash, EPROM, clocks, reset,
networking and Standard I/O interfaces in
a small package
FPGA System Design
Challenges
Today’s FPGAs
Highly integrated …
CPU, sram, mem cntl.,
std IPs & I/Fs such as
usb2, PCIe, GE, IOs, …
Huge programmable
fabrics, complex power
paradigm
Allows quick time to
market compared with
ASIC
System Design Challenges
for today’s FPGAs.
Signal Integrity for
DDR3 ….1067 MHz
High speed serial IOs
USB3 ……4.8 Gb/s
4xPCIe v2 …6.4 Gb/s
Ethernet ……10 Gb/s
Cross talk and maintain
clean power distribution
Maintain required air flow
April 6, 2011 6www.rhinolabsinc.com
System design
HW Design
Logic DesignSW Design
Application Logic Design
MFG, bring up and test
Logic Design
Components selection
schematics
SI analysis (pre layout)
Layout (placement &
routing)
Fab and assembly
Design and Fab
Board Bring up and
verifications
BSP
OS porting
Application SW
development
3-6 months Estimated cost: ~$100Ks
Using Standard FPGA System
Design Adds Time and Costs
April 6, 2011 7www.rhinolabsinc.com
Designing a standard T&M application
card – the “standard” way
Example Application #1:
T&M using FPGA
Fast FPGA device – V6 or V7
Associated DDR memory
Fast interfaces – PCIe x4/x8
GE or 10GE – for stand alone
application
Configuration devices
Clocking, Reset, Logic
Software and/or hardware
integration
OS and applications
FPGA
DDR DDR
CONFIG
GE/10GE
PCIe
PWR
Expertise required: HW design, Signal integrity , layout,
FPGA tools, logic design , power design, thermal & temp
analysis, OS/App, HSIO, component sourcing, etc.April 6, 2011 8www.rhinolabsinc.com
Proposed Solution
iCE to save time and cost
Get a head start:• Use an Off-the-shelf iCE
(Integrated Compute
Element) device from Rhino
Labs
• Design a simpler than
originally needed carrier
card
• Focus on logic and SW
applications
• Be in the market 6-9
months earlier
April 6, 2011 9www.rhinolabsinc.com
Example Application #2 :
Network Security Box
SD
Design a network
security unit
• Fast standard
networking
interfaces
1GE/10GE
• management ports
• Logging capabilities
and interfaces
April 6, 2011 10www.rhinolabsinc.com
Network Security Unit
example continued
POW
ER
FPGA/
SoC
DDR
reset
DDR
Quad
GE
Usb
2.0
Flash
Clock
gen
Configuration
mgmt
CF/SD
Network security unit• Design and bring up a
Firewall unit
• FPGA and or SoC
based processing unit
• Fast networking
interfaces (GE/10GE)
• logging and storing
capabilities
April 6, 2011 11www.rhinolabsinc.com
The iCE Approach:
Network Security Unit
POWE
R
CF/SD
Network security unit
• Drop an iCE unit,
connect a simplified
power circuitry
• Focus on your
software application
• Move to production
in a simplified
operation
April 6, 2011 12www.rhinolabsinc.com
System design
HW Design
Logic DesignSW Design
Application Logic
Design
MFG, bring up and test
Logic Design
Components selection
Complete schematics
SI analysis (pre layout)
Layout (placement &
routing)
Fab and assembly
Design and Fab
Board Bring up and
verifications
BSP
OS porting
Application SW
development
80% of work
is done
Significantly reduce
costs and risk.
FPGA System Design: Approach that Saves time and costs
April 6, 2011 13www.rhinolabsinc.com
Recommendations for today‟s
FPGA Systems Design
Using off-the-shelf „Integrated Compute
Element‟ hardware lets the customer focus
on logic design and application software
Establish your manufacturing partner
ideally before design start
Get a partner on board who has extensive
experience in delivering standard modules,
custom subsystems, and certified products
April 6, 2011 14www.rhinolabsinc.com
Concluding Remarks
Today‟s FPGAs are creating challenges
and opportunities for FPGA designers
iCEs can be used as building blocks to
save time and costs
iCE will help you focus more on logic
design and sw application
Thanks April 6, 2011 15www.rhinolabsinc.com