response surface channel modeling · 2012-08-21 · response surfaces •visualize response...

© 2011 ANSYS, Inc. September 14, 2011

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Response Surface Channel Modeling Designer SI & DesignXplorer


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Outline

Product Introductions

• Designer SI

• DesignXplorer

Intro to DOE & Response Surface Modeling

• Response Surfaces

• Sensitivity Plots

• Optimization/tradeoff

• Design simplification

• Defects Per Million Opportunities (DPMO)

Summary


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Designer SI

•Circuit Simulator- Nexxim Engine (transient, fast convolution, statistical and IBIS-AMI circuit simulation) •Integrated Schematic capture and layout tool •Design management front-end linking EM simulation products (HFSS, Q3D, SIwave, ..) •2D quasi-static field solver


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Nexxim Circuit Engine Strengths

Statistical analysis and transient simulation: New features VerifEye and QuickEye provide statistical analysis and fast convolution simulation capabilities. Time-domain simulation using frequency-domain S-parameters: Nexxim's inherent automatic enforcement of passivity and causality to accurately model and simulate physical behavior in the time domain (complex interconnects in signal integrity applications). To address the problem of passivity enforcement for large port count, non-passive S-parameter based models; "Passivity by Perturbation" option. Nexxim also includes the patented "TWA" algorithm. "TWA" will dramatically speed up the State Space fitting procedure often by orders of magnitude. State Space model generation is a critical need for time domain S-parameter simulation. Higher capacity at increased simulation speed: Cutting-edge numerical algorithms provide Nexxim with the capacity and speed to handle simulations of very large transistor/device counts, and high harmonic content without sacrificing simulation accuracy. Robust convergence: Nexxim includes robust algorithms across all analysis domains (DC, time and frequency) that ensure convergence even as circuit size, harmonic content and circuit nonlinearities increase.


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DesignXplorer

DesignXplorer (DX) explores a wide range of responses from a limited number of actual solutions.

It creates Response Surfaces • Allows for optimization and six-sigma studies that include a large number of

variations without requiring a simulation for all variations

DX uses Design of Experiments (DOE) – DOE method determines how many, and which design points should be solved

for the most efficient approach to optimization

– Response surface is fit to solved DOE


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Why Response Surface Modeling?

Response Surface Modeling enables the designer to model and consider all aspects of a high speed channel design. We fit a statistical model to outputs of the design as a function of the change in input variables. A DOE table is used to select design points to solve explicitly for and the statistical model so to speak, “fills in the gaps”

Optimized conditions and worst case scenarios are obtainable within the set of all possible design combinations within a realistic simulation timeframe.

For example consider 30 variables or “factors”, if each variable has only 5 variations or “levels” we are looking at a huge number of possible combinations in order to find optimal solutions and or worst case scenarios.

!!!!530 FactorsLevelsnsCombinatio


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PCIe Channel Example

PCB Board Model

Pad Ball

PCIConnectorPackage 1 Socket

TlineVias Vias

TLines

Package 2PCIBoard

PCIe Gen 3 DOE Channel Simulation

TX

RX

0 0 0 0 0 0 0 0

P2_Pad1_p P2_Pad1_n

P2_Pad2_p2

P2_Pad2_n2

P2_Pad3_n P2_Pad3_p

Pad3_n

Pad3_p

Pad2_p

Pad2_n

Pad1_n

Pad1_p

Ball1_n

Ball1_p

Ball2_n

Ball2_p

Ball3_n

Ball3_p

Pin1

Pin2

Pin3

Pin4

Pin5

Pin6

Pin7

Pin8

Pin9

Pin10

Pin11

Pin12

p1

p3

p5

p7

p9

p11

Die_1n

Die_1p

Die_2n

Die_2p

Die_3n

Die_3p

Pin1

Pin3

Pin5

Pin7

Pin9

Pin11

Pin2

Pin4

Pin6

Pin8

Pin10

Pin12

Pin1

Pin2

Pin3

Pin4

Pin1

Pin2

Pin3

Pin4

Pin1

Pin2

Pin3

Pin4

1

2

3

4

5

6

W103

Pin1

Pin2

Pin3

Pin4

Pin1

Pin2

Pin3

Pin4

Pin1

Pin2

Pin3

Pin4

p1

p3

p5

p7

p9

p11

Die_1n

Die_1p

Die_2n

Die_2p

Die_3n

Die_3p

ID=156

ID=157

ID=158

ID=164

ID=165

1

2

3

4

5

6

W176

1

2

3

4

5

6

W177

Pad3_n

Pad3_p

Pad2_p

Pad2_n

Pad1_n

Pad1_p

Ball1_n

Ball1_p

Ball2_n

Ball2_p

Ball3_n

Ball3_p

ID=187

1

2

3

4

5

6

W190

12 components consisting of multiple design parameters varying from material specific to physical.


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Example of model details

•Trace width and space •Different dielectric regions for fiber skew •Varying degrees of trace etching •Varying dielectric materials •Dielectric thickness

•Via stub lengths •Routing configurations •Via thickness •Anti-pad sizes


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Problem Scale

30 different factors isn’t unreasonable considering an entire PCIe Channel, Example:

Package

• Thickness, Pad breakout, trace length, ball pitch, dielectric material (5)

Socket

• Thickness, material properties, SG via ratio (3)

Board

• MS and SL trace & space, etch factors, Cu roughness, dielectric materials, via config (8)

Connector

• Various vendor models, often only one or two options. (1)

2nd Board

• MS, SL, etch factors, Cu roughness, dielectric materials, via config (8)

2nd Package

• Thickness, Pad breakout, trace length, ball pitch, dielectric material (5)


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DOE Workflow


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Circuit Simulation- HPC


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DOE Methodology


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PCIe Channel Example – DOE Setup


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PCIe Channel Example – DOE Setup


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Response Surfaces

•Visualize response surfaces in 3D or 2D plots (continuous, discreet, mixed) variables •The Measure of fit provides a metric for evaluating the accuracy of the response surface model.

•Eye Height Coefficient of Determination (R-Squared) = 0.9962

•Eye Width Coefficient of Determination (R-Squared).= 0.9891

Provides a measure of how well future Outcomes will be predicted By the statistical model


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Sensitivity Plots

Which variables have the most impact on the output.

• Negative numbers show a decrease impact on output

• Positive numbers show an increase impact on output

Sensitivity plots help us make the decision; which variable in my design offers the most impact changing my eye height or width.

More importantly is shows up which inputs we may consider fixing thus narrowing the data set


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Optimization –Min. EYE Height/Width


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Narrowing the field

At this stage we know two valuable insights;

• which variable set yields the worst case eye

• which of those variables don’t contribute much to this case.

Additional judgment also comes into play here for example:

• Manufacturability

• Cost

We narrow the field of variables and re-run the DOE for improved accuracy.

Minimized to just the Package, Board, and Card T-line lengths


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Sensitivities updated of second DOE

Change in relative significance

Package Length

board Length


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Defect Rate Prediction (DPMO)

If we cannot achieve an acceptable design on one or more of our output criteria we need to determine whether or not our design can meet a specific defect rate target in this case, 1000ppm.

For this case we will leave the design in the worst case and see how it does in the six sigma analysis for DPMO (Defects Per Million Opportunities) or ppm ( parts per million)


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6-Sigma Distribution functions

Plots showing the normal probability distribution and Cumulative distribution functions for Eye Width and Eye Height.


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Distribution Characteristics


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DPMO

•Eye Height at worst case is with in the PCIe spec at 25mVPP •Eye Width simulation shows possible violations of 0.3(UI) with a Sigma Level of 3.259 •With a Sigma Level at 3.259 corresponding to 559 DPMO were within our 1000DPMO goal!!


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Summary

Response Surface Modeling enables the designer to model and consider all aspects of a high speed channel design.

optimized conditions and worst case scenarios are obtainable within the set of all possible design combinations within a realistic simulation timeframe.

Using a cohesive tool set such as Designer SI and DesignXplorer improves simulation time, and reduces operator error.

Designer Si as the circuit simulation tool directly linked to electromagnetic models yields the highest possible accuracy.

Transient, statistical transient, peak distortion analysis, and equalization schemes are all inclusive within the Designer environments and can be part of the DOE, “improves goodness of fit R^2”


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Summary of tools

Designer SI Circuit

HFSS SOD

DesignXplorer

HPC pack

response surface channel modeling · 2012-08-21 · response surfaces •visualize response...

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