Reliability and Yield of MOS Devices and Circuits

Prof Gilson Wirth

UFRGS - Porto Alegre, Brazil

This set of slides is a summary of the lecture. The lecture may be tailored to the

needs and interest of the audience, and composed by a larger set of slides.

The lecture covers new phenomena which play a role on the performance and

reliability of highly scaled MOS devices. Performance and reliability become

influenced also by factors other than physical dimensions.

Furthermore, variations of parameters over time (aging and transient effects such

as noise and soft errors) may lead to dramatically increased overhead in the

timing budget, as well as on test procedures.

We need to understand the underlying physical mechanisms, and develop analysis

and modeling techniques to support IC designers.

Among the effects discussed in this lecture, the major ones are:

- Parametric variability due to effects such as random dopant fluctuations and line

edge roughness.

- Aging effects such as Bias Temperature Instability (BTI), Hot Carrier Injection

(HCI), Electromigration and Time Dependent Dielectric Breakdown (TDDB).

- Radiation Effects, such as Single Event Transients (SET) and Single Event

Upsets (SEU).

- Device intrinsic noise, with focus on the Random Telegraph Signal (RTS).

A short CV and list of publications may be found at

http://lattes.cnpq.br/1745194055679908

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Issues in Nano-Scale Technologies

Electrical Behavior / Parameter Variation

Spatial Temporal

Designer must consider both Process and Temporal Variations

Random:

RDF, LER, etc

Systematic:

Process

Gradients, etc

Aging:

NBTI, HCI,

Electrom., etc

Transient:

SET/SEU, Noise, etc

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Issues in Nano-Scale Technologies

Transient Error

MinimumAcceptable

Performance

AverageSpeed

Time

Perf

orm

an

ce

Permanent Failure

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Issues in Nano-Scale Technologies

Transient Error

MinimumAcceptable

Speed

Time

Sp

eed

Permanent Failure

Variability

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Sources & Types of VariationsSources & Types of Variations

<Lg> and <W>, <layer thicknesses>,

<R>’s, <doping>, <tox>, <Vbody>

Process

Line Edge Roughness (LER), Discrete doping,

Discrete oxide thickness, R and Vbody distributions

Environment

Operating temperature range,

VDD range

Self-heating, Hot spots,IR drops

Globalor

Cor-rela-ted

LocalOr

Ran-dom

Temporal

<NBTI> and <HCI>

Distribution of NBTI, HCI, Noise,

Radiation Eff. (SET/SEU),Oxide breakdown currents

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Sources & Types of VariationsSources & Types of Variations

<Lg> and <W>, <layer thicknesses>,

<R>’s, <doping>, <tox>, <Vbody>

Process

Line Edge Roughness (LER), Discrete doping,

Discrete oxide thickness, R and Vbody distributions

Environment

Operating temperature range,

VDD range

Self-heating, Hot spots,IR drops

Globalor

Cor-rela-ted

LocalOr

Ran-dom

Temporal

<NBTI> and <HCI>

Distribution of NBTI, HCI, Noise,

Radiation Eff. (SET/SEU),Oxide breakdown currents

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Long Range x Short Range Variations

VT

Fre

quency

VT

Fre

quency

Long Range

Variation in VT

Short Range

Variation in VT(also mismatch in

analog circuits)

Different Averages

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Different Types of Process Variation

Total Parameter Variation

Systematic Random

Layout and

Neighborhood

Dependent

Systematic

Across Chip

Intra-Die Inter-Die

Short range

Mismatch

Random

Across Chip

After Saxena et al, IEEE-TED 2008

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Systematic x RandomSystematic x Random

130 nm: Systematic 90 nm: More Random

Ring Oscillator Freq VariabilityNeuberger, Wirth el al. ESSCIRC 2006.

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Systematic VariationsSystematic Variations

Example of Layout Dependent Systematic Variations:CMP affects dense areas of lines differently than sparsely populated areas of lines.

Design Measure: Regularity and Dummies also in Digital Circuits

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250 180 130 90 65 45 nm

Defect limited

yield

Parametric limited

yield

250 180 130 90 65 45 nm

Defect limited

yield

Parametric limited

yield

hard fails, screenablesoft fails, sensitive to Temp / Vdd / f ,difficult to screen

Random VariationsRandom Variations

σσσσ / µµµµ ≈ (Area)-0.5

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Variability Increases with ScalingVariability Increases with Scaling

Current-ratio variability of 10:1 current mirror for 130-nm, 90-nm, and 65-

nm technologies [Bernstein et al., IBM J. RES. & DEV., 2006].

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Pessimistic Design Hurts PerformancePessimistic Design Hurts PerformanceP

erfo

rman

ce

Technology generation

Is This Worth a Huge

Investment?

Average Performance

Worst Case

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Optimistic Design Hurts Reliability & YieldOptimistic Design Hurts Reliability & Yield

- Parametric Yield Loss- Wear Out Before End of Expected Product Life Time

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Random Process VariationsRandom Process Variations

RDF: Random Dopant FluctuationsLER: Line Edge Roughness

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RDF: Random RDF: Random DopantDopant FluctuationsFluctuations

The simulationParadigm now A 22 nm MOSFET

In production 2009

A 4.2 nm MOSFETIn production 2023A Asenov et al., IEEE-TED 2003

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LER: Line Edge RoughnessLER: Line Edge Roughness

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Parameters become Random Variables Parameters become Random Variables

[Source: S. Y. Borkar, Intel, 2004]

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Power Power xx TimingTiming

[Source: S. Y. Borkar, Intel, 2004]

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Too

leaky

Too

slow

Pro

bab

ilit

y

Vt

Good

chips

Power Power xx TimingTiming

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AgingAging

NBTI: Negative Bias Temperature InstabilityShifting of PMOS Vt over time, reducing On Current

HCI: Hot Carrier InjectionShifting on NMOS Vt over time, reducing On Current

ElectromigrationIncrease of Interconnect Resistance (or Rupture)

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HCI: Hot Carrier StressHCI: Hot Carrier Stress

Noise relevance of traps

Hot carrier stress generates additional trap states near to the drain:

- Locally shifts Vt at the drain side.

- Is also a source of noise.

Source: R Brederlow, PhD Thesis

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HCI: Hot Carrier StressHCI: Hot Carrier Stress

Drain voltage - effective gate voltage [V]

0.0 0.5 1.0 1.5

Ch

an

ge

s in

ga

te r

efe

rre

dvo

lta

ge

no

ise

[%

]

101

102

103

Ch

an

ge

s in

dra

in c

urre

nt [%

]100

101

102

Stress @ Vg=1.2V, Vd=5.5V

n-MOS W / L = 15µm / 0.75µmCharacterization @ Vg= 1.2V

105 s

3x104 s

HCI in NMOS: Reduced On Current and Increased Noise.

Source: R Brederlow, PhD Thesis

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NBTI: Negative Bias Temp InstabilityNBTI: Negative Bias Temp Instability

-Vt increases over time- Ids reduces affecting PMOS Speed.

Source: K Kang et al., IEEE ICCD 2006

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Design Centering Over Product LifetimeDesign Centering Over Product Lifetime

NBTI-Aware Technique for Transistor Sizing of High-Performance CMOS Gates.M da Silva, V Camargo, L Brusamarello, G Wirth and R da Silva. LATW 2009

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HCI and NBTIHCI and NBTI

• Note that these effects are also history dependent, varying according to total time spent in the 'on' or 'off' state.

• Associated with the average threshold shift, there are also random shifts.

• Even for identical use conditions and devices, there are mismatch shifts due to random variations in the number and spatial distribution of the charges/interface states formed.

• Small gate area devices will experience more random mismatch.

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ElectromigrationElectromigration

• Particularly likely to affect the thin tightly spaced interconnect lines of deep-submicrometer design.

• Difficult to be prevented by product testing.• Main cause: generation of stress in the grain boundaries and

interfaces.

Common Failure Modes:Grain Boundaries andInterfaces.

M. A. Meyer and E. Zschech,

Proc. 9th Int. Workshop

Stress Induced Phenom.

Metallization, 2007.

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Transient FaultsTransient Faults

Radiation Effects:SET: Single Event TransientSEU: Single Event Upset

RTS: Random Telegraph Signal

Signal Integrity Issues (e.g., Noise Coupling, Substrate Noise Coupling, etc).

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Radiation EffectsRadiation Effects

Please clic on Fig to run movie

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Radiation EffectsRadiation Effects

OUT (Vdd)

PMOS

NMOS

VDD

IN (GND)

CNODE

IP

IC

ID

10

OUT (Vdd)

PMOS

NMOS

VDD

IN (GND)

CNODE

IP

IC

ID

10

Charge Collection Mechanism

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SET in Combinational LogicSET in Combinational Logic

1

1

1

0

1

1

0

0

0

1 0

1 0

1 0

1 00 10 1

1

Particle

strike

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SEU in Sequential LogicSEU in Sequential Logic

1 0OF

F

OF

F

PN N

gnd

OF

F

OF

F

0 1

BIT-FLIP

ionization

P

WL WL

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Sequence of Events from Ionization to FailureSequence of Events from Ionization to Failure

+

-+-

-+-

+

+-

+-

ionization Transient current (injected or extracted from

the junction)

Transient voltage pulse(capacitor node) clk

BIT-FLIP ERROR

FAULT FAULT EFFECT

FAILURE

Sensors(detection)

Time redundancy(detection, mitigation)

Hardware redundancy

Error correcting codes(detection and mitigation)

Fault tolerant techniques

Self-checking mechanisms with recovery

Recomputation(detection and mitigation)

Redundancy

/ Spare components

Error latencyFault latency

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BulkBulk--BICSBICS

gnd

+ +- --

α particles

protons,

heavy ions

ionization

Bulk-

BICS

Bulk-

BICS

VDD

+

Wirth et al., IEEE Micro, 2007

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RTS: Random Telegraph SignalRTS: Random Telegraph Signal

Inversion layer

Trap

Gate Oxide

Interaction with the inversion layerDrain Current ID

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RTS: Random Telegraph SignalRTS: Random Telegraph Signal

Leads to modulation of the local mobility and number of free carriers in the channel

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Variability: Dependency on Circuit BandwidthVariability: Dependency on Circuit Bandwidth

1 10 100 1000 100002,5

3,0

3,5

4,0

4,5

5,0

5,5

6,0

σnp/<

np

BW

>

fH/f

L

G Wirth et al. IEEE Trans Electron Dev, 2007

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RTS: Random Telegraph SignalRTS: Random Telegraph Signal

f(log)

S(lo

g)

Time

Cu

rre

nt

τe

τc

δΙd

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RTS and RTS and DigitalDigital CircuitsCircuits

VT Fluctuations

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RTS and RTS and DigitalDigital CircuitsCircuits

VT Fluctuations

+ -

∆∆∆∆VT

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RTS in SRAMRTS in SRAM

RTS causes instability issues on SRAM memoriesRTS impact on cell characteristics: far from Normality

Accurate Model for RTS noise in digital circuits: Statistical RTS model for digital circuits. L Brusamarello, G Wirth and R da Silva. Microelectronics Reliability, 2009.

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RTS: Erratic Fluctuations of SRAM Cache RTS: Erratic Fluctuations of SRAM Cache

VminVmin at the 90nm Process Technology Nodat the 90nm Process Technology Nodee

Source: M Agostinelli et al. (Intel), IEDM 05

Vmin on some SRAM arrays varied from one measurement to the next.

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RTS in CMOS Image Sensor PixelsRTS in CMOS Image Sensor Pixels

Source: X Wang, P R Rao, A Mierop, A Theuwissen. IEDM 06.

Temporal output behavior of pixels

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RTS Flash MemoriesRTS Flash Memories

FANTINI et al. IEEE-EDL December 07

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Signal Integrity IssuesSignal Integrity Issues

Crosstalk Noise:Due to electromagnetic coupling between Signal Lines.

Power/Ground Noise:Due to Simultaneous Switching of Many Gates.

Substrate Noise:Signal can couple from one node to another via thesubstrate.

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Could Variability & Could Variability & ReliabReliab. . CostCost BecomeBecomeShow Stopper ?Show Stopper ?

Technology Node

Co

st

Cost per Transistor

Reliability Cost

TotalProduct Cost

ScalingNot Profitable

High-cost reliability solutions (increased design cost, increased silicon area, etc) and service may lead to unacceptable costs.

Based on T Austin et al., IEEE D&T of Comp., 2008.

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Technology Node

Co

st

Cost per Transistor

Reliability Cost

TotalProduct Cost

Need for New Low-Cost, Resilient Design Methodologies

Based on T Austin et al., IEEE D&T of Comp., 2008.

Could Variability & Could Variability & ReliabReliab. . CostCost BecomeBecomeShow Stopper ?Show Stopper ?

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HW & SW Techniques for Enhancing HW & SW Techniques for Enhancing ReliabReliab..

SW

HW

Application

Operating Sys

BIOS

Intercon. & I/O

Memory

Logic

Check-point and Roll Back,

Application Replication & SW

Voting, Robust Data Structures,

Memory Management, etc.

Space, Time and Information

Redundancy & HW Voting.

Sense & Correct.

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Issues for TestIssues for Test

- Traditional Go-Don’t Go Test (usually intended toscreen hard failures, not Adequate

- Burn-In and Iddq Test Challenged by Leakage Currents- Complex Aging Mechanisms

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ConclusionConclusion

• Process parameter variations and variations of parameters over time (both aging and transient) are very important in Nano-scale technologies• Tools for automated estimation of yield and reliability are mandatory• New design methodologies to assure yield and reliability are required• New test methodologies to coupe with parametric and transient failures needed• It is needed to simultaneously address power, speed and reliability constraints• Proper process eng., modeling, simulation and design can lead to high yield and reliability.

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Bibliography (to be completed)Bibliography (to be completed)

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Reliability Prediction Methodology Accounting for Multiple SBD and Wear Out”, IEEE TED, VOL. 56,

NO. 7, pp. 1424- 1432,JULY 2009.

•Tibor Grasser and Ben Kaczer, “Evidence That Two Tightly Coupled Mechanisms Are Responsible

for Negative Bias Temperature Instability in Oxynitride MOSFETs”, IEEE TED, VOL. 56, NO. 5, pp.

1056-1062, MAY 2009.

•W Wang, V Reddy, A Krishnan, R Vattikonda, S Krishnan Y Cao, “Compact Modeling and

Simulation of Circuit Reliability for 65-nm CMOS Technology”, IEEE TDMR, VOL. 7, NO. 4, pp. 509 -

517, DECEMBER 2007.

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& Test of Computers, pp. 322-333, July/August 2008.

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1837-1852, SEPTEMBER 2003.

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“Quantitative Evaluation of Statistical Variability Sources in a 45-nm Technological Node LP N-

MOSFET”, IEEE TED, VOL. 29, NO. 6, pp. 609-611, JUNE 2008.

•A Datta, S Bhunia, S Mukhopadhyay and K Roy, “Delay Modeling and Statistical Design of

Pipelined Circuit Under Process Variation”, IEEE-TCAD, V. 25, NO. 11, pp. 2427-2436, NOV. 2006.

•Q Chen, H Mahmoodi, S Bhunia and K Roy, “Efficient Testing of SRAM With Optimized March

Sequences and a Novel DFT Technique for Emerging Failures Due to Process Variations”, IEEE

TVLSI, VOL. 13, NO. 11, pp. 1286-1295,NOV. 2005.

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•G Formicone, M Saraniti, D Vasileska and D Ferry, “Study of a 50-nm nMOSFET by Ensemble

Monte Carlo Simulation Including a New Approach to Surface Roughness and Impurity Scattering in

the Si Inversion Layer”, IEEE TED, VOL. 49, NO. 1, pp. 125-132, JANUARY 2002.

• Saxena et al., “Variations in Transistor Performance and Leakage in Nanometer-Scale

Technologies”, IEEE TED, V. 55, No. 1, pp. 131-144, January 2008.

• Bernstein et al., “High-performance CMOS variability in the 65-nm regime and beyond”, IBM J.

RES. & DEV., pp. 433-449, 2006.

• S Borkar, “Designing Reliable Systems from Unreliable Components: The Challenge of Transistor

Variability and Degradation”, IEEE Micro, pp. 10-16, 2005.

• K Agarwal and S Nassif, “Characterizing Process Variation in Nanometer CMOS”, DAC 2007, pp.

396-399, 2007.

• K Kang, H Kufluoglu, M Alam and K Roy, “Efficient Transistor-Level Sizing Technique under

Temporal Performance Degradation due to NBTI”, ICCD 2006, pp. 216, 221, 2006.

• Ehrenfried Zschech et al., “Geometry and Microstructure Effect on EM-Induced Copper

Interconnect Degradation”, IEEE TDMR, VOL. 9, NO. 1, pp. 20-30, MARCH 2009.

• M. Agostinelli et al., “Erratic Fluctuations of SRAM Cache Vmin at the 90nm Process Technology

Node”, IEDM 2005,

• X Wang, P Rao, A Mierop and A Theuwissen, “Random Telegraph Signal in CMOS Image Sensor

Pixels”, IEDM 2006.

• G WIRTH, R da SILVA; R BREDERLOW. “Statistical Model for the Circuit Bandwidth Dependence

of Low-Frequency Noise in Deep-Submicrometer MOSFETs”. IEEE TED, v. 54, p. 340-345, 2007.

• R da SILVA,; G WIRTH; L BRUSAMARELLO. “An appropriate model for the noise power spectrum

produced by traps at the Si-SiO2 interface: a study of the influence of a time-dependent Fermi level”.

Journal of Statistical Mechanics. Theory and Experiment, v. 2008, p. P10015, 2008.

• WIRTH, G. I. ; VIEIRA, Michele G ; HENES NETO, Egas ; KASTENSIMIDT, Fernanda G L .

Modeling the sensitivity of CMOS circuits to radiation induced single event transients.

Microelectronics Reliability, v. 48, p. 29-36, 2008.

54 Gilson Wirth

• WIRTH, G. I. ; VIEIRA, Michele G ; KASTENSIMIDT, Fernanda G L . Accurate and Computer

Efficient Modelling of Single Event Transients in CMOS Circuits. IEE Proceedings. Circuits, Devices

and Systems, v. 1, p. 137-142, 2007.

•BRUSAMARELLO, Lucas ; SILVA, Roberto da ; WIRTH, G. I. ; REIS, Ricardo Augusto da Luz .

Probabilistic Approach for yield analysis of dynamic logic circuits. IEEE Transactions on Circuits and

Systems. I, Regular Papers, v. 55, p. 2238-2248, 2008.

•WIRTH, G. I. ; SILVA, Roberto da . Low-Frequency Noise Spectrum of Cyclo-Stationary Random

Telegraph Signals. Electrical Engineering (Berlin), v. 90, p. 435-441, 2008.

•HENES NETO, Egas ; WIRTH, G. I. ; KASTENSIMIDT, Fernanda G L . Mitigating Soft Errors in

SRAM Address Decoders Using Built-in Current Sensors. Journal of Electronic Testing, 2007.

•WIRTH, G. I. . Bulk Built In Current Sensors for Single Event Transient Detection in Deep-

Submicron Technologies. Microelectronics Reliability, v. 48, p. 710-715, 2008

•HENES NETO, Egas ; RIBEIRO, Ivandro ; VIEIRA, Michele G ; WIRTH, G. I. ; KASTENSIMIDT,

Fernanda G L . Using Bulk Built-in Current Sensors in Combinational and Sequential Logic to Detect

Soft Errors. IEEE Micro, USA, v. 26, p. 10-18, 2006.

•SILVA, Roberto da ; WIRTH, G. I. ; BREDERLOW, Ralf . Novel analitical and numerical approach to

modelling low-frequency noise in semiconductor devices. Physica. A, Inglaterra, v. 362, n. 2, p. 277-

288, 2006.

•WIRTH, G. I. ; KOH, Jeongwook ; SILVA, Roberto da ; BREDERLOW, Ralf ; THEWES, Roland .

Modeling of Statistical Low-Frequency Noise of Deep-Submicron MOSFETs. IEEE Transactions On

Electron Devices, USA, v. 52, n. 7, p. 1576-1588, 2005.

•WIRTH, G. I. ; SILVA, Roberto da ; KOH, Jeongwook ; THEWES, Roland ; BREDERLOW, Ralf .

Noise and Fluctuations in Deep-Sub-Micron MOSFETs. Journal Of Integrated Circuits And Systems,

Brazil, n. In Press, 2005.

• G Wirth, R da Silva, P Srinivasan, J Krick and R Brederlow, “Statistical Model for MOSFET Low-

Frequency Noise under Cyclo-Stationary Conditions”, IEDM 2009.