regarding rz/t1 mpu(cortex
TRANSCRIPT
© 2017 Renesas Electronics Corporation. All rights reserved. R01TU0175EJ0100
Regarding RZ/T1 MPU(Cortex®-R4)
2017/7/3
Industrial System Solution Department
Industrial Automation Business Division
Industrial Solution Business Unit
Renesas Electronics Corporation
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■A Summary of MPU(Memory Protection Unit)(1/2)
● In ARM® Cortex®-R4 used in RZ/T1, there are 12 region (Region 0~11) which can be programed as MPU region.
● Memory type (cacheability, memory accessing order, etc) can be programed Individually for each MPU region.
It can be programed to control memory access of each MPU region, protect memory region from unintended unauthorized access.
When MPU is in effective, any access to an address that is not mapped to an MPU region generates a Background fault memory abort.
Remark Cortex®-M3 also has its own MPU and it needs different setting.
That MPU setting for Cortex-M3 is omitted in this document.
Specified Base Address, Size
Region 0
Region 1
Region 3
Program region A
Program region B
Peripheral
I/O region
Cache enabled (high speed),
Full access
Cache disabled (Shared with another CPU),
Full access
No instruction fetches enabled
(Malfunction prevention),
Full access
Access restricted region
No instruction fetches enabled
(Malfunction prevention),
Privileged read-only (Protection)
Region 2
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■ A Summary of MPU(Memory Protection Unit)(2/2)
●Two or more overlapping regions can be programmed, and the programed attributes of the biggest region number will be applied.
Also every region has subregions which can be disabled individually, so that the attribute of below layer or background can be applied.
●By register setting, the address that is not in region defined in any of the MPU region program can be applied with default memory map.
Region 0
Region 3
Disabled subregion
of Region3
Accessed with attribute
programed by Region3 in
which its priority is the highest
For this subregions of
Region3 is disabled,
accessed with attribute
programed by Region0
Accessed with attribute
programed by Region0
Subregion0 The least significant addresses
Each sized are equal
Subregion7 The most significant addresses
The subregions is divided into 8 equal sized region.
Each subregions (0~7) can be Individually.
Memory Map
Default memory map
Default memory map could be applied to
a space where no Region is defined
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0000 0000h
4000 0000h
6000 0000h
8000 0000h
A000 0000h
C000 0000h
F000 0000h
FFFF 7FFFh
■The Default Memory Map
● As will be mentioned later, by setting BR bit of the System Control Register (SCTLR) to "1", the address that is not specified with
any of Region 0~11 can be applied with the Default Memory Map pre-fixed as below.
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■How to set MPU(Abstract)
By Settings to System Control Co-processor Registers as below, MPU be enabled.
Setting can only be done in Privileged modes (like SVC, SYS or IRQ modes that are not the User modes).
Refer to ARM Architecture Reference Manual for detailed information of each registers.Refer to RZ/T1 Group Initial Settings(R01AN2554)for sample of practical settings.
Remark:
Before MPU is enabled, cache cleaning and disabling are necessary.Refer to RZ/T1 Group Initial Settings(R01AN2554)for detailed information.
1. Select target region by writing its memory region number to MPU Region Number Register(RGNR).
2. Set base address with MPU Data Region Base Address Register(DRBAR).
3. Set region attributes with MPU Data Region Access Control Register(DRACR).
4. Set region size and either enable or disable with MPU Data Region Size and Enable Register(DRSR).
5. Repeat step 1. ~ 4. for setting of other regions.
6. Grant the permission of operation of MPU by M bit of the System Control Register(SCTLR).
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■How to set MPU(1/9)
1. Select target region by writing its memory region number to MPU Region Number Register(RGNR)
Coding format of instruction: mcr p15, 0, <Rd>, c6, c2, #0
●Region [3:0]
Select target MPU region number to be defined. For RZ/T1, 0~11 can be used.
Region 0 Use 0 for Region bit of this register to program Region 0 settings.
reserved Region
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■How to set MPU(2/9)
2. The base address is defined by the MPU Data Region Base Address Register (DRBAR).
Coding format of instruction: mcr p15, 0, <Rd>, c6, c1, #0
●Region Base Address [31:5]
Set the base address of MPU region to be defined.
The base address must be aligned to the region size.
Region
The base address of a region selected by
current RGNR register will be set.
Region Base Address reserved
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■How to set MPU(3/9)
3. The memory attributes and the access control is defined by the Data Region Access Control Register(DRACR).
Coding format of instruction: mcr p15, 0, <Rd>, c6, c1, #4
● Execute Never bit, XN[12]
Region can contain executable code(XN=0)or region is an Execute never region (XN=1) is available for this setting.
Any attempt to execute an instruction from an Execute never region results in a Permission fault.
reservedreserved reserved
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■How to set MPU(4/9)
●Access Permissions field, AP[10:8]
Below attributes are available for each MPU regions.
AP[10:8] Privileged permissions *1 User permissions Description
b000 No access No access All accesses generate a Permission fault
b001 Read/Write No access User mode accesses generate Permission faults
b010 Read/Write Read-only User mode write accesses generate Permission faults
b011 Read/Write Read/Write Full access
b101 Read-only No access Privileged read-only, all other accesses generate Permission faults
b110 Read-only Read-only All write accesses generate Permission faults
note1 : Denotes access in Privileged modes
● Shareable bit, S[2]
Available for Normal memory regions only.
Shareable. (S=1): Non-cacheable. Available for a shared memory accessed from multiple core and such, to keep its coherency.
Non-shareable (S=0): Cacheable.
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■How to set MPU(5/9)
●TEX[5:3], C[1], and B[0] encodings
MPU region can be defined by combination of these setting as below.
TEX [5:3] C [1] B [0] Description Memory Type Shareable?
b000 0 0 Strongly-ordered Strongly-ordered Shareable
b000 0 1 Shareable Device. Device Shareable
b000 1 0 Outer and Inner Write-Through, no Write-Allocate Normal Depends on S bit
b000 1 1 Outer and Inner Write-Back, no Write-Allocate Normal Depends on S bit
b001 0 0 Outer and Inner Non-cacheable Normal Depends on S bit
b001 1 1 Outer and Inner Write-Back, Write-Allocate Normal Depends on S bit
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■How to set MPU(6/9)
● Memory attributes
Normal ・・・ Cacheable (except for the setting of S bit = 1 (Shareable) as mentioned later), Bufferable.
Generally used for program region for running in high speed.
Device ・・・ Non-cacheable, Bufferable, Coherence always kept for order of memory access.
Generally used for a peripheral I/O region where order of memory access must be kept.
Strongly-ordered ・・・ Non-cacheable, Non-bufferable, order is always kept for (R/W) access.
Access performance will reduce for the write buffer is been disabled, but R/W ordering will be more precise.
Notes A memory attributes of TCM region will disregard the ones defined by MPU. Except for a access permission defined by MPU.
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■How to set MPU(7/9)
4. Set region size and either enable or disable with MPU Data Region Size and Enable Register (DRSR).
Coding format of instruction: mcr p15, 0, <Rd>, c6, c1, #2
●Subregion Disable[15:8]
Each bits corresponds to a subregion 0~7 that MPU region is divided equally to. Bit 8 corresponds to the subregion 0.
Bit value=0: Subregion is part of this region (enabled).
Bit value=1: Specified subregion is disabled. The subregion is not part of this region
8Subregion0 The least significant addresses
Each sized are equal
15Subregion7 The most significant addresses
reserved SubregionDisable
reserved RegionSize
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■How to set MPU(8/9)
●Region Size[5:1]
Indicates the size of the current memory region.
●EN bit[0]
MPU Status of region is set. Region is disable after the RESET.
EN=0: Defined region is disabled
EN=1: Defined region is enabled
Setting value Size indicated
b00100 32Byte
b00101 64Byte
b00110 128Byte
b00111 256Byte
b01000 512Byte
b01001 1KByte
b01010 2KByte
Setting value Size indicated
b01011 4KByte
b01100 8KByte
b01101 16KByte
b01110 32KByte
b01111 64KByte
b10000 128KByte
b10001 256KByte
Setting value Size indicated
b10010 512KByte
b10011 1MByte
b10100 2MByte
b10101 4MByte
b10110 8MByte
b10111 16MByte
b11000 32MByte
Setting value Size indicated
b11001 64MByte
b11010 128MByte
b11011 256MByte
b11100 512MByte
b11101 1GByte
b11110 2GByte
b11111 4GByte
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■How to set MPU(9/9)
6. The operation of MPU is authorized by M bit[0] of System control registers(SCTLR).
Coding format of instruction: mcr p15, 0, <Rd>, c1, c0, #0
●M bit[0]
MPU will be in operation when set to "1"
Remark BR bit[17]: By setting to "1", MPU background region is enabled and default memory map is applied to those address that is
not defined in any of MPU regions.
Notes: Those bits that are not mentioned below are omitted in this document.
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Setting examples for sample program of RZ/T1 Group Initial Settings
For detailed information including example of program, Please
refer to RZ/T1 Group Initial Settings(R01AN2554).
● For the Extended internal SRAM, the SPI multiple I/O bus
space and such that need high speed access, Normal
attribute is used. If needed, enabling cache is possible.
● Because CS4, CS5(including their mirror apace)are not used,
Execute Never attribute is used to prevent from run by accident.
● Peripheral I/O register region is set to Device space to prevent
the sequence of Write/Read access to be mixed or omitted.
Also fetching instruction code is disabled.
27FF FFFFH
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■Write buffers
Cache controller of Cortex-R4, in addition to writing to a cache memory, also has write buffer that could hold data
which access to the AXI bus. Even in the case of a cache disabled, it also improves performance of write access of
Normal attribute, and Device attribute memory by write buffer.
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■Notes concerning MPU
1) In the case of writing to external NOR flash ROM, etc., …
In Cortex-R4, the write buffer becomes enabled if the attributes of that region was defined as Normal or Device by MPU, but in the
case of writing to an external memory, the writing the correct data may fail due to the unintended buffering ha occurred.
In any time to write to the external memory, please follow either one of the procedure listed below.
1. Disable write buffer by defining memory attributes as Strongly-ordered.
2. Right after the every time writing instruction code has been executed, issue DMB instruction code to drain write buffer.
(In this case, it would not be a problem if the memory attributes was either Normal or Device)
2) If the memory attributes are either Device or Strongly-ordered, abort will be generated when an Unaligned access is detected.
3) When defining region by MPU, the base address must be a multiple of its size. If this requirement was not met the operation of MPU is not guaranteed.
© 2017 Renesas Electronics Corporation. All rights reserved. R01TU0175EJ0100
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