recent development and progress in nonvolatile memory for ...€¦ · mirrorbit® cell (5f2 per...

7/23/2012

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Recent Development and Progress

in Nonvolatile Memory

for Embedded Market

Saied Tehrani, Ph.D.

Chief Technology Officer, Spansion Inc.

July 11, 2012

2

Outline

NOR Flash

− Standalone

− Embedded in SOC

NAND Flash

− Status and Market Needs

− NAND Scaling Challenges

− Lithography Gaps

Summary

Market Trend for Nonvolatile Memory

Other Nonvolatile Technologies

− Phase Change Memory

− Resistive RAM

− MRAM

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3

Total Flash Market

Source: iSupply

$0

$5,000

$10,000

$15,000

$20,000

$25,000

$30,000

$35,000

$40,000

$M

4

Ultra Light and Thin Laptops

Enabling Innovation

“1,000 Songs in Our Pocket”

Music and Phone in One Device

Solid State Drive to Replace Hard Drives

Smart Phone – Phone, Media & Internet

Tablets – Ebook + Browsing Platform

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Enabling Disruption

Music

Phone

Storage

eBook

Data Storage

Personal Computing

6

Flash Memory for Every Design Need

Performance

(Parallel NOR)

System Cost

(Serial NOR)

Density

(NAND)

Fast Read for Fast

Code / Data Access

Better Reliability

Interactivity and

Boot Times

High Density / Low Cost

Compromised Reliability

Data Storage

Low Density / Fewer Pins

Better Reliability

Serial Slow Access

Code Boot

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Auto Infotainment Set-top Box / TV Communications

NOR and NAND Flash for Embedded Market

Multi-language interfaces, rich graphics, user configuration data

Parallel NOR for fast boot

Embedded SLC NAND data storage

Internet and app support drives larger software requirements

Serial NOR for fast boot

Embedded SLC NAND for reliable application storage

Multi-mode base stations drive increased software complexity

Parallel NOR for fast boot

Embedded SLC NAND data storage

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Outline

NOR Flash

− Standalone

− Embedded in SOC

NAND Flash




Summary




− Resistive RAM

− MRAM

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9

Embedded NOR Flash TAM

$1,500

$2,000

$2,500

$3,000

$3,500

2011 2012 2013 2014 2015 2016

$M

Source: iSupply

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NOR Flash Memory Cell – MirrorBit® Technology

Core Gate

CoSi

ONO MirrorBit®

Tunnel Oxide Proprietary

Storage Medium N+ N+

p-substrate

Gate Top Oxide

MirrorBit cell stores charge in two physically different locations

Non-conducting storage dielectric

− Doubles device density

Symmetric transistor

− Selectable source-drain

− Simple, planar structure

BL D/S

BL D/S

WL

WL

WL

WL

...

Contact

...

BL

WL

WL

WL

WL

WL

BL BL

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Spansion 45nm Technology

- 46.0%

Cell size = 0.020 mm2

Poly 1 HDP

ONO

Poly 2

CoSi

45nm

Cell size = 0.037 mm2

65nm

HDP Poly-1

Poly-2

ONO

CoSi

• Junction engineering to optimize doping profile

• Bit line trench to minimize neighboring bit program disturb

• Optimized program and erase algorithms

• Performance and reliability same as 65nm

45nm Technology

12

NOR Cell Size Scaling Example

5.0F2

4.3F2

4.1F2

5.9F2

5.3F2

4.7F2

5.3F²

0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

90nm 65nm 45nm 32nm

Co

re e

ffe

cti

ve

ce

ll s

ize

[p

er

2-b

it]

(µm

2)

Source: Spansion estimates

50% reduction

MirrorBit® cell

Floating gate NOR cell [MLC]

# of F2 is “per bit”

Spansion

Product

Introduction In Production 2012 2015

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Outline

NOR Flash

− Standalone

− Embedded in SOC

NAND Flash




Summary



− Resistive RAM


− MRAM

14

Embedded Flash in Microcontrollers (MCU)

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MCU TAM

Source: Semico

0

2,000

4,000

6,000

8,000

10,000

12,000

14,000

16,000

18,000

20,000

2006 2007 2008 2009 2010 2011 2012

$M

Total MCU

Flash MCU

16

MCU Volume by Embedded Flash Density

0

1,000

2,000

3,000

4,000

5,000

6,000

2006 2007 2008 2009 2010 2011 2012

Units (M)1MB+

1MB

512KB

256KB

128KB

64KB

32KB

16KB

8KB

4KB

Source: Semico

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Embedded NOR Flash

Flash Density High

Ac

ce

ss

Sp

ee

d

Fa

st

1T FG Cell

(~20F2)

Spansion

MirrorBit ® Cell

(5F2 per Bit)

Dual Gate Cell

(21 to 37F2)

18

Outline

NAND Flash




NOR Flash

− Standalone

− Embedded in SOC

Summary




− Resistive RAM

− MRAM

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Rapid NAND Growth Cycle

NAND Industry Experienced 18,000% Volume Growth in 10 Years

Data Source: WSTS Inc

NAND Units / Year (Mu)

Demand for NAND

More NAND Supply

Product Innovation

Lower Price

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NAND Flash Market Outlook

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Higher Density at the Cost of Performance and Reliability

Performance

Reliability

SLC NAND

MLC NAND

Die Capacity

From SLC NAND to MLC and TLC NAND

Process technology shrink every 18 months

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NAND Technology Migration

Density has doubled every year since 2004

Source: Samsung

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Managing Around Lower Quality NAND

Write Amplification = NAND Write / Host Write

Lower Write Amplification

Less Writes to the NAND

Extended NAND life

Efficient controllers are implementing firmware with lower Write Amplification to extend life of NAND

NAND

Controller

NAND

Memory

Host Write NAND Write

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NAND Controller

Improving Performance and Quality

Data Compression reduces amount of data written to the NAND

− Less data Writes increases performance

− Less data Writes increases NAND life

NAND

Memory

Host Write NAND Write Data In Data Out

Size of Data Out << Size of Data In

Wear Leveling is another mechanism to improve application quality

− NAND Data is moved from one physical location to another periodically to balance the wear-out of NAND cells

Compression

Engine

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Outline

NAND Flash




NOR Flash

− Standalone

− Embedded in SOC

Summary




− Resistive RAM

− MRAM

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NAND Cell and Architecture

Array Interconnections

Common Source Line

Cell Size ~ 4.0F2

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Scaling Challenges in NAND: Interference

Seokkiu Lee, Memory Workshop (IMW), pp.6-9, 2012

Capacitive coupling between

neighboring Word and Bit lines

Simulation results show WL-to-

WL and BL-to-BL interferences

double going from low-20nm to

low-10nm node

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Scaling Challenges in NAND: Fewer Electrons and Larger Variation

Location of parasitic charge in a

NAND cell and the required number

of electron at these locations to

shift the cell Vt by 100mV

Kirk Prall and Krishna Parat, IEDM 2010, pp. 102-105

Number of electrons required for

100mV Vt shift vs. cell feature size.

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Floating-Gate NAND Scaling Limitation

Physical Limit

NAND Flash Size

Half

Pit

ch

[n

m]

2Y nm Polygate

34 nm

The conventional ONO interlayer poly dielectric does not fit the pitch

Below 20nm

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Alternative NAND Architecture: Planar Charge Trap NAND

• Charge Trap cell in standard NAND array architecture

• Planar architecture

• Reduced interference coupling of neighboring cell

Charge Trap

Layer

Gate

Top Oxide

Tunnel Ox

P - substrate N+ N+

P - substrate

Doped Poly

Salicide

Charge Trap Storage Device Cell Size 4.0F2

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Alternative NAND Architecture: 3D

Jungdal Choi and Kwang Soo Seol, VLSI Tech. Digest, 178-179, 2011

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Outline

NAND Flash




NOR Flash

− Standalone

− Embedded in SOC

Summary




− Resistive RAM

− MRAM

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Lithography Roadmap

Rayleigh’s

Formula:

• Smaller wavelength and larger NA achieve finer pitch

− Maximum NA of 1.35 for 193 nm Immersion

• Challenge is to maintain high k1 for manufacturability while reducing min. feature Min. feature

1990 2000

Dim

en

sio

n:

(mm

)

0.01

0.1

1.0 i-line

l=365nm

DUV (KrF)

l=248nm DUV (ArF)

l=193nm

0.50

0.35

0.25 0.18

Minimum feature

near wavelength

Minimum feature

below wavelength

2010

EUV

l=13.5nm

?? 0.13

0.09

0.065

0.045

0.032

0.022

gap

0.018

0.010 2020

Serge Tedesco, CEA LETI. 2012 NIKON Litho Vision Presentation

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Technique to Extend Litho Tool Capability (A)

RET (Resolution Enhancement Technology) by OPC (Optical Proximity Correction)

Mask

Wafer Pattern

Line-end

pull-back

improved

Enhanced

pattern

fidelity

Good CD

control

Line-end

pull-back

Less

necking

Loss of

pattern

fidelity

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Technique to Extend Litho Tool Capability (B)

DFM (Design for Manufacturability): Changing cell layout to improve lithography performance

Irregular active and gate patterns

Vertical pattern for active

Horizontal pattern for gate

Yan Borodovsky, Intel. 2006 SPIE Microlithography, San Jose, CA

Difficult to print – requires intensive OPC Easy to print

36

Example 2

(Self-Aligned

Double

Patterning)

Example 1

(Litho-Litho-

Etch)

Technique to Extend Litho Tool Capability (C)

Double (or Quadruple) Patterning to extend process window by relaxing pitch to achieve fine patterns

HM

2X P

P

R

1

P

R

1

P

R

1

P

R

2

P

R

2

HM

2X P P

1) Print the1st pattern with 2X pitch

P

Quadruple patterning can further achieve 2x more pattern density

2) Coat and print the 2nd pattern between the formed 1st pattern

3) Transfer the lithography pattern to the hardmask and substrate

1) Print and form the 1st pattern with 2X pitch

2) Film deposition and etch to form the spacer as hardmask

3) Transfer the spacer to the substrate layer

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Technique to Extend Litho Tool Capability (D)

SMO (Source-Mask Optimization) to extend process window by optimizing illuminator and OPC based on layout pattern

+

Conventional

Quad illuminator

Basic OPC

design

Custom

illuminator

+

Strong OPC

design

Naoya Hayashi, DNP, 2012 NIKON Litho Vision Presentation

Source Mask Process Window Evaluated by Depth of Focus

Smaller window

Larger window

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Next Generation Lithography Tool: EUV

Technical Challenges

• EUV source intensity – Low wafer throughput

• Mask inspection – Embedded defect in the blank

• Mirror reflectivity / contamination – Cleaning frequency / downtime

• Resist maturity – Still in development

Katsuhiko Murakami, NIKON, From 2012 NIKON Litho Vision Presentation

More advanced EUV system

under development to achieve

< 10nm half-pitch

ST

I

ST

I

16nm half-pitch EUV resist lines

J.K. Stowers et. al.,

Proc. of SPIE Vol.

7969, 2011

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Lithography Trend

ArF (193nm) lithography already extended to 1X nm node

− More innovative approaches under development to further extend ArF capability

EUV lithography significantly improved

− Need to resolve manufacturing challenges

− Target technology: 16nm node or smaller

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Outline



− Resistive RAM

− MRAM

NOR Flash

− Standalone

− Embedded in SOC

Summary


NAND Flash




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Resistive Change Memory Building Blocks

Three Critical Components

Phase-Change Memory

or

Resistive RAM

Resistive

Change

Element

~4F2 RCM components:

1. MLC RCM memory device

2. Compact select device

3. Fine-line interconnect

Top View

Fine-Line Interconnect Both Directions

Select

Device

RCM

2F (SLC)

2.8F (MLC)

2F (SLC)

2.8F (MLC)

Schematic

42

Phase-Change RAM

Chalcogenide GeSbTe (GST) alloy

High current:

Scaling

Set pulse time:

Performance

Amorphous

Crystalline Temperature during Write

Source: Micron

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[1] S. Sadeghipour, ITHERM, 2006

[2] J. Tominga, et al., EPCOS, 2010

[3] S. Raox, et al, Phase Change Materials Science and Application, Spring 2009.

Phase Change Memory Scaling Challenges

Loss of margin between set and

reset current with scaling [3]

Heat Loss

from a PCM cell [1,2]

44

Conductive Bridge RAM (CBRAM)

Schematic illustration of the CBRAM conduction

mechanism

ON- state resistance dependence on

programming current

DC switching

Micheal Kund, et al., IEDM, 2005 & NVMTS, 07

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Oxygen Vacancy Based RRAM

DC bi-polar switching characteristics. Oxygen vacancies convert the dielectric into a

metal-rich filament (ON state) and reset (off state) by oxidation of the narrower tip of the

conductive filament.

D. C, Gilmer, IMW, IEDM, 2012

46

B. Govoreanu, et el, IEDM, 2011

Memory Stack: TiN/10nm HfO2/10nm Hf/TiN

Distribution for ON/OFF states with adaptive switching

Oxygen Vacancy-based Resistive RAM

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Significant variability in the placement of HRS and LRS with cycling

Issues with O-RRAM

Set/Rset distributions from a 1IT1R 1M O-RRAM (no window)

Kirk Prall, et al., Memory Workshop (IMW), pg. 1-5, 2012

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In Production: Toggle MRAM

Magnetic thin film as a storage element

SRAM random access speed-35nm Read & Write Cycle time

Magnetic Polarization rather than charge storage

Densities of 256kb-16Mb in production (180nm-130nm)

Challenging to scale to small geometries & reduce write current

Source: Everspin

7/23/2012

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Use spin momentum from current to change direction of S, m.

DS

Fixed

Layer

Tunnel

Barrier

Free

layer m

Torquet

S

D

D

In Development: Spin Torque MRAM

2000

2500

3000

3500

4000

4500

5000

5500

-0.4 0.1

Res

ista

nc

e (Ω

)

Current (mA)

MR

Rmin

Rmax

Source: Everspin

Challenges: Achieving low program current, high tunnel oxide breakdown,

and data retention simultaneously

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Summary

Nonvolatile memory market continues to grow with evolution of smarter and lighter portable products

Flash memory is now leading the semiconductor industry in requiring the most advanced lithography technologies

Active research in alternative Nonvolatile memories to address performance or scalability challenges of traditional Nonvolatile memory technologies

NOR and NAND Flash provide different value to the systems and will continue to coexist

recent development and progress in nonvolatile memory for ...€¦ · mirrorbit® cell (5f2 per...

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