quartus ii schematic design tutorial xiangrong ma [email protected]
TRANSCRIPT
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Design Flow
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Project information Directory Project name Top level name
Device Select Cyclone
(small & fast for compile)
Create Project
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Create a new Schematic File Add Gates Add Pins Check Design
Design Capture
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Fix Errors Check Reports
Compile(Synthesis & Fit & STA)
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Create a waveform vector File Add input/output pins(using Node Finder) Change value for input pins
Keep outputs as “X”
Create test stimulus file
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Right Click on Project, choose “Settings” Select “Simulator Setting” Select input file Select Simulation mode
Functional timing
Setup Simulation Environment
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Functional Simulation Generate Functional netlist file for simulation 0 delay, just “functional”
Timing Simulation After Compilation, timing information was
extracted from devices Wire delay/logic delay information would be
used for “back-annotated simulation” Much more accurate
Generate Netlist
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Run Simulation
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Fix errors
Analysis
S=A and BC=A or B
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.qpf Quatus Project File .qsf Quatus Setting File .vwf Vector Waveform File .bdf Block Design File .rpt Report
File extension description
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Quartus II 7.2 Web Edition(sp3)
URLs
https://www.altera.com/download/quartus-ii-we/dnl-quartus_we-v72.jsp