Quartus II Schematic Design Tutorial
Xiangrong [email protected]
Design Flow
Project information Directory Project name Top level name
Device Select Cyclone
(small & fast for compile)
Create Project
Create a new Schematic File Add Gates Add Pins Check Design
Design Capture
Fix Errors Check Reports
Compile(Synthesis & Fit & STA)
Create a waveform vector File Add input/output pins(using Node Finder) Change value for input pins
Keep outputs as “X”
Create test stimulus file
Right Click on Project, choose “Settings” Select “Simulator Setting” Select input file Select Simulation mode
Functional timing
Setup Simulation Environment
Functional Simulation Generate Functional netlist file for simulation 0 delay, just “functional”
Timing Simulation After Compilation, timing information was
extracted from devices Wire delay/logic delay information would be
used for “back-annotated simulation” Much more accurate
Generate Netlist
Run Simulation
Fix errors
Analysis
S=A and BC=A or B
.qpf Quatus Project File .qsf Quatus Setting File .vwf Vector Waveform File .bdf Block Design File .rpt Report
File extension description
Quartus II 7.2 Web Edition(sp3)
URLs
https://www.altera.com/download/quartus-ii-we/dnl-quartus_we-v72.jsp