Publications of Luca Selmi

Papers on International Journals:

[RI1] E. Sangiorgi, B. Ricco and L. Selmi, Three dimensional distribution of CMOS Latch-upcurrent , IEEE Electron Device Letters, vol.EDL-8 n.4, April 1987, pp.154.

[RI2] L. Selmi, E. Sangiorgi, G. Crisenza, D. Re and B. Ricco, Hysteresis cycle in the Latch-upcharacteristic of wide CMOS structures , IEEE Electron Device Letters, vol.EDL-5 n.5,May 1988, pp.214.

[RI3] R. Menozzi, L. Selmi, E. Sangiorgi, G. Crisenza, T. Cavioni and B. Ricco, Layout de-pendence of CMOS Latch-up , IEEE Transactions on Electron Devices, vol.ED-35 n.11,November 1988, pp.1892.

[RI4] C. Fiegna, L. Selmi, E. Sangiorgi and B. Ricco, Three dimensional effects in dynamicallytriggered CMOS latch-up , IEEE Transactions on Electron Devices, vol. ED-36, n.9,September 1989, pp.1683.

[RI5] E. Sangiorgi, C. Fiegna, R. Menozzi, L. Selmi and B. Ricco, Latch-up in CMOS circuits:a review , European Transactions on Telecommunications, vol.1 n.3, May-June 1990,pp.107. p

[RI6] R. Menozzi, L. Selmi, E. Sangiorgi and B. Ricco, Effects of the interaction of neighboringstructures on the Latch-up behavior of C-MOS ICs , IEEE Transactions on ElectronDevices, vol.ED-38 n.8, August 1991, pp.1978.

[RI7] L. Selmi, D. B. Estreich and B. Ricco, Small Signal MMIC Amplifiers with Bridged T-coil Matching Networks, IEEE Journal of Solid State Circuits, vol. 27, n.7, July 1992,pp.1093.

[RI8] L. Selmi, R. Menozzi, P. Gandolfi and B. Ricco, Numerical Analysis of the Gate VoltageDependence of the Series Resistances and Effective Channel Length in sub-micron GaAsMESFETs, IEEE Transactions on Electron Devices, vol.ED-39, Sept. 1992, pp.2015.

[RI9] L. Selmi and B. Ricco, Modelling thermal effects in the DC I-V characteristics of GaAsMESFETs, IEEE Transactions on Electron Devices, vol.ED-40, Feb. 1993, pp.273.

[RI10] R. Menozzi, P. Cova and L. Selmi, Experimental Application of a Novel Technique toExtract Gate Bias Dependent Source and Drain Parasitic Resistances of GaAs MESFETs,Solid State Electronics, vol.36, n.7, July 1993, pp.1083.

[RI11] L. Selmi and B. Ricco, Design of an X-band, Transformer Coupled Amplifier with im-proved Stability and Layout, IEEE Journal of Solid State Circuits, vol.28, n.6, June 1993,pp.701.

[RI12] M.Begin, F.M.Ghannouchi, F.Beauregard, L. Selmi and B.Ricco, Characterization of theTransient Behavior of a GaAs MESFET Using Dynamic I-V and S-parameter Measure-ments, IEEE Transactions on Instrumentation and Measurements, vol.45, n.1, Feb. 1996,pp.231.

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[RI13] L. Selmi, E. Sangiorgi and B. Ricco, Parameter extraction from I-V characteristics ofsingle MOSFETs , IEEE Transactions on Electron Devices, vol.ED-36 n.6, June 1989,pp. 1094.

[RI14] M. Lanzoni, M. Manfredi, L. Selmi, E. Sangiorgi, R.Capelletti and B. Ricco, Hot-Electroninduced Photon Energies in n-channel MOSFET’s operating at 77 and 300 K , IEEEElectron Device Letters, vol. EDL-10 n.5, May 1989, pp.173.

[RI15] C. Fiegna, E. Sangiorgi and L. Selmi, Oxide Field Dependence of Electron InjectionFrom Silicon into Silicon Dioxide., IEEE Transactions on Electron Devices, vol.ED-40,n.11, Nov. 1993, p.2018. e successivo Reply, IEEE Transactions on Electron Devices,vol.ED-41, n.9, Sept. 1994, p.1681.

[RI16] L. Selmi, C. Fiegna and R. Bez, Correlation between Substrate Hot Electron Energyand Homogeneous Degradation in n-MOSFETs, IEEE Transactions on Electron Devices,vol.ED-41, n.9, Sept. 1994, p.1677.

[RI17] L. Selmi and B. Ricco, Frequency Resolved Measurements for the Characterization ofMOSFET Parameters at Low Longitudinal Fields, IEEE Transactions on Electron De-vices, vol.ED-42, n.2, Feb. 1995, pp.315.

[RI18] L. Selmi, Silicon Luminescence Techniques for the Characterization of Hot-Carrier andDegradation Phenomena in MOS Devices, invited at INFOS 1995 and published onMicroelectronic Engineering, vol.28, n.1, June 1995, pp.250.

[RI19] L. Selmi, E. Sangiorgi and R. Bez, Non-Local Effects in p-MOSFET Substrate HotHole Injection Experiments, IEEE Electron Device Letters, vol.EDL-16, n.10, Oct. 1995,pp.442.

[RI20] D.Esseni, L. Selmi, E. Sangiorgi, R. Bez and B.Ricco, Temperature Dependence of Gateand Substrate Currents in the CHE Crossover Regime, IEEE Electron Device Letters,vol.EDL-16, n.11, Nov. 1995, pp.506.

[RI21] B. Fischer, L. Selmi, A. Ghetti and E. Sangiorgi, Electron Injection in the Gate Oxide ofMOS Structures at Liquid Nitrogen Temperature: Measurement and Simulation, Journalde Physique IV, Colloque 3, vol. 6, April 1996, pp.C3/19-C3/24.

[RI22] B. Fischer, A. Ghetti, L. Selmi, R. Bez and E. Sangiorgi, Bias and Temperature Depen-dence of Homogeneous Hot-Electron Injection from Silicon into Silicon Dioxide at LowVoltages, IEEE Transactions on Electron Devices, vol.44, no.2, Feb. 1997, pp.288.

[RI23] L. Selmi, A.Ghetti, R.Bez and E.Sangiorgi, Trade-offs between tunneling and Hot-CarrierInjection in short channel Floating Gate MOSFETs, Microelectronic Engineering, vol.36,n.1-4, June 1997, pp.293.

[RI24] L. Selmi, M. Mastrapasqua, D.M. Boulin, J.D. Bude, M. Pavesi, E. Sangiorgi and M.R.Pinto, Verification of Electron Distributions in Silicon by means of Hot-Carrier Lumines-cence Measurements, IEEE Transactions on Electron Devices, vol.45, no.4, Apr. 1998,pp.802.

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[RI25] L. Selmi, M. Pavesi, H.S. Wong, A. Acovic and E. Sangiorgi, Monitoring Hot CarrierDegradation in SOI MOSFETs by Hot Carrier Luminescence Techniques, IEEE Transac-tions on Electron Devices, vol.45, no.5, May 1998, pp.1135.

[RI26] D. Esseni and L. Selmi, A Better Understanding of Substrate Enhanced Gate Currentin MOSFETs and Flash Cells, Part I: Phenomenological aspects, IEEE Transactions onElectron Devices, vol.46, no.2, February 1999, pp. 369

[RI27] L. Selmi and D. Esseni, A Better Understanding of Substrate Enhanced Gate Current inMOSFETs and Flash Cells, Part II: Physical Mechanisms, IEEE Transactions on ElectronDevices, vol.46, no.2, February 1999, pp. 376

[RI28] A. Ghetti and L. Selmi and R. Bez, Low Voltage Hot Electrons and Soft-programmingLifetime Prediction in Non-Volatile Memory Cells, IEEE Transactions on Electron De-vices, vol.46, no.4, April 1999, pp.696.

[RI29] M.Pavesi, L.Selmi, M.Manfredi, E.Sangiorgi, M.Mastrapasqua and J.Bude, Evidence ofSubstrate Enhanced High Energy Tails in the Distribution Function of Deep SubmicronMOSFETs by Light Emission Measurements, IEEE Electron Device Letters, vol.20, no.11,1999, pp.595.

[RI30] P.Palestri, C.Fiegna, L. Selmi, F.Hurkx, J.Slotboom and E.Sangiorgi, A Better Insightin the Performance of Silicon BJT’s Featuring Highly Non-Uniform Collector DopingProfiles, IEEE Trans. Electron Devices, vol.47, n.5, May 2000, pp.1044.

[RI31] D.Esseni, L. Selmi, A.Ghetti and E.Sangiorgi, The Injection Efficiency of CHISEL GateCurrents in Short MOS Devices: Physical Mechanisms, Device Implications and Sensitiv-ity to Technological Parameters, IEEE Trans. Electron Devices, vol.47, n.11, Nov. 2000,pp.2194.

[RI32] A.Abramo, A.Cardin, L. Selmi, and E.Sangiorgi, Two-Dimensional Quantum MechanicalSimulation of Charge Distribution in Silicon MOSFETs, IEEE Trans. Electron Devices.,vol.47, Oct.2000, pp.1858.

[RI33] S.Zanchetta, A.Todon, A.Abramo, L.Selmi, and E.Sangiorgi, Analytical and NumericalStudy of the Impact of HALOs on Short Channel and Hot Carrier Effects in Scaled MOS-FETs, Solid State Electronics, vol.46, pp.429, 2001.

[RI34] F.Driussi, D.Esseni, L.Selmi and F.Piazza, Hot Hole Gate Current in Surface ChannelpMOSFETs, IEEE Electron Device Letters, vol.22, n.1, 2001, pp.29.

[RI35] A.Dalla Serra, A. Abramo, P.Palestri, L.Selmi and F.Widdershoven, Closed and OpenBoundary Models for Gate Current Calculations in MOS Devices, IEEE Trans. on Elec-tron Devices, vol.48, no.8, 2001, pp.1811.

[RI36] D.Esseni, J.Bude and L.Selmi, On Interface and Oxide Degradation in VLSI MOSFETs,Part I: Deuterium Effect in CHE Stress Regime, IEEE Trans. on Electron Devices, vol.49,no.2, pp.247, 2002.

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[RI37] D.Esseni, J.Bude and L.Selmi, On Interface and Oxide Degradation in VLSI MOSFETs,Part II: Fowler-Nordheim Stress Regime, IEEE Trans. on Electron Devices, vol.49, no.2,pp.254, 2002.

[RI38] D.Esseni, M.Mastrapasqua, G.Celler, C.Fiegna, L.Selmi and E.Sangiorgi, Low Field Elec-tron and Hole Mobility of SOI Transistors Fabricated on Ultra Thin Silicon Films for DeepSubmicron Technology Application, IEEE Trans. on Electron Devices, vol.48, pp.2842-2850, 2001.

[RI39] P.Palestri and L.Selmi, Non-Local Microscopic View of Signal Propagation Times in BJTsBiased up to High Currents, Solid State Electronics, vol.45, no.10, pp.1753, 2001.

[RI40] A.Dalla Serra, P.Palestri and L.Selmi, Can Photon Emission/ Absorption Processes Ex-plain the Substrate Current of Tunneling MOS Capacitors ?, Solid State Electronics,vol.46, no.7, pp.1069-1073, 2001.

[RI41] D.Esseni and L.Selmi, BipFLASH: a Novel Non-Volatile Memory Cell Concept for HighSpeed - Low Power Applications, Microelectronic Engineering, vol.59, pp.231, 2001.

[RI42] D.Esseni, J.Bude and L.Selmi, Experimental Study of Low Voltage Anode Hole Injectionin Thin Oxides, Microelectronic Engineering, vol.59, pp.55, 2001.

[RI43] M.Mastrapasqua, D.Esseni, G.K.Celler, C.Fiegna, L.Selmi and E.Sangiorgi, Measure-ments of Low Field Mobility in Ultra Thin SOI n- and p- MOSFETs, MicroelectronicEngineering, vol.59, pp.409, 2001.

[RI44] F.Driussi, D.Esseni, L.Selmi and F.Piazza, Damage Generation and Location in n- and p-channel MOSFETs Biased in the Substrate Enhanced Gate Current Regime, IEEE Trans.on Electron Devices, vol.49, no.5, pp.787, 2002.

[RI45] D.Esseni, L.Selmi, R.Bez and A.Modelli, A New High Injection Efficiency Non VolatileMemory Cell: BipFlash, Solid State Electronics, vol.47, 2002, pp.1739.

[RI46] P.Palestri, M.Pavesi, P.Rigolli, L.Selmi, A.Dalla Serra, A.Abramo, F.Widdershoven andE.Sangiorgi, Advanced Physically Based Device Modeling for Gate Current and Hot Car-rier Phenomena in Scaled MOSFETs, capitolo del volume “Future Trends in Microelec-tronics”, Wiley, 2002, pp.99-112.

[RI47] M.Pavesi, P.L.Rigolli, M.Manfredi, P.Palestri, L.Selmi, Spontaneous hot carrier photonemission rates in silicon: improved modeling and application to metal oxide semiconductordevices, Physical Review B, vol.65, 195209-1, 2002.

[RI48] P.Palestri, M.Pavesi, P.Rigolli, L.Selmi, A.Dalla Serra, A.Abramo, F.Widdershoven andE.Sangiorgi, A Comparative Analysis of Substrate Current Generation Mechanisms inTunneling MOS Capacitors, IEEE Trans. on Electron Devices, vol.49, n.8, 2002, pp.1427-1435 e n.10 pp.1844.

[RI49] D.Esseni, C.Fiegna, M.Mastrapasqua, G.Celler, L.Selmi, E.Sangiorgi, An ExperimentalStudy of Mobility Enhancement in Ultra-Thin SOI Transistors Operated in Double-GateMode, IEEE Trans. on Electron Devices, vol.50, n.2, 2003, pp.802.

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[RI50] P.Palestri, D.Esseni, L.Selmi, G.Guegan, E.Sangiorgi, A Methodology to Extract the Chan-nel Current of Permeable Gate MOSFETs, IEEE Trans. on Electron Devices, vol.50, n.5,2003, pp.1314.

[RI51] D.Esseni, A.Abramo, L.Selmi and E. Sangiorgi, Physically Based modeling of low fieldelectron mobility in Ultra-Thin SIngle- and Double-Gate SOI n-MOSFETs, IEEE Trans-action on Electron Devices, vol.50, no.12, 2003, pp.2445-2455.

[RI52] F.Driussi, D.Esseni, L.Selmi, On the Electrical Monitor for Device Degradation in theCHISEL Stress Regime, IEEE Electron Device Letters, vol.24, no.5, pp.357, 2003.

[RI53] E.Sangiorgi, P.Palestri, D.Esseni, C.Fiegna, A.Abramo, L.Selmi, Device Simulation forDecananometer MOSFETs, Material Science in Semiconductor Processing, vol.6, 2003,pp.93.

[RI54] L.Pantisano, L.Lucci, E.Cartier, A.Kerber, G.Groeseneken, M.Green, and L.Selmi, Im-pact of band structure on charge trapping in Thin SiO2/Al2O3 Poly-Si Gate Stacks, IEEEElectron Device Letters, vol.25, no.5, pp.320, May 2004.

[RI55] F.Driussi, D.Esseni, L.Selmi, Investigation of the Energy Distribution of Stress InducedOxide Traps by Numerical Analysis of the Trap-Assisted Tunneling of Hot Electrons, IEEETrans. Electron Devices, vol.51, no.10, pp.1170, 2004.

[RI56] F.Driussi, D.Esseni, L.Selmi, Performance and Reliability of the CHISEL Injection Regimeas the Programming Mechanism for FLASH Memory Cells, IEEE Trans. on Material andDevice Reliability, vol.4, no.3, pp.327, 2004.

[RI57] R.Nonis, N.DaDalt, P.Palestri and L.Selmi, Modeling, design and characterization of anew Low Jitter analog Dual Tuning LC-VCO PLL Architecture, IEEE Jou. of Solid StateCircuits, vol.40, no.6, pp.1303-1309, 2005.

[RI58] F.Driussi, D.Esseni, L.Selmi, Experimental characterization of Statistically IndependentDefects in Gate Dielectrics, Part I: Description and Validation of the Model, IEEE Trans.Electron Devices, vol.52, no.5, pp.942–948, 2005.

[RI59] F.Driussi, D.Esseni, L.Selmi, Experimental characterization of Statistically IndependentDefects in Gate Dielectrics, Part II: Experimental Results on FLASH Memory Arrays,IEEE Trans. Electron Devices, vol.52, no.5, pp.949–954, 2005.

[RI60] A.Arreghini, F.Driussi, D.Esseni, L.Selmi, M.J.van Duuren, R.van Schaijk, New ChargePumping model for the analysis of the spatial trap distribution in the nitride layer ofSONOS devices, Microelectronic Engineering, vol.80, June 2005, pp.333-336.

[RI61] P.Palestri, D.Esseni, S.Eminente, C.Fiegna, E.Sangiorgi, L.Selmi, Understanding Quasi-Ballistic Transport in nano-MOSFETs. Part I: Scattering in the Channel and in theDrain, IEEE Trans. on Electron Devices, vol.52, n.12, December 2005, pp.2727.

[RI62] S.Eminente, D.Esseni, P.Palestri, C.Fiegna, L.Selmi, E.Sangiorgi Understanding Quasi-Ballistic Transport in nano-MOSFETs. Part II: Technology Scaling along the ITRSRoadmap, IEEE Trans. on Electron Devices, vol.52, n.12, December 2005, pp.2736.

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[RI63] L.Lucci, P.Palestri, D.Esseni, L.Selmi, Modelling the Uniform Transport in Thin Film SOIMOSFETs with a Monte Carlo Simulator for the 2D Electron Gas, Solid State Electronics,vol.49, n.9, September 2005, pp.1529-1535.

[RI64] P.Palestri, S.Eminente, D.Esseni, C.Fiegna, E.Sangiorgi and L.Selmi, An Improved Semi-classical Monte-Carlo Approach for nano-scale MOSFET Simulation, Solid-State Elec-tronics, vol.49, 2005, pp.727-732.

[RI65] W.Stefanutti, P.Palestri, N.Akil, L.Selmi, Monte-Carlo Simulation of Substrate EnhancedElectron Injection in Split-gate Memory Cells, IEEE Trans. on Electron Devices, vol.53,n.1, January 2006, pp.89.

[RI66] P.Palestri, N.Akil, W.Stefanutti, M.Slotboom and L.Selmi, Effect of the Gap Size on theSource-Side-Injection Efficiency of Split-gate Memory Cells, IEEE Trans. on ElectronDevices, vol.53, n.3, March 2006, pp.488–492.

[RI67] R.Clerc, P.Palestri and L.Selmi, On the Physical Understanding of the kT Layer Conceptin Quasi Ballistic Regime of Transport in Nanoscale Devices, IEEE Trans. on ElectronDevices, vol.53, n.7, 2006, pp.1634.

[RI68] P.Palestri, N.Barin, D.Brunel, C.Busseret, A.Campera, P.A.Childs, F.Driussi, C.Fiegna,G.Fiori, R.Gusmeroli, G.Iannaccone, M.Karner, H.Kosina, A.L.Lacaita, E.Langer, B.Majkusiak,C.Monzio Compagnoni, A.Poncet, E.Sangiorgi, L.Selmi, A.S.Spinelli, J.Walczak, Com-parison of modeling approaches for the capacitance-voltage and current-voltage charac-teristics of advanced gate stacks, IEEE Trans. on Electron Devices, vol.54, n.1, 2007,pp.106-113.

[RI69] R.Nonis, E.Palumbo, P.Palestri, L.Selmi, A design methodology for MOS Current ModeLogic frequency dividers, IEEE Trans. on Circuits and Systems, vol.54, n.2, 2007, pp.245-254.

[RI70] L. Lucci, P. Palestri, D. Esseni, L. Bergagnini, L. Selmi, Multi-Subband Monte-Carlo studyof transport, quantization and electron gas degeneration in Ultra-thin SOI n-MOSFETs,IEEE Transactions on Electron Devices, vol.54, n.5, 2007, pp.1156.

[RI71] M. De Michielis, D. Esseni, P. Palestri, L. Selmi, A new analytical model for the energydispersion in two-dimensional hole inversion layers, Solid State Electronics, vol. 51, n. 4,Apr.2007, pp. 598-603.

[RI72] F. Driussi, L. Selmi, N. Akil, Michiel J. van Duuren, and Rob van Schaijk, Impact of De-vice Layout and Annealing Process During the Passivation of Interface States in Presenceof Silicon Nitride Layers, IEEE Transactions on Semiconductor Manufacturing, vol.21,n.2, 2008, pp.195-200.

[RI73] D.S.Golubovic, E., A.Arreghini, F. Driussi, Michiel J. van Duuren, N. Akil, L. Selmi, andD.Esseni, Programming and Retention Characteristics of SONOS Memory Arrays withLayered Tunnel Barrier, Semiconductor Science and Technology, vol.23, 2008, pp.1-6,(selected by the ”Institute of Physics” for inclusion in http:Select.iop.org).

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[RI74] M. Zilli, D. Esseni, P. Palestri, L. Selmi, On the apparent Mobility in Nanometric n-MOSFETs, IEEE Electron Device Letters, no.11, vol.28, novembre 2007, pag.1036-1039.

[RI75] M. De Michielis, D. Esseni, Y.L.Tsang, P. Palestri, L. Selmi, A.G.ONeill and S.Chattopadhyay,A semi analytical description of the hole band structure in inversion layers for the phys-ically based modelling of pMOS transistors, IEEE Trans. on Electron Devices, vol.54,2007, pag.2164–2173.

[RI76] I. Riolino, M. Braccioli, L. Lucci, P. Palestri, D. Esseni, C. Fiegna, L. Selmi, MonteCarlo simulation of decananometric nMOSFETs: multi-subband vs. 3D-electron gas withquantum corrections, Solid-State Electronics, issues 11-12, vol. 51, November-December2007, pag. 1558-1564.

[RI77] R. Nonis, E. Palumbo, P. Palestri, L. Selmi, A Design Methodology for MOS Current-Mode Logic Frequency Dividers, IEEE Transactions on Circuits and Systems-I: RegularPapers, n.2, vol.54, febbraio 2007, pag. 245-254.

[RI78] L. Bizjak, N. Da Dalt, P. Thurner, R. Nonis, P. Palestri, L. Selmi, Comprehensive Behav-ioral Modeling of Conventional and Dual-Tuning PLLS, IEEE Transactions on Circuitsand Systems- I: Regular Papers, n. 6, vol. 55, luglio 2008, pag. 1628-1638.

[RI79] M. Lenzi, P. Palestri, E. Gnani, S. Reggiani, A. Gnudi, D. Esseni, L. Selmi, G. Baccarani,Investigation of the Transport Properties of Silicon Nanowires using Deterministic andMonte Carlo Approaches to the Solution of the Boltzmann Transport Equation, IEEETransactions on Electron Devices, n. 8, vol. 55, agosto 2008, pag. 2086-2096.

[RI80] G.Comparone, P.Palestri, D.Esseni L.Lucci and L. Selmi, A better understanding of therequirements for predictive modeling of strain engineering in nMOS transistors, Jou. ofComputational and Theoretical Nanoscience, v.5, 2008, pp.1106-1114,

[RI81] F.Driussi, D.Esseni, L. Selmi, P.E.Hellstrom, G.Malm, J.Hallstedt, M.Ostling, T.Grasby,D.R.Leadley and X. Mescot, On the electron mobility enhancement in biaxially strainedSi MOSFETs, Solid State Electronics, v.52, 2008, pp.498.

[RI82] E.Sangiorgi, P.Palestri, D.Esseni, C.Fiegna, L. Selmi, The Monte Carlo approach to trans-port modeling in deca-nanometer MOSFETs, Solid State Electronics, v.52, pp.1414-1423,2008.

[RI83] A.Arreghini, N.Akil, F.Driussi, D.Esseni, L. Selmi and M.J.Van Duuren, Long termcharge retention dynamics of SONOS cells, Solid State Electronics, v.52, 2008, pp.1460-1466.

[RI84] L. Selmi, D.Esseni, P.Palestri, Foreword, Special Issue on ULIS International Conferenceon Ultimate Integration of Silicon, Solid-State Electronics, 2009.

[RI85] N.Serra, P.Palestri, G.D.J.Smit, L. Selmi, Multi-Subband Monte Carlo simulations of Iondegradation due to fin thickness fluctuations in FinFETs, Solid State Electronics, vol.53,2009, pp.424-432.

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[RI86] D.Ponton, P.Palestri, D.Esseni, L. Selmi, M.Tietbout, B.Parvais, D.Siprak and G.Knoblinger,Design of Ultra-Wideband Low-Noise Amplifiers in 45-nm CMOS Technology: Compar-ison Between Planar Bulk and SOI FinFET Devices, IEEE Trans. on Circuits and Sys-tems. I, Regular Papers, vol.56, pp.920-932, 2009.

[RI87] E.Vianello, M.Bocquet, F.Driussi, L.Perniola, G.Molas and L. Selmi, Program efficiencyand high temperature retention of SiN/high-K based memories, Microelectronic Engineer-ing, vol.86, 2009, pp.1830-1833.

[RI88] E.Vianello, F.Driussi, A.Arreghini, P.Palestri, D.Esseni, L. Selmi, N.Akil, M.Van Du-uren, Experimental and Simulation Analysis of Program/Retention Transients in SiliconNitride-Based NVM Cells, IEEE Trans. on Electron Devices, vol.56, 2009, pp.1980–1990.

[RI89] PALESTRI P, ALEXANDER C, ASENOV A, AUBRY-FORTUNA V, BACCARANI G,BOURNEL A, BRACCIOLI M, CHENG B, DOLLFUS P, ESPOSITO A, ESSENI D,FENOUILLET-BERANGER C, FIEGNA C, FIORI G, GHETTI A, IANNACCONE G,MARTINEZ A, MAJKUSIAK B, MONFRAY S, PEIKERT V, REGGIANI S, RIDDETC, SAINT-MARTIN J, SANGIORGI E, SCHENK A, L. Selmi, SILVESTRI L, TONI-UTTI P, WALCZAK J, A comparison of advanced transport models for the computationof the drain current in nanoscale nMOSFETs, Solid State Electronics, vol.53, pp.1293-1302, 2009.

[RI90] D.Esseni, F.Conzatti, M.De Michielis, N.Serra, P.Palestri, L. Selmi, Semi-classical trans-port modelling of CMOS transistors with arbitrary crystal orientations and strain engi-neering, Jou. of Computational Electronics, vol.8, 2009, pp.209–224.

[RI91] M.Agostinelli, M.Alioto, D.Esseni and L. Selmi, Leakage-Delay Tradeoff in finFET LogicCircuits: a Comparative Analysis with Bulk Technology, IEEE Trans on Very Large ScaleIntegration (VLSI) Systems, pp.232-245, 2010.

[RI92] P.Palestri , L.Lucci , S.Dei Tos , D.Esseni and L. Selmi, An improved empirical ap-proach to introduce quantization effects in the transport direction in multi-subband MonteCarlo simulations, Semiconductor Science and Technology, vol.25, n.5, doi: 10.1088/0268-1242/25/5/055011, 2010.

[RI93] M.Iellina, P.Palestri, N.Akil, M.Van Duureen, F.Driussi, D.Esseni and L. Selmi, A simula-tion study of the Punch-through Assisted Hot Holes Injection mechanism for non-volatile-memory cells, IEEE Trans. on Electron Devices, pp. 1055-1062, 2010.

[RI94] M.Nocente, D.Fontanelli, P.Palestri, R.Nonis, D.Esseni and L. Selmi, A numerical modelfor the oscillation frequency, the amplitude and the phase-noise of MOS-current-mode-logic ring oscillators, Int. Journal of Circuit Theory and Applications, pp. 607-629, 2010.

[RI95] M.Bresciani, P.Palestri , D.Esseni and L. Selmi, Simple and efficient modeling of the Ekrelationship and low-field mobility in Graphene Nano-Ribbons, Solid State Electronics,vol.54, pp. 1015-1021, 2010.

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[RI96] L. De Michielis, L. Selmi and A.Ionescu, A quasi-analytical model for nanowire FETswith arbitrary polygonal cross section, Solid State Electronics, vol.54, pp. 929-934, 2010.

[RI97] L. De Michielis, K.E. Moselund, L. Selmi and A.M. Ionescu, Corner effect and localvolume inversion in SiNW FETs, IEEE Transactions on Nanotechnology, vol.10, n.4pp.810–816, 2011.

[RI98] E.Vianello, F.Driussi, L.Perniola, G.Molas, J.-P.Colonna, B. De Salvo and L. Selmi, Ex-planation of the Charge Trapping Properties of Silicon Nitride Storage Layers for NVMDevices Part I: Experimental Evidences from the Physical and Electrical Characterization,IEEE Trans. on Electron Devices, vol.58, n.8, ISSN: 0018-9383, pp. 2483-2489, 2011.

[RI99] E.Vianello, F.Driussi, P.Blaise, P.Palestri, D.Esseni, L.Perniola, G.Molas, B. De Salvoand L. Selmi, Explanation of the Charge Trapping Properties of Silicon Nitride StorageLayers for NVM Devices Part II: Atomistic and Electrical Modeling, IEEE Trans. onElectron Devices, vol.58, n.8, ISSN: 0018-9383, pp. 2490-2499, 2011.

[RI100] F.Conzatti, N.Serra, D.Esseni, M.De Michielis, A.Paussa, P.Palestri, L. Selmi S.M.Thomas,T.E.Whall, D.Leadley, E.M.C.Parker, L.Witters, MJ.Hytch, E.Snoeck, T.J.Wang, W.C.Lee,G.DoornBos, G.Vellianitis, M.J.H.Van Dahl and R.J.P.Lander, Investigation of StrainEngineering in FinFETs Comprising Experimental Analysis and Numerical Simulations,IEEE Trans. on Electron Devices,vol. 58; ISSN: 0018-9383, pp. 1583-1593, 2011.

[RI101] A.Cristofoli, P.Palestri, M.P.Giordani, V.Cindro, G.F.Dalla Betta L. Selmi, ExperimentalDetermination of the Impact Ionization Coefficients in Irradiated Silicon, IEEE Trans. onNuclear Science,vol. 58; ISSN: 0018-9499, pp. 2091–2096, 2011.

[RI102] GRENIER P, ALIMONTI G, BARBERO M, BATES R, BOLLE E, BORRI M, BOSCARDINM, BUTTAR C, CAPUA M, CAVALLI-SFORZA M, COBAL M, CRISTOFOLI A,DALLA BETTA G.-F, DARBO G, DA VIA C, DEVETAK CE, DEWILDE B, DI GIRO-LAMO B, DOBOS D, EINSWEILER K, ESSENI D, FAZIO S, FLETA C, FREESTONEJ, GALLRAPP C, GARCIA-SCIVERES M, GARIANO G, GEMME C, GIORDANI M.-P, GJERSDAL H, GRINSTEIN S, HANSEN T, HANSEN T.-E, HANSSON P, HASIJ, HELLE K, HOEFERKAMP M, HAGGING F, JACKSON P, JAKOBS K, KALLIO-PUSKA J, KARAGOUNIS M, KENNEY C, KAHLER M, KOCIAN M, KOK A, KOLYAS, KOROKOLOV I, KOSTYUKHIN V, KRAGER H, LA ROSA A, LAI C.H, LIETAERN, LOZANO M, MASTROBERARDINO A, MICELLI A, NELLIST C, OJA A, OSHEAV, PADILLA C, PALESTRI P., PARKER S, PARZEFALL U, PATER J, PELLEGRINIG, PERNEGGER H, PIEMONTE C, POSPISIL S, POVOLI M, ROE S, ROHNE O,RONCHIN S, ROVANI A, RUSCINO E, SANDAKER H, SEIDEL S, SELMI L, SIL-VERSTEIN D, SOABAE K, SLAVICEK KT, STAPNES S, STUGU B, STUPAK J,SU D, SUSINNO G, R. THOMPSON, TSUNG J.-W, TSYBYCHEV D, WATTS S.J,WERMES N, YOUNG C, ZORZI N, Test beam results of 3D silicon pixel sensors forthe ATLAS upgrade, Nuclear Instruments and Methods in Physics Research. Section A,Accelerators, Spectrometers, Detectors and Associated Equipment, vol. 638; pp.33–40, ,2011.

[RI103] F.Conzatti, N.Serra, D.Esseni, M.De Michielis, A.Paussa, P.Palestri, L. Selmi S.M.Thomas,T.E.Whall, D.Leadley, E.M.C.Parker, L.Witters, MJ.Hytch, E.Snoeck, T.J.Wang, W.C.Lee,

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G.DoornBos, G.Vellianitis, M.J.H.Van Dahl and R.J.P.Lander, Investigation of StrainEngineering in FinFETs Comprising Experimental Analysis and Numerical Simulations,IEEE Trans. on Electron Devices,vol. 58; ISSN: 0018-9383, pp. 1583-1593, , 2011.

[RI104] E.Vianello, F.Driussi, D.Esseni, L. Selmi, F.Widdershoven, M.J.van Duuren, Explanationof SILC probability density distributions with nonuniform generation of traps in the tunneloxide of flash memory arrays, IEEE Trans. on Electron Devices,vol. 54; ISSN: 0018-9383,pp. 1953–1962, , 2007.

Papers at International Conferences:

[CI1] L. Selmi, F. Venturi, E. Sangiorgi and B. Ricco, Three dimensional distribution of Latch-up current in scaled CMOS structures , Proceedings ESSDERC 1987, Bologna, Italy,September 1987, pp.783.

[CI2] R. Menozzi, M. Lanzoni, L. Selmi, B. Ricco, An improved procedure to test CMOS ICsfor Latch-up , Proceedings International Test Conference, Washington D.C., September1990, pp.1028.

[CI3] P. Pavan, E. Zanoni, R. Menozzi and L. Selmi, Adjacent structure interactions in theLatch-up triggering of CMOS twin-tub and epitaxial technologies , Proceedings 5th Euro-pean Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Bor-deaux, October 1991, pp.333.

[CI4] R. Menozzi, L. Selmi, E. Sangiorgi and B. Ricco, Effects of the interaction of neighboringstructures on the Latch-up behavior of C-MOS ICs, Proceedings 4th European Sympo-sium on Reliability of Electron Devices, Failure Physics and Analysis, Technopolis, Bari,October 1990, pp.175.

[CI5] L. Selmi and Don B. Estreich, An accurate System for automated On-wafer Character-ization of Three-port Devices , Proceedings IEEE GaAs IC Symposium, New Orleans,October 1990, pp.343.

[CI6] L. Selmi, D. B. Estreich and B. Ricco, Application of Bridged T-coils to the design ofMultiplicative Gain MMIC Amplifiers Proceedings Seventeenth IEEE Solid State CircuitsConference, Milano, 11-13 September 1991, pp.173.

[CI7] L. Selmi and B. Ricco, Design of an X-band, Transformer Coupled Amplifier with im-proved Stability and Layout , URSI Int. Symposium on Signals, Systems and Electronics,Paris, September 1992, pp.768.

[CI8] L. Selmi and B. Ricco, Thermal Characterization of GaAs MESFETs by means of PulsedMeasurements , IEEE IEDM Technical Digest, Washington D.C., December 1991, p.255.

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[CI9] B. Ricco, L. Selmi and E. Sangiorgi, A novel method to determine the Source and Drainresistances of individual MOSFETs , IEDM Technical Digest, S.Francisco, December1988, p.122.

[CI10] L. Selmi, M. Lanzoni, S. Bigliardi and E. Sangiorgi, Photon Emission from sub-micronp-channel MOSFETs Biased at High Fields , Proc. European Solid State Device ResearchConference, Leuwen, Belgium, September 1992, p.747.

[CI11] R. Menozzi, L. Selmi, P. Gandolfi and B. Ricco, Extraction of the Series Resistancesand Effective Channel Length of GaAs MESFETs by means of Electrical Methods: ANumerical Analysis, IEEE IEDM Technical Digest, Washington D.C., December 1991,p.341.

[CI12] L. Selmi, C. Fiegna, E.Sangiorgi, R. Bez and B. Ricco, Analysis of Uniform Degradationin n-MOSFETs, IEEE IEDM Technical Digest, S. Francisco, December 1992, p.729.

[CI13] L. Selmi, H. S. Wong, M. Lanzoni, E. Sangiorgi and M. Manfredi, Investigation of HotElectron Luminescence in Silicon by means of Dual Gate MOS Structures , IEEE IEDMTechnical Digest, Washington DC, December 1993, p.531.

[CI14] L. Selmi, C. Fiegna, E. Sangiorgi, R. Bez and B. Ricco, A Study of Injection Conditionsin the Substrate Hot Electron Induced Degradation of n-MOSFETs, Proc. InternationalWorkshop on VLSI Process and Device Modelling (VPAD), Nara, Japan, May 1993,p.156.

[CI15] L. Selmi, E. Sangiorgi, R. Bez and B. Ricco, Measurement of the Hot Hole Injection Prob-ability from Si Into SiO2 in p-MOSFET’s , IEEE IEDM Technical Digest, WashingtonDC, December 1993, p.333.

[CI16] L. Selmi, A. Alfieri and B. Ricco, AC Frequency Resolved Measurements for Direct Ex-traction of the Parasitic Resistance of Individual MOSFETs , IEEE IEDM TechnicalDigest, S.Francisco, December 1994, p.471.

[CI17] M. Lanzoni, L. Selmi, R. Bez and M. Manfredi, A Test Pattern to Investigate the Effect ofCapping Layers on the Hot Carrier Induced Photon Spectra of MOSFET’s, IEEE ICMTSTechnical Digest, San Diego, March 1993, p.204.

[CI18] L. Selmi, E. Sangiorgi, R. Bez and B. Ricco, A Test Chip and an Accurate MeasurementSystem to Characterize Hot Hole Injection in the Gate Oxide of p-MOSFET’s, IEEEICMTS Technical Digest, San Diego, March 1993, p.68.

[CI19] M.Begin, F. M. Ghannouchi, L. Selmi and B. Ricco, Instantaneous S-parameters Mea-surements of MESFETs under Burst Bias Conditions, IEEE IMTC Technical Digest,Hamamatsu, Japan, May 1994, p.858.

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[CI20] L. Selmi, A. Pieracci, M. Lanzoni, M. Pavesi, R. Bez and E. Sangiorgi, ExperimentalAnalysis of Polarization in the Hot-Carrier Luminescence of Silicon Devices, ProceedingsESSDERC 1994, Edimburgh, September 1994, p.421.

[CI21] M.Begin, F. M. Ghannouchi, F. Beauregard, L. Selmi, B. Ricco and V. Borelli, Char-acterization of Transient Effects in the S-Parameters of GaAs MESFETs by means ofPulsed Measurements, Proceedings ESSDERC 1994, Edimburgh, September 1994, p.639.

[CI22] D.Esseni, L. Selmi, E. Sangiorgi, R. Bez and B. Ricco, Bias and Temperature Dependenceof Gate and Substrate Currents in n-MOSFETs at Low Drain Voltage , IEEE IEDMTechnical Digest, S.Francisco, December 1994, p.307.

[CI23] A.Ghetti, L. Selmi, E. Sangiorgi, A.Abramo and F.Venturi, A Combined Transport-Injection Model for Hot-Electron and Hot-Hole Injection in the Gate Oxide of MOS struc-tures, IEEE IEDM Technical Digest, S.Francisco, December 1994, p.363.

[CI24] D.Esseni, L. Selmi, R.Bez, L.Ravazzi and E. Sangiorgi, Soft Programming in ScaledFLASH Cells, Proceedings ESSDERC 1995, Delft, The Netherlands, Sept. 1995, p.549.

[CI25] L. Selmi, M.Mastrapasqua, D.M.Boulin, J.D.Bude, M.Manfredi, E. Sangiorgi and M.R.Pin-to, Characterization and Modeling of Hot-Carrier Luminescence in Silicon n+/n/n+

Devices, IEEE IEDM Technical Digest, Washington D.C., December 1995, pp.293.

[CI26] L. Selmi, M. Pavesi, H. S. Wong, A. Acovic and E. Sangiorgi, A Comparative Study ofHot-Carrier Induced Light Emission and Degradation in Bulk and SOI MOSFETs , IEEEIEDM Technical Digest, Washington D.C., December 1995, pp.49.

[CI27] L. Selmi, R. Bez and E. Sangiorgi, An Improved Test Structure to Characterize Ultra-Low Hot Carrier Injection in Homogeneous Conditions , IEEE ICMTS Technical Digest,Trento, March 1996, pp.83.

[CI28] L. Selmi, B. Fischer, A. Ghetti and R. Bez, Hot-carriers at low voltages: New experimen-tal evidences and open issues, invited paper, IEEE IEDM Technical Digest, S.Francisco,December 1996, pp.375.

[CI29] A. Ghetti, L. Selmi, R. Bez and E. Sangiorgi, Monte Carlo Simulation of Low Voltage HotCarrier Effects in Non Volatile Memory Cells , IEEE IEDM Technical Digest, S.Francisco,Dicembre 1996, pp.379.

[CI30] D.Esseni, L. Selmi and R.Bez, The Impact of Device Design on the Substrate EnhancedGate Current of VLSI MOSFET’s, Proc. ESSDERC, 1998, pp.288.

[CI31] P. Palestri, C. Fiegna, L. Selmi, G.A.M. Hurkx, J.W. Slotboom and E. Sangiorgi, Opti-mization Guidelines for Epitaxial Collectors of Advanced BJT’s with Improved BreakdownVoltage and Speed , IEEE IEDM Technical Digest, S.Francisco, Dicembre 1998, pp.741.

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[CI32] P. Palestri, L. Selmi, G.A.M. Hurkx, J.W. Slotboom and E. Sangiorgi, Energy DependentElectron and Hole Impact Ionization in Si Bipolar Transistors , IEEE IEDM TechnicalDigest, S.Francisco, Dicembre 1998, pp.885.

[CI33] D. Esseni and L. Selmi, Experimental Signature and Physical Mechanisms of SubstrateEnhanced Gate Current in MOS Devices, IEEE IEDM Technical Digest, S.Francisco,Dicembre 1998, pp.579.

[CI34] D. Esseni, L. Selmi, A.Ghetti and E.Sangiorgi, The Scaling Properties of CHISEL andCHE Injection Efficiency in MOSFETs AND FLASH Memory Cells , IEEE IEDM Tech-nical Digest, Washington, Dicembre 1999, pp.275.

[CI35] A. Todon, L. Selmi, A.Abramo and E.Sangiorgi, On the Optimization of HALOs for 0.1µm MOSFETs and Below , Proc. IEEE ISDRS Conf., Charlottesville, Dicembre 1999,pp.41.

[CI36] A. Todon, L. Selmi, A.Abramo and E.Sangiorgi, Short Channel and Hot Carrier Perfor-mance of ULSI MOSFETs with HALO Structures, Proc. First European Workshop onUltimate Integration of Silicon (ULIS’2000), Grenoble, January 2000, pp..

[CI37] A. Abramo, A. Cardin, L. Selmi and E.Sangiorgi, Two Dimensional Quantum Simulationof Silicon MOSFETs, Proc. IEEE ISDRS Conf., Charlottesville, Dicembre 1999, pp.77.

[CI38] A. Abramo, A. Cardin, L. Selmi and E.Sangiorgi, Two Dimensional Quantum MechanicalAspects in the Charge Distribution of ULSI Silicon MOSFETs, Proc. First EuropeanWorkshop on Ultimate Integration of Silicon (ULIS’2000), Grenoble, January 2000, pp..

[CI39] P.Palestri, L.Selmi, M.Pavesi, F.Widdershoven and E.Sangiorgi, Coupled Monte CarloSimulation of Si and SiO2 Transport in MOS Capacitors, Proc. SISPAD 2000, Seattle,Sept. 2000, pp.38.

[CI40] P.Palestri, L.Selmi, F.Hurkx and J.Slotboom, A Monte Carlo Technique to InvestigateSignal Delays of Advanced Si BJT’s up to High Currents, Proc. SISPAD 2000, Seattle,Sept. 2000, pp.46.

[CI41] A.Abramo, L.Selmi, Z.Yu, R.W.Dutton, Well-tempered MOSFETs: 1D versus 2D quan-tum analysis, Proc. SISPAD 2000, Seattle, Sept. 2000, pp.188.

[CI42] P.Palestri, L.Selmi, E.Sangiorgi, Monte Carlo Analysis of Signal Delays in BJT’s, Proc.“Advancesin Silicon Technology and Devices”, Padova, April 2000.

[CI43] A.Dalla Serra, A.Abramo, P.Palestri, L.Selmi, E.Sangiorgi, Tunneling Injection in Thin-Oxide MOS Capacitors, Proc.“Advances in Silicon Technology and Devices”, Padova,April 2000.

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[CI44] F.Driussi, D.Esseni, L.Selmi, F.Piazza, E.Sangiorgi, Substrate Enhanced Gate Currentsin CMOS Devices, Proc.“Advances in Silicon Technology and Devices”, Padova, April2000.

[CI45] F.Driussi, D.Esseni, L.Selmi, F.Piazza, Observation of a New Hole Gate Current Com-ponent in p+-poly Gate p-channel MOSFET’s, Proc. ESSDERC 2000, Cork, Sept. 2000,pp.136.

[CI46] A.Dalla Serra, A.Abramo, P.Palestri, L.Selmi, F.Widdershoven A comparison betweensemi-classical and quantum-mechanical escape-times for gate current calculations, Proc.ESSDERC 2000, Cork, Sept. 2000, pp.340.

[CI47] P.Palestri, L.Selmi, M.Pavesi, F.Widdershoven, E.Sangiorgi, Cathode Hot Electrons andAnode Hot Holes in Tunneling MOS Capacitors, Proc. ESSDERC 2000, Cork, Sept.2000, pp.296.

[CI48] P.Rigolli, M.Manfredi, M.Pavesi, P.Palestri and L.Selmi, Hot Carrier Effects in MOScapacitors: Improvements in Coupled Monte Carlo Simulations of Si and SiO2 Transport,INFM Meeting, Genova, June 2000.

[CI49] F.Driussi, D.Esseni, L.Selmi and F.Piazza, Substrate Enhanced Degradation of CMOSDevices, IEEE IEDM Technical Digest, S.Francisco, Dicembre 2000, pp.323.

[CI50] P.Palestri, P.Rigolli, M.Pavesi, L.Selmi, A.Dalla Serra, A.Abramo, F.Widdershoven andE.Sangiorgi, Impact Ionization and Photon Emission in MOS Capacitors and FETs, IEEEIEDM Technical Digest, S.Francisco, Dicembre 2000, pp.97.

[CI51] D.Esseni, J.Bude and L.Selmi, Deuterium Effect on Interface States and SILC Generationin the CHE Stress Conditions: A Comparative Study, IEEE IEDM Technical Digest,S.Francisco, Dicembre 2000, pp.339.

[CI52] D.Esseni, M.Mastrapasqua, G.K.Celler, F.H.Baumann, C.Fiegna, L.Selmi and E.Sangiorgi,Low Field Mobility of Ultra Thin SOI n- and p-MOSFETs: Measurements and Impli-cations on the Performance of Ultra Short MOSFETs, IEEE IEDM Technical Digest,S.Francisco, Dicembre 2000, pp.671.

[CI53] F.Driussi, D.Esseni, L.Selmi and F.Piazza, Hot Carrier Degradation and Damage Profil-ing of CMOS Devices with Biased Substrates, MEDEA/RESPONSE Workshop, AgrateBrianza, Nov.2000.

[CI54] A.Dalla Serra, P.Palestri, L.Selmi, Can Photon Emission/ Absorption Processes Explainthe Substrate Current of Tunneling MOS Capacitors ?, Proc. 2nd ULIS Workshop, Greno-ble, January 2001, pp.117.

[CI55] D.Esseni, L.Selmi, BipFLASH: a Novel Non-Volatile Memory Cell Concept for High Speed- Low Power Applications, Proc. INFOS, June 2001, pp.93.

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[CI56] D.Esseni, J.Bude, L.Selmi, Experimental Study of Low Voltage Anode Hole Injection inThin Oxides, Proc. INFOS, June 2001, pp.159.

[CI57] M.Mastrapasqua, D.Esseni, G.K.Celler, F.H.Baumann, C.Fiegna, L.Selmi, and E.SangiorgiMeasurements of Low field mobiliy in ultra-thin SOI n- and p-mosfets, Proceedings of thetenth International Symposium on Silicon-on-insulator technology and devices, The elec-trochemical society, pp.97-102, 2001.

[CI58] D.Esseni, M.Mastrapasqua, C.Fiegna, G.Celler, L.Selmi and E.Sangiorgi, Low Field Elec-tron Mobility in Double Gate, Ultra-Thin SOI MOSFETs, IEEE IEDM Technical Digest,Washington, Dicembre 2001, pp.445.

[CI59] S.Zanchetta, D.Esseni, P.Palestri and L.Selmi, Microscopic Analysis of the Impact ofSubstrate Bias on the Gate Current of pMOSFETs, ISDRS Conference, Washington, Dec.2001, pp.106.

[CI60] A. Dalla Serra, P.Palestri, F.Widdershoven and L.Selmi, On the Extraction of OxideThickness and Sub-Band Energy Shift in Thin Oxide MOS Capacitors with PermeableGates, ISDRS Conference, Washington, Dec. 2001, pp.597.

[CI61] D.Esseni, M.Mastrapasqua, C.Fiegna, G.Celler, L.Selmi and E.Sangiorgi, Ultra Thin SOITransistors for Ultimate CMOS Technology: Fundamental Properties and ApplicationPerspectives, Proc. WOFE, 2002, pp.29.

[CI62] G.Ingrosso, L.Selmi and E.Sangiorgi, Monte Carlo Simulation of Program and EraseCharge Distributions in NROMTM Devices, Proc. ESSDERC, 2002, pp.187.

[CI63] D.Esseni, A.Abramo, L.Selmi and E.Sangiorgi, Study of Low Field Electron Transportin Ultra Thin Single and Double Gate SOI MOSFETs, IEEE IEDM Technical Digest,Washington, Dicembre 2002, pp.719.

[CI64] F.Driussi, R.Iob, D.Esseni, L.Selmi R.van Schaijk and F.Widdershoven, SpectroscopicAnalysis of Trap Assisted Tunneling in Thin Oxides by Means of Substrate Hot Elec-tron Injection Experiments, IEEE IEDM Technical Digest, Washington, Dicembre 2002,pp.159.

[CI65] L.Lucci, L.Pantisano, E.Cartier, A.Kerber, G.Groeseneken, M.Y.Ho, M.Green and L.Selmi,Polarity dependent charge Trapping in Thin SiO2/Al2O3 Gate Stacks with Poly-Si GateElectrodes: Influence of High Temperature Annealing, SISC Conference Technical Digest,Dicembre 2002, pp.S8-03.

[CI66] R.Nonis, P.Palestri, N.DaDalt and L.Selmi, Phase Noise Modelling in Phase Locked LoopFrequency Synthesizer, AustroChip Technical Digest, ISBN 3-9501635-0-6, October 2002,pp.29-35.

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[CI67] P.Palestri, D.Esseni, L.Selmi, G.Guegan, E.Sangiorgi, On the Extraction of Channel Cur-rent in Permeable Gate MOSFETs, Proc. IEEE ULIS 2003 Workshop, pp.57, 2003.

[CI68] P.Palestri, D.Esseni, A.Abramo, R.Clerc and L.Selmi, Carrier Quantization in SOI MOS-FETs using an Effective Potential Based Monte Carlo Tool, Proc. IEEE ESSDERC,pp.407, 2003.

[CI69] L.Lucci, D.Esseni, J.Loo, Y.Ponomarev, L.Selmi, A.Abramo and E.Sangiorgi, Quanti-tative Assessment of Mobility Degradation by Remote Coulomb Scattering in Ultra-ThinOxide MOSFETs: Measurements and Simulations, Proc. IEEE IEDM, pp.463-466, 2003.

[CI70] L.Selmi, D.Esseni, P.Palestri, Towards Microscopic Understanding of MOSFET Reliabil-ity: The Role of Carrier Energy and Transport Simulations, invited paper, Proc. IEEEIEDM, pp.333-336, 2003.

[CI71] R.Nonis, N.Da Dalt, P.Palestri, and L.Selmi, Modeling, Design and Characterization ofa New Low Jitter Analog Dual Tuning LC-VCO PLL Architecture, Proc. ISCAS Conf.,May 2004, vol.IV, pp.553-556.

[CI72] P.Palestri, S.Eminente, D.Esseni, C.Fiegna, E.Sangiorgi and L.Selmi, An Improved Semi-classical Monte-Carlo Approach for nano-scale MOSFET Simulation, Proc. ULIS Conf.,March 2004. pp.101-104.

[CI73] L.Lucci, P.Palestri, D.Esseni and L.Selmi, Comparative Analysis of Basic Transport Prop-erties in the Inversion Layer of Bulk and SOI MOSFETs: a Monte-Carlo Study, Proc.IEEE ESSDERC, Sept. 2004. pp.321, ISBN 0-7803-8479-2.

[CI74] F.Driussi, D.Esseni, L.Selmi, F.Widdershoven and M.Van Duureen, Experimental Evi-dence and Statistical Modeling of Cooperating Defects in Stressed Oxides, Proc. IEEEESSDERC, Sept. 2004. pp.209, ISBN 0-7803-8479-2.

[CI75] S.Eminente, D.Esseni, P.Palestri, C.Fiegna, L.Selmi and E.Sangiorgi, Enhanced Ballis-ticity in nano-MOSFETs along the ITRS Roadmap: A Monte Carlo Study, Proc. IEEEIEDM, Dec. 2004. pp.609.

[CI76] P.Palestri, D.Esseni, S.Eminente, C.Fiegna, E.Sangiorgi and L.Selmi, A Monte-CarloStudy of the Role of Scattering in Deca-nanometer MOSFETs, Proc. IEEE IEDM, Dec.2004. pp.605.

[CI77] L.Lucci, P.Palestri, D.Esseni, and L.Selmi, Mobility, Velocity and Average Energy in UltraThin Body SOI MOSFETs, Proc. First EUROSOI Workshop, Granada, January 2005,pp.51.

[CI78] F.Driussi, S.Marcuzzi, P.Palestri, and L.Selmi, Gate Current in Stacked Dielectrics forAdvanced FLASH EEPROM cells, Proc. ESSDERC, Grenoble, September 2005, pp.317.

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[CI78] R.Nonis, E.Palumbo, P.Palestri, and L.Selmi, A Model to Understand Current Consump-tion, Maximum Operating Frequency And Scaling Trends Of MCML Frequency Dividers,AustroChip Technical Digest, ISBN 3-901578-13-7, October 2005, pp.57–60.

[CI79] L.Lucci, P.Palestri, D.Esseni, L.Selmi, Multi-subband Monte Carlo modelling of nano-MOSFETs with strong vertical quantization and electron gas degeneration, Proc. IEEEIEDM, Dec. 2005, pp.631-634.

[CI80] F.Driussi, L.Selmi, N.Akil. M.J.van Duuren, and R.van Schaijk On the Passivation ofInterface States in SONOS Test Structures: Impact of Device Layout and Annealing Pro-cess, Proc. IEEE ICMTS, Mar. 2006. pp.51-54.

[CI81] R.Clerc, P.Palestri and L.Selmi, Quasi Ballistic transport in Fully Depleted SOI MOS-FETs : the kT layer concept revisited, Proc. second IEEE EUROSOI workshop, Mar.2006. pp.103-104.

[CI82] M.De Michielis, D.Esseni, P.Palestri and L.Selmi, A New Analytical Model for the EnergyDispersion in 2D Hole Inversion Layers, Proc. IEEE ULIS workshop, Apr. 2006. pp.81-84.

[CI83] L.Lucci, P.Palestri, D.Esseni, and L.Selmi, Simulation of Double-Gate nano-MOSFETswith the Multi-subband Monte Carlo Method, Proc. IEEE ULIS workshop, Apr. 2006.pp.89-92.

[CI84] J.L.van der Steen, D.Esseni, P.Palestri and L.Selmi, Validity of the effective mass approx-imation in silicon and germanium inversion layers, Proc. Int. Workshop on Computa-tional Electronics, Apr. 2006. pp.301-302.

[CI85] D.Ponton, L.Lucci, P.Palestri, D.Esseni, and L.Selmi, Assessment of the Impact of BiaxialStrain on the Drain Current of Decanometric n-MOSFET, Proc. ESSDERC 2006, pp.166-169.

[CI86] I.Riolino, M.Braccioli, L.Lucci, D.Esseni, C.Fiegna, P.Palestri and L.Selmi, Monte-CarloSimulation of Decananometric Double-Gate SOI devices: Multi-Subband vs. 3D-ElectronGas with Quantum Corrections, Proc. ESSDERC 2006, pp.162-165.

[CI87] E.Vianello, F.Driussi, D.Esseni, L.Selmi, M.J.van Duuren and F.Widdershoven, DoesMulti-Trap Assisted Tunneling explain the oxide thickness dependence of the Statistics ofSILC in FLASH Memory Arrays ?, Proc. ESSDERC 2006, pp.403-406.

[CI88] T. Vanhoucke, G.A.M. Hurkx, D. Panko, R. Campos, A. Piontek, P. Palestri, L. SelmiPhysical Description of the Mixed-Mode Degradation Mechanism for High PerformanceBipolar Transistors, Proc. IEEE BCTM, 2006, pp.25-28.

[CI89] D.Esseni, P. Palestri and L.Selmi, Transport in deca-nanometric MOSFETs: from band-structure to on-currents, invited paper, Proc. IEEE IEDM, 2006, pp.933-936.

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[CI90] P. Palestri R.Clerc, D.Esseni, L.Lucci and L.Selmi, Multi-Subband-Monte-Carlo investi-gation of the mean free path and of the kT layer in degenerated quasi ballistic nanoMOS-FETs, Proc. IEEE IEDM, 2006, pp.945-948.

[CI91] A.Arreghini, F.Driussi, D.Esseni, L.Selmi, M.J.van Duuren, and R. van Schaijk, Experi-mental Extraction of Charge Centroid and of Charge Type in the P/E operation of SONOSMemory Cells, Proc. IEEE IEDM, 2006, pp.499-502.

[CI91] R. Nonis, E. Palumbo, P. Palestri, L. Selmi, A Model to Understand Current Consump-tion, Maximum Operating Frequency And Scaling Trends Of MCML Frequency Dividers,pag. 329–332, PRIME 2006 (2nd Conference on Ph.D. Research in MicroElectronics andElectronics) ISBN 1-4244-0156-9, Otranto (Italia), giugno 2006;

[CI92] N. Barin, D. Brunel, C. Busseret, A. Campera, P. A. Childs, F. Driussi, C. Fiegna,G. Fiori, R. Gusmeroli, G. Iannaccone, M. Karner, H. Kosina, A. L. Lacaita, E. Langer,B. Majkusiak, C. Monzio Compagnoni, P. Palestri, A. Poncet, E. Sangiorgi, L. Selmi,A. S. Spinelli, J. Walczak, Quantum Mechanical simulation of capacitance-voltage andcurrent-voltage characteristics of advanced gate stacks: comparison between different ap-proaches, poster presentation, INC2, Arlington (USA), May 2006

[CI93] L. Lucci, M. Bescond, R. Clerc, P. Palestri, D. Esseni, L. Selmi, S. Cristoloveanu, Analysisof transport properties of nanoscale SOI devices: Full Quantum versus Semi Classicalmodels, pag. 43–44, EUROSOI 2007, Leuven (Belgio), gennaio 2007;

[CI94] R.Clerc, M. Ferrier, Q. Rafhay, G. Ghibaudo, P.Palestri, L. Lucci, L. Selmi, Progressin Technology Oriented Analytical Models for Advanced MOSFET devices, SEMIC Work-shop, Wuppertal (Germania), Feb. 2007, published online: http://www.math.uni-wuppertal.de/org/Num/conferences/clerc abst.pdf

[CI95] F. Driussi, D. Esseni, L.Selmi, P.-E. Hellstrom, G.Malm, J.Hallstedt, M.Ostling, T.J.Grasby,D.R.Leadley and X. Mescot , Experimental and Simulation Study of the Biaxial Strain andTemperature dependence of the Electron Mobility Enhancement in Si MOSFETs, Proc.IEEE ULIS Conference, March 2007, pp.21-24.

[CI96] A.Arreghini, N.Akil, F.Driussi, D.Esseni, L.Selmi and M.J.vanDuuren, Characterizationand Modeling of long term retention in SONOS Non Volatile Memories, Proc. ESSDERCConference, 2007, pp.406-409.

[CI97] F.Driussi, D.Esseni, L.Selmi, M.Schmidt, M.C.Lemme, H.Kurz, D.Buca, S.Mantl, M.Luysberg,R.Loo, D.Nguyen and M. Reiche, Fabrication, Characterization and Modeling of StrainedSOI MOSFETs with Very Large Effective Mobility, Proc. ESSDERC Conference, 2007,pp.315-318.

[CI98] M.Agostinelli, M.Alioto, D.Esseni and L.Selmi, Trading off static power and dynamicperformance in CMOS digital circuits: bulk versus double gate SOI MOSFETs, Proc.ESSDERC Conference, 2007, pp.191-194.

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[CI99] E.Sangiorgi, P.Palestri, D.Esseni, C.Fiegna, and L.Selmi, The Monte Carlo approach totransport modeling in decananometer MOSFETs, Plenary Invited paper, Proc. ESS-DERC Conference, 2007, pp.48-57.

[CI100] R.Clerc, Q.Rafhay, M.Ferrier, P.Palestri, G.Ghibaudo and L.Selmi, Technology OrientedAnalytical Models of MOSFETs in the Quasi Ballistic Regime, Proc. SSDM Conference,2007, pp..

[CI101] C.Fiegna, M.Braccioli, S.C.Brugger, F.M.Bufler, P.Dollfus, V.Aubry-Fortuna, C.Jungemann,B.Meinerzhagen, P.Palestri, S.Galdin-Retailleau, E.Sangiorgi, A.Schenk and L.Selmi, Com-parison of Monte Carlo Transport Models for Nanometer-Size MOSFETs, Proc. IEEESISPAD Conference, Vienna 2007, pp.57-60.

[CI102] M.Zilli, P.Palestri, D.Esseni, and L.Selmi, On the experimental determination of the bal-listic ratio in nanoMOSFETs, Proc. IEEE IEDM, 2007, pp.105.

[CI103] Q.Rafhay, P.Palestri, D.Esseni R.Clerc and L.Selmi, Mobility and Backscattering in Ger-manium n-type Inversion Layers, Proc. SSDM Conference, 2007, pp.46-47.

[CI104] L.Selmi, P.Palestri, D.Esseni L.Lucci and M.De Michielis, An efficient, mixed semiclassi-cal/quantum mechanical model to simulate planar and wire nano-transistors, Proc. Slo-Nano Conference, 2007, pp.82-83.

[CI105] M.De Michielis, P.Palestri, D.Esseni L.Selmi, A new Multi-Sub-Band Monte Carlo Simu-lator for Nano p-MOSFETs, Proc. IEEE ULIS Conference, 2008, pp.67-70.

[CI106] N.Serra, P.Palestri, G.D.J.Smit and L.Selmi, The Impact of Longitudinal NonuniformFin-Thickness on Quasi-Ballistic Transport in FinFETs, Proc. IEEE ULIS Conference,2008, pp.75-78.

[CI107] R.Clerc, P.Palestri, L.Selmi and G.Ghibaudo, Back-scattering in Quasi-Ballistic NanoMOS-FETs: The role of Non Thermal Carrier Distributions, Proc. IEEE ULIS Conference,2008, pp.125-128.

[CI108] M.Agostinelli, M.Alioto, D.Esseni and L.Selmi, Design and evaluation of mixed 3T-4TFinFET stacks for leakage reduction, Proc. PATMOS Conference, 2009, pp.31–41.

[CI109] P.Toniutti, P.Palestri, D.Esseni and L.Selmi, Revised analysis of the mobility and ION

degradation in high-k gate stacks: surface optical phonons vs. remote Coulomb scattering,Proc. ESSDERC 2008, Edinburg, Sept. 2008, pp.246-249.

[CI110] E. Vianello, F. Driussi, P. Palestri, A. Arreghini, D. Esseni, L.Selmi, N. Akil, M. vanDuuren and D. Golubovic, Impact of the Charge Transport in the Conduction Band onthe Retention of Silicon Nitride Based Memories, Proc. ESSDERC 2008, Edinburg, Sept.2008, pp.107-110.

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[CI111] D.Ponton,, P.Palestri, D.Esseni, L.Selmi, M.Tiebout, B.Parvais and G.Knoblinger, Designof UWB LNA in 45nm CMOS Technology: Planar Bulk vs. FinFET, Proc. IEEE ISCAS2008, , April 2008, pp.2701-2704.

[CI112] R. Clerc, P.Palestri, Q. Rafhay, M. Ferrier, G. Pananakakis, G. Ghibaudo, L. Selmi, QuasiBallistic transport in advanced MOSFET devices, Proceedings International Semiconduc-tor Conference (CAS), Sinaia (RO), 15-17 ottobre 2007, pp.35-40.

[CI112] E.Sangiorgi, P.Palestri, D.Esseni, C.Fiegna, L. Selmi, Monte Carlo modeling of nanome-ter scale MOSFETs, International Workshop on the Physics of Semiconductor Devices(IWPSD), Mumbay (India), dicembre 2007, pp.68–73.

[CI113] M. Schmidt, M.C. Lemme, H.D.B. Gottlob, H. Kurz, F. Driussi, L. Selmi, Mobility Extrac-tion of UTB n-MOSFETs down to 0.9 nm SOI thickness, Proc. IEEE ULIS Conference,Aachen, 2009, pp.27-30.

[CI114] P. Palestri, C. Alexander, A. Asenov, G. Baccarani, A. Bournel, M. Braccioli, B. Cheng, P.Dollfus, A. Esposito, D. Esseni, A. Ghetti, C. Fiegna, G. Fiori, V. Aubry-Fortuna, G. Ian-naccone, A. Martinez, B. Majkusiak, S. Monfray, S. Reggiani, C. Riddet, J. Saint-Martin,E. Sangiorgi, A. Schenk, L. Selmi, L. Silvestri, J. Walczak,Comparison of Advanced Trans-port Models for Nanoscale nMOSFETs, Proc. IEEE ULIS Conference, Aachen, 2009,pp.125-128.

[CI115] L. De Michielis, K. Boucart, K. E. Moselund, D. Bouvet, P. Dobrosz, S. Olsen, A. O’Neill,L. Lattanzio, L. Selmi, and A. M. Ionescu, Optimization of the Channel Lateral StrainProfile for Improved Performance of Multi-Gate MOSFETs, VLSI-TSA, Taiwan, 2009,p.119–120.

[CI116] L. De Michielis, L. Selmi and A. M. Ionescu, A model for robust electrostatic design ofnanowire FETs with arbitrary polygonal cross sections, Proc. ESSDERC 2009, Athens,Sept. 2009, pp.472-475.

[CI117] M.Bresciani, P.Palestri, D.Esseni, L. Selmi, A better understanding of the low-field mo-bility in Graphene Nano-ribbons, Proc. ESSDERC 2009, Athens, Sept. 2009, pp.480-483.

[CI118] E.Vianello, L.Perniola, P.Blaise, G.Molas, J.P.Colonna, F.Driussi, P.Palestri, D.Esseni,L. Selmi, N.Rochat, C.Licitra, D.Lafond, R.Kies, G.Reimbold, B.De Salvo and F.Boulanger,New insight on the charge trapping mechanisms of SiNbased memory by atomistic simu-lations and electrical modeling, Proc. IEEE IEDM, Dec. 2009, pp.4.5.1–4.5.4.

[CI119] N.Serra, F.Conzatti, D.Esseni, M.De Michielis, P.Palestri, L. Selmi, S.Thomas, T.E.Whall,E.H.C.Parker, D.R.Leadley, L. Witters, A.Hikavyy, M.J.Hytch, F.Houdellier, E.Snoeck,T.J.Wang, W.C.Lee, G.Vellianitis, M.J.H.van Dal, B.Duriez, G.Doornbos and R.J.P.Lander,Experimental and physics based modeling assessment of strain induced mobility enhance-ment in FinFETs, Proc. IEEE IEDM, Dec. 2009, pp.-.

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[CI120] M.Bocquet, E.Vianello, G.Molas, L.Perniola, H.Grampeix, F.Martin, J.P.Colonna, A.M.Papon,P.Brianceau, M.Gly, B.De Salvo, G.Pananakakis, G.Ghibaudo, L. Selmi, An in-depth in-vestigation of physical mechanisms governing SANOS memories characteristics, Proc.International memory Workshop, 2009, pp. 1-4, DOI10.1109/IMW.2009.5090579.

[CI121] A.Zaka, Q.Rafhay, P.Palestri, R.Clerc, D.Rideau, L. Selmi, C.Tavernier, H.Jaouen, Onthe Accuracy of Current TCAD Hot Carrier Injection Models for the Simulation of Degra-dation Phenomena in Nanoscale Devices, Proc. International Semiconductor Device Re-search Conference (ISDRS), 2009, pp. 1-2, DOI10.1109/ISDRS.2009.5378310.

[CI122] V.Gudmundsson, P.Palestri, P.-E.Hellstrom, L. Selmi and M.Ostling, Multi-subband MonteCarlo simulation of fully-depleted silicon-on-insulator Schottky barrier MOSFETs, Proc.Int. Conf. on Ultimate Integration on Silicon (ULIS), Glasgow, March 2010, pp. 61–64.

[CI123] P.Toniutti, M.De Michielis, P.Palestri, F.Driussi, D.Esseni and L. Selmi, Understandingthe mobility reduction in MOSFETs featuring high- dielectrics Proc. Int. Conf. onUltimate Integration on Silicon (ULIS), Glasgow, March 2010, pp. 65–68.

[CI124] SANGIORGI E and ALEXANDER C and ASENOV A and AUBRY-FORTUNA V andBACCARANI G and BOURNEL A and BRACCIOLI M and CHENG B and DOLLFUSP and ESPOSITO A and ESSENI D and FENOUILLET-BERANGER C and FIEGNA Cand FIORI G and GHETTI A and IANNACCONE G and MARTINEZ A and MAJKU-SIAK B and MONFRAY S and PALESTRI P and PEIKERT V and REGGIANI S andRIDDET C and SAINT-MARTIN J and SCHENK A L. Selmi and SILVESTRI L andWALCZAK J, Drain Current Computation in Nanoscale nMOSFETs: Comparison ofTransport Models, Proc. 27th Int. Conf. on Microelectronics (MIEL 2010), Nis (Serbia),May 2010, pp.3–7.

[CI125] E.Vianello, E.Nowak, L.Perniola, F.Driussi, P.Blaise,G.Molas, B.De Salvo, and L. Selmi,A Consistent Explanation of the Role of the SiN Composition on the Program/RetentionCharacteristics of MANOS and NROM like Memories, Proc. International MemoryWorkshop (IMW), Seoul (Korea), May 2010, pp.106–109.

[CI126] M.Bresciani, A.Paussa, P.Palestri, D.Esseni and L. Selmi, Low-Field Mobility and High-Field Drift Velocity in Graphene Nanoribbons and Graphene Bilayers, Proc. IEEE IEDM,Dec. 2010, pp.724–727.

[CI127] F.Conzatti, P.Toniutti, D.Esseni, P.Palestri and L. Selmi, Simulation study of the on-current improvements in Ge and sGe versus Si and sSi nano-MOSFETs, Proc. IEEEIEDM, Dec. 2010, pp. 363–366.

[CI128] D.Ponton, P.Palestri, G.Knoblinger, M.Fulde and L. Selmi, LC-Oscillator featuring in-dependent gate biasing implemented in 32 nm CMOS technology, Proceedings of the In-ternational Conference on Microelectronics, doi: 10.1109/ICM.2010.5696111, pp.184–187,2010.

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[CI129] E.Vianello, E.Nowak, D.Mariolle, N.Chevalier, L.Perniola, G.Molas, J.Colonna, F.Driussiand L. Selmi, Direct Probing of Trapped Charge Dynamics in SiN by Kelvin Force Mi-croscopy, Proc. Int. Conf. on Microelectronic Test Structures (ICMTS), Tokyo, March2010, pp.94–97.

[CI130] BUFLER F. M, AUBRY-FORTUNA V, BOURNEL A, BRACCIOLI M, DOLLFUSP, ESSENI D, FIEGNA C, GAMIZK F, DE MICHIELIS M, PALESTRI P, SAINT-MARTIN J, SAMPEDROK C, SANGIORGI E, L. Selmi, TONIUTTI P, Comparison ofSemiclassical Transport Formulations Including Quantum Corrections for Advanced De-vices with High-Gate Stacks, Proc. Int. Workshop on Computational Electronic (IWCE),Pisa, Ottobre 2010, pp.312–322.

[CI131] L.De Michielis, M.Iellina, P.Palestri, A.M.Ionescu and L. Selmi, Tunneling Path Impacton Semiclassical Numerical Simulations of TFET Devices, Proc. Int. Conf. on UltimateIntegration on Silicon (ULIS), Cork, March 2011, pp. 146–149.

[CI132] A.Revelant, L.Lucci, L. Selmi and B.Ankele, Device Variability and Correlation Controlby Automated Tuning of SPICE Cards to PCM Measurements, Proc. IEEE Int. Conf.on Microelectronic Test Structures (ICMTS), Amsterdam, March 2011, pp.147–152.

[CI133] A.Paussa, M.Bresciani, D.Esseni, P.Palestri and L. Selmi, Phonon Limited Uniform Trans-port in Bilayer Graphene Transistors, Proc. ESSDERC 2011, Helsinky, Sept. 2011,pp.XXX–XXX.

[CI134] F. Conzatti, M.G. Pala, D. Esseni, E. Bano, L. Selmi, A simulation study of strain inducedperformance enhancements in InAs nanowire Tunnel-FETs, Proc. IEEE IEDM, Dec.2011, pp.XXX–XXX.

[CI135] A.Paussa, M.Geromel, P.Palestri, M.Bresciani, D.Esseni and L. Selmi, Simulation ofgraphene nanoscale RF transistors including scattering and generation/recombinationmechanisms,Proc. IEEE IEDM, Dec. 2011, pp.XXX–XXX.

Books, Book chapters, Tutorials, PhD Courses, Summer Schools:

[L1] L. Selmi and C.Fiegna, Physical Aspects of Cell Operation and Reliability, in “Flash Mem-ories”, P.Cappelletti, C.Golla, P.Olivo and E.Zanoni eds., chap.4, Kluwer, 1999, pp.153-240.

[L2] E.Franchi Scarselli e L. Selmi, Esercizi d’Esame di Elettronica Digitale, Patron, 1998.

[L3] L. Selmi editor, Proceedings of the 2001 INFOS Conference, Graphis, Udine, 2001.

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[L4] L. Selmi, E.Sangiorgi editors, Microelectronic Engineering Special Issue devoted to the2001 Insulating Films on Semiconductors Conference, INFOS 2001, vol.59, Nov. 2001,Elsevier Science Publishing, Amsterdam, pp.55.

[L5] L. Selmi, E.Sangiorgi editors, Proceedings of the IEEE ULIS 2003 Conference, Udine,2003, ISBN: 88-900-984-0-6.

[L6] L. Selmi guest editor, Special Issue of Solid State Electronics devoted to the IEEE Ulti-mate Integration of Silicon (ULIS) 2003 Conference, Elsevier 2003.

[L7] L. Selmi, Characterization of Mobility and Carrier Transport Properties of Ultra ThinBody MOS Devices, Tutorial at the 2008 IEEE International Conference on Microelec-tronic Test Structures, Edinburg, 2008.

[L8] L. Selmi, Introduction to Semiconductor Device Characterization, Tutorial Lesson at the2006 SINANO Summer School, Bertinoro, 2006.

[L9] L. Selmi, FLASH Memories, PhD Course of the International Doctorate School EEATS,Grenoble, June 2006 and June 2008.

[L10] L. Selmi, FLASH Memories, Socrates-Erasmus course at the University of Twente, TheNetherlands, March 2007.

[L11] L. Selmi, Hot Carriers in Semiconductors , PhD Course of the International DoctorateSchool EEATS, Grenoble, July 2007.

[L12] D.Esseni, P.Palestri and L. Selmi editors, Proceedings of the IEEE ULIS 2008 Conference,Udine, 2008, ISBN: 978-1-4244-1730-8, Library of Congress: 2007906907.

[L13] D.Esseni, P.Palestri and L. Selmi editors, Special Issue of Solid State Electronics devotedto the IEEE Ultimate Integration of Silicon (ULIS) 2008 Conference, Elsevier 2009.

[L14] L. Selmi, Modeling of Ultra-Thin Body SOI nanotransistors, Tutorial Lecture at the 2009EUROSOI Conference, Goteborg.

[L15] L. Selmi, Characterization of carrier transport and mobility of thin semiconductor layers,Tutorial Lecture at the 2008 IEEE ICMTS Conference.

[L16] E.Sangiorgi, S.Eminente, C.Fiegna, P.Palestri, D.Esseni and L. Selmi, Quasiballistic Trans-port in Nano-MOSFETs, in S.Luryi, J.Xu, A.Zaslawsky. (ed.) (2007) ”Future Trends inMicroelectronics: Up the Nano Creek”, J. Wisley & Sons, Inc., ISBN/ISSN: ISBN 978-0-470-08146-4, pp. 287-296.

[L17] BELLEVILLE M, BOURGOIN J-P, CASTELLO R, DE MAN H, GESSNER T, SCHULZS, IONESCU A, L. Selmi, SEMERIA M, SKOTNICKI T, TENHUNEN H, THEWES R,VAN ROSSUM M, VEENDRICK H, WIDDERSHOVEN F., Towards and Beyond 2015:

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technology, devices, circuits and systems, Medea+ Scientific Committee, 2006, pp. 1–74.

[L18] Q. Rafhay, R. Clerc, G. Ghibaudo, P. Palestri and L. Selmi, Modeling of End of theRoadmap nMOSFET with Alternative Channel Material, in Balestra F. (ed.) (2010)”Nanoscale CMOS - Innovative Materials, Modeling and Characterization”, Wiley, Hobo-ken, NJ, pp. 287-334.

[L19] D.Esseni, P. Palestri and L. Selmi, Nanoscale MOS transistors: Semiclassical Modelingand Applications, Cambridge University Press, 2011, ISBN:978-0-521-51684-6.

International Patents:

[B1] D.Esseni, L. Selmi, R.Bez and A.Modelli, US patent number US6734490, concesso 11maggio 2004.

Research Reports:

[RR1] L. Selmi, H. S. Wong, E. Sangiorgi, M. Lanzoni and M. Manfredi, Investigation of HotElectron Luminescence in Silicon by means of Dual Gate MOS Structures , IBM ResearchReport, RC 19192 (83607), Yorktown Heights, 10-4-1993.

[RR2] P.Palestri, C.Fiegna, L. Selmi, M.S.Peter, G.A.M.Hurkx, J.W.Slotboom and E.Sangiorgi,Analysis of highly non-uniform collector doping profiles for the optimization of the break-down / speed trade off in advanced BJTs, Philips Research Nat. Laboratories Report808/99, Eindhoven, 4-1999.

[RR3] P.Palestri, L. Selmi, G.A.M.Hurkx, J.W.Slotboom, D.Terpstra, M.Peter, R.Woltjer andE. Sangiorgi, Non Local Electron and Hole Impact Ionization in Advanced Si BJTs, PhilipsResearch Nat. Laboratories Report NL-UR806/00, Eindhoven, 3-2000.

Papers on National Journals or in Italian:

[RN1] L. Selmi, Progetto e Caratterizzazione di dipositivi e circuiti integrati a semiconduttore, Tesi per il conseguimento del Dottorato di Ricerca in Ingegneria Elettronica ed Infor-matica, Bologna, 1992.

[RN2] B. Ricco, M. Favalli and L. Selmi, Logiche di tipo BiCMOS , Alta Frequenza, vol.3, n.1,Gennaio 1991, pp.25.

[RN3] L. Selmi, Problematiche di affidabilita , Atti del Corso di Formazione avanzata ”Memoriee Microprocessori”, Tecnopolis CSATA, Valenzano, Bari, 30 giugno - 3 luglio 1992, pp.34.

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[RN4] C. Fiegna and L. Selmi, Problemi della ricerca sulle Tecnologie CMOS , Alta Frequenza,vol.7, n.1, Gennaio 1995, pp.25.

[RN5] L. Selmi, Memorie di tipo FLASH EEPROM: principi di funzionamento e applicazioni,Atti della Scuola Estiva in Ingegneria dell’Informazione, Bressanone, 1998, pp.8-42.

[RN6] L. Selmi, Teoria dei dispositivi FET, Atti della VIII Scuola Nazionale di Scienza deiMateriali, INFM, Genova, 4 ottobre 1999.

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