ptolemy ii (uc berkeley) graphical entry of models components are ‘actors’ actors designed in...
DESCRIPTION
Automated Modeling and Emulation of Interconnect Designs for Many-Core Chip Multiprocessors. Colin J. Ihrig, Rami Melhem, and Alex K. Jones University of Pittsburgh Email: [email protected], [email protected], [email protected]. ACME Actor Generator. Problem - PowerPoint PPT PresentationTRANSCRIPT
Ptolemy II (UC Berkeley)
Graphical entry of models
Components are ‘actors’Actors designed in Java
Ptolemy II Graphical Model CreationPtolemy II Graphical Model Creation
ACME Actor Generator
SoC Generation Tool FlowSoC Generation Tool Flow
2x2 Mesh Interconnect Network2x2 Mesh Interconnect Network
Xilinx Platform Studio SystemXilinx Platform Studio System
Processor Based Actors
Design complex components
Example: Switch arbiters
Describe functionality in C
Use Java Native Interface with Ptolemy II
2x2 Mesh Interconnect Network2x2 Mesh Interconnect Network
ACME actor library ACME actor library mirrors Ptolemy’s mirrors Ptolemy’s
Java libraryJava library
Xilinx library contains IP Xilinx library contains IP blocks and board blocks and board
descriptionsdescriptions
Emulate caches and interconnect in Emulate caches and interconnect in FPGA fabricFPGA fabric
Leave remaining components in Leave remaining components in softwaresoftware
ACME
Emulate systems using FPGAs
System emulation
Rapid SoC prototyping
Hardware design
Logic Containing
VHDL Actors
Microblaze
Processor
Systems
Serial Port
for PC Communication
Actor Generator GUIActor Generator GUI
Extend Ptolemy II GUI for Extend Ptolemy II GUI for graphical actor creationgraphical actor creation
Generate skeleton code for actorGenerate skeleton code for actor
ACME Actor GeneratorACME Actor Generator
Network
Switch
Processing Node
Automated Modeling and Emulation of Interconnect Automated Modeling and Emulation of Interconnect Designs for Many-Core Chip MultiprocessorsDesigns for Many-Core Chip Multiprocessors
Colin J. Ihrig, Rami Melhem, and Alex K. JonesColin J. Ihrig, Rami Melhem, and Alex K. Jones
University of PittsburghUniversity of Pittsburgh
Email: [email protected], [email protected], [email protected]: [email protected], [email protected], [email protected]
Emulation AugmentationEmulation Augmentation
User specified latency and User specified latency and throughput circuitthroughput circuit
Processor / hardware synchronization Processor / hardware synchronization via a hardware barrier circuitvia a hardware barrier circuit
Three cycle throughput
One additional latency cycleProcessors
set / reset barrier
Barrier clocks custom logic
Problem
Architectures moving towards many cores
Need to study new architectures
Software simulators do not scale well
System design is time consuming