prototyping with surface mount technology · prototyping strategies divide and conquer approach...
TRANSCRIPT
Prototyping with SurfaceMount Technology
Take your Design to the Market
Well before Sunset
Ajith Narayanan
Zoid Labs
28 Feb 2019
Zoid Labs IEW 2019 1
From Idea to Product
Idea Proto-1
Proto-2
. . .Proto-N
Product
Zoid Labs IEW 2019 2
Context:
• Limited Resources
• Budgetary constraints
• Desire to in-source• e.g to protect IP
• e.g to build technology base
• Non-trivial level of complexity
• Time to Market
Overview
1 Introduction
2 Prototyping – Strategies, Activities,
Bottlenecks
3 SMT PCB Assembly process & Tips
4 Challenges in prototyping with SMT
5 Reducing cycle time with in-house assembly
6 Streamlining with DFP (Design for
Prototyping)
7 Equipment and Process
8 ConclusionZoid Labs IEW 2019 4
Overview
1 Introduction
2 Prototyping – Strategies, Activities,
Bottlenecks
3 SMT PCB Assembly process & Tips
4 Challenges in prototyping with SMT
5 Reducing cycle time with in-house assembly
6 Streamlining with DFP (Design for
Prototyping)
7 Equipment and Process
8 ConclusionZoid Labs IEW 2019 5
Overview
1 Introduction
2 Prototyping – Strategies, Activities,
Bottlenecks
3 SMT PCB Assembly process & Tips
4 Challenges in prototyping with SMT
5 Reducing cycle time with in-house assembly
6 Streamlining with DFP (Design for
Prototyping)
7 Equipment and Process
8 ConclusionZoid Labs IEW 2019 6
Overview
1 Introduction
2 Prototyping – Strategies, Activities,
Bottlenecks
3 SMT PCB Assembly process & Tips
4 Challenges in prototyping with SMT
5 Reducing cycle time with in-house assembly
6 Streamlining with DFP (Design for
Prototyping)
7 Equipment and Process
8 ConclusionZoid Labs IEW 2019 7
Overview
1 Introduction
2 Prototyping – Strategies, Activities,
Bottlenecks
3 SMT PCB Assembly process & Tips
4 Challenges in prototyping with SMT
5 Reducing cycle time with in-house assembly
6 Streamlining with DFP (Design for
Prototyping)
7 Equipment and Process
8 ConclusionZoid Labs IEW 2019 8
Overview
1 Introduction
2 Prototyping – Strategies, Activities,
Bottlenecks
3 SMT PCB Assembly process & Tips
4 Challenges in prototyping with SMT
5 Reducing cycle time with in-house assembly
6 Streamlining with DFP (Design for
Prototyping)
7 Equipment and Process
8 ConclusionZoid Labs IEW 2019 9
Overview
1 Introduction
2 Prototyping – Strategies, Activities,
Bottlenecks
3 SMT PCB Assembly process & Tips
4 Challenges in prototyping with SMT
5 Reducing cycle time with in-house assembly
6 Streamlining with DFP (Design for
Prototyping)
7 Equipment and Process
8 ConclusionZoid Labs IEW 2019 10
Overview
1 Introduction
2 Prototyping – Strategies, Activities,
Bottlenecks
3 SMT PCB Assembly process & Tips
4 Challenges in prototyping with SMT
5 Reducing cycle time with in-house assembly
6 Streamlining with DFP (Design for
Prototyping)
7 Equipment and Process
8 ConclusionZoid Labs IEW 2019 11
Introduction: SMT Basics
SMTchip
Zoid Labs IEW 2019 12
Introduction: SMT Basics
SMTboard
Zoid Labs IEW 2019 13
Introduction: SMT Basics
SMTMayhem
Zoid Labs IEW 2019 14
Introduction: SMT Basics
MoreMayhem
Zoid Labs IEW 2019 15
Introduction: SMT Basics
0201=0.6 x0.3mm,20 x10mil,0.02 x0.01”
Zoid Labs IEW 2019 16
Introduction: SMT Basics
0080048x4mil=0.2 x0.1mm
Zoid Labs IEW 2019 17
Section 2
Prototyping:Strategies,Activities,Bottlenecks
Zoid Labs IEW 2019 18
Prototyping Strategies
• Divide and Conquer approach• E.g. Build and test a sub-circuit• More common towards early stages of
prototyping• Partial assembly → Full assembly
• Big Bang approach
• Build and test completely assembled PCB• Typically for product-intent PCBs• More common towards later stages of
prototyping
Zoid Labs IEW 2019 19
Prototyping Strategies
• Divide and Conquer approach• E.g. Build and test a sub-circuit• More common towards early stages of
prototyping• Partial assembly → Full assembly
• Big Bang approach
• Build and test completely assembled PCB• Typically for product-intent PCBs• More common towards later stages of
prototyping
Zoid Labs IEW 2019 20
Prototyping Strategies
• Divide and Conquer approach• E.g. Build and test a sub-circuit• More common towards early stages of
prototyping• Partial assembly → Full assembly
• Big Bang approach
• Build and test completely assembled PCB• Typically for product-intent PCBs• More common towards later stages of
prototyping
Zoid Labs IEW 2019 21
Prototyping Strategies
• Divide and Conquer approach• E.g. Build and test a sub-circuit• More common towards early stages of
prototyping• Partial assembly → Full assembly
• Big Bang approach
• Build and test completely assembled PCB• Typically for product-intent PCBs• More common towards later stages of
prototyping
Zoid Labs IEW 2019 22
Prototyping Strategies
• Divide and Conquer approach• E.g. Build and test a sub-circuit• More common towards early stages of
prototyping• Partial assembly → Full assembly
• Big Bang approach
• Build and test completely assembled PCB• Typically for product-intent PCBs• More common towards later stages of
prototyping
Zoid Labs IEW 2019 23
Prototyping Strategies
• Divide and Conquer approach• E.g. Build and test a sub-circuit• More common towards early stages of
prototyping• Partial assembly → Full assembly
• Big Bang approach
• Build and test completely assembled PCB• Typically for product-intent PCBs• More common towards later stages of
prototyping
Zoid Labs IEW 2019 24
Prototyping Strategies
• Divide and Conquer approach• E.g. Build and test a sub-circuit• More common towards early stages of
prototyping• Partial assembly → Full assembly
• Big Bang approach
• Build and test completely assembled PCB• Typically for product-intent PCBs• More common towards later stages of
prototyping
Zoid Labs IEW 2019 25
Prototyping Strategies
• Divide and Conquer approach• E.g. Build and test a sub-circuit• More common towards early stages of
prototyping• Partial assembly → Full assembly
• Big Bang approach
• Build and test completely assembled PCB• Typically for product-intent PCBs• More common towards later stages of
prototyping
Zoid Labs IEW 2019 26
Activities in Prototyping
Design
Circuit
SchematicDesign
PCB
Layout
Fabricate
PCBAssemble
PCB
Test
Zoid Labs IEW 2019 27
Activities (in successive steps)
(?) ModifySchematic
(?) ModifyLayout
(?) Refab/rework PCB(?) Replace
parts/Reassemble
PCB
Test
Zoid Labs IEW 2019 28
Iterative process
• Say 5 iterations
• If a typ. iteration takes 1 day ⇒ 5 days
• If it takes 4 weeks ⇒ 5 months!
• ⇒ Critical to have fast turn-around
• ⇒ Cycle time can make it or break it!
Zoid Labs IEW 2019 29
Iterative process
• Say 5 iterations
• If a typ. iteration takes 1 day ⇒ 5 days
• If it takes 4 weeks ⇒ 5 months!
• ⇒ Critical to have fast turn-around
• ⇒ Cycle time can make it or break it!
Zoid Labs IEW 2019 30
Iterative process
• Say 5 iterations
• If a typ. iteration takes 1 day ⇒ 5 days
• If it takes 4 weeks ⇒ 5 months!
• ⇒ Critical to have fast turn-around
• ⇒ Cycle time can make it or break it!
Zoid Labs IEW 2019 31
Iterative process
• Say 5 iterations
• If a typ. iteration takes 1 day ⇒ 5 days
• If it takes 4 weeks ⇒ 5 months!
• ⇒ Critical to have fast turn-around
• ⇒ Cycle time can make it or break it!
Zoid Labs IEW 2019 32
Iterative process
• Say 5 iterations
• If a typ. iteration takes 1 day ⇒ 5 days
• If it takes 4 weeks ⇒ 5 months!
• ⇒ Critical to have fast turn-around
• ⇒ Cycle time can make it or break it!
Zoid Labs IEW 2019 33
Bottlenecks
• Modify schematic design • Modify the PCB Layout • Re-fab PCB • Rework (modify/hack) PCB • Replace part(s) . . . • Assemble new PCB . . . • Test
Zoid Labs IEW 2019 34
Bottlenecks
• Modify schematic design • Modify the PCB Layout • Re-fab PCB • Rework (modify/hack) PCB • Replace part(s) . . . • Assemble new PCB . . . • Test
Zoid Labs IEW 2019 35
Bottlenecks
• Modify schematic design • Modify the PCB Layout • Re-fab PCB • Rework (modify/hack) PCB • Replace part(s) . . . • Assemble new PCB . . . • Test
Zoid Labs IEW 2019 36
Bottlenecks
• Modify schematic design • Modify the PCB Layout • Re-fab PCB • Rework (modify/hack) PCB • Replace part(s) . . . • Assemble new PCB . . . • Test
Zoid Labs IEW 2019 37
Bottlenecks
• Modify schematic design • Modify the PCB Layout • Re-fab PCB • Rework (modify/hack) PCB • Replace part(s) . . . • Assemble new PCB . . . • Test
Zoid Labs IEW 2019 38
Bottlenecks
• Modify schematic design • Modify the PCB Layout • Re-fab PCB • Rework (modify/hack) PCB • Replace part(s) . . . • Assemble new PCB . . . • Test
Zoid Labs IEW 2019 39
Bottlenecks
• Modify schematic design • Modify the PCB Layout • Re-fab PCB • Rework (modify/hack) PCB • Replace part(s) . . . • Assemble new PCB . . . • Test
Zoid Labs IEW 2019 40
Section 3
SMT Assembly Process&Process Tips
Zoid Labs IEW 2019 41
SMT PCB Assembly – PCBs, Stencils
Unframed or “cut” stencil
Zoid Labs IEW 2019 42
SMT PCB Assembly – PCBs, Stencils
PCB after placing and reflow
Zoid Labs IEW 2019 43
SMT PCB Assembly – PCBs, Stencils
Assembled PCB, with minor rework
Zoid Labs IEW 2019 44
SMT PCB Assembly Process (1/3)
PCB, Stencil, Paste . . . Action!
• Lay the PCB right side up, for stencilling
• Overlay with stencil, adjust until
registration is good
• Apply solder paste, squeegee through
• Examine solder paste coverage
• Remove stencil without smudging
Zoid Labs IEW 2019 45
SMT PCB Assembly Process (1/3)
PCB, Stencil, Paste . . . Action!
• Lay the PCB right side up, for stencilling
• Overlay with stencil, adjust until
registration is good
• Apply solder paste, squeegee through
• Examine solder paste coverage
• Remove stencil without smudging
Zoid Labs IEW 2019 46
SMT PCB Assembly Process (1/3)
PCB, Stencil, Paste . . . Action!
• Lay the PCB right side up, for stencilling
• Overlay with stencil, adjust until
registration is good
• Apply solder paste, squeegee through
• Examine solder paste coverage
• Remove stencil without smudging
Zoid Labs IEW 2019 47
SMT PCB Assembly Process (1/3)
PCB, Stencil, Paste . . . Action!
• Lay the PCB right side up, for stencilling
• Overlay with stencil, adjust until
registration is good
• Apply solder paste, squeegee through
• Examine solder paste coverage
• Remove stencil without smudging
Zoid Labs IEW 2019 48
SMT PCB Assembly Process (1/3)
PCB, Stencil, Paste . . . Action!
• Lay the PCB right side up, for stencilling
• Overlay with stencil, adjust until
registration is good
• Apply solder paste, squeegee through
• Examine solder paste coverage
• Remove stencil without smudging
Zoid Labs IEW 2019 49
SMT PCB Assembly Process (2/3)
On their pads, get set. . . Go!• Pick and place components on wet PCB
• Ensure parts are correct• Ensure polarity/orientation• Don’t let solder paste dry up• If doing manually with tweezers, don’t let
parts fly!
• Put loaded PCB into oven
Run appropriate cooking profile
• Remove, Inspect, Re-heat if necessary
Zoid Labs IEW 2019 50
SMT PCB Assembly Process (2/3)
On their pads, get set. . . Go!• Pick and place components on wet PCB
• Ensure parts are correct• Ensure polarity/orientation• Don’t let solder paste dry up• If doing manually with tweezers, don’t let
parts fly!
• Put loaded PCB into oven
Run appropriate cooking profile
• Remove, Inspect, Re-heat if necessary
Zoid Labs IEW 2019 51
SMT PCB Assembly Process (2/3)
On their pads, get set. . . Go!• Pick and place components on wet PCB
• Ensure parts are correct• Ensure polarity/orientation• Don’t let solder paste dry up• If doing manually with tweezers, don’t let
parts fly!
• Put loaded PCB into oven
Run appropriate cooking profile
• Remove, Inspect, Re-heat if necessary
Zoid Labs IEW 2019 52
SMT PCB Assembly Process (2/3)
On their pads, get set. . . Go!• Pick and place components on wet PCB
• Ensure parts are correct• Ensure polarity/orientation• Don’t let solder paste dry up• If doing manually with tweezers, don’t let
parts fly!
• Put loaded PCB into oven
Run appropriate cooking profile
• Remove, Inspect, Re-heat if necessary
Zoid Labs IEW 2019 53
SMT PCB Assembly Process (2/3)
On their pads, get set. . . Go!• Pick and place components on wet PCB
• Ensure parts are correct• Ensure polarity/orientation• Don’t let solder paste dry up• If doing manually with tweezers, don’t let
parts fly!
• Put loaded PCB into oven
Run appropriate cooking profile
• Remove, Inspect, Re-heat if necessary
Zoid Labs IEW 2019 54
SMT PCB Assembly Process (2/3)
On their pads, get set. . . Go!• Pick and place components on wet PCB
• Ensure parts are correct• Ensure polarity/orientation• Don’t let solder paste dry up• If doing manually with tweezers, don’t let
parts fly!
• Put loaded PCB into oven
Run appropriate cooking profile
• Remove, Inspect, Re-heat if necessary
Zoid Labs IEW 2019 55
SMT PCB Assembly Process (2/3)
On their pads, get set. . . Go!• Pick and place components on wet PCB
• Ensure parts are correct• Ensure polarity/orientation• Don’t let solder paste dry up• If doing manually with tweezers, don’t let
parts fly!
• Put loaded PCB into oven
Run appropriate cooking profile
• Remove, Inspect, Re-heat if necessary
Zoid Labs IEW 2019 56
SMT PCB Assembly Process (3/3)
Finishing up!• Brush & clean with Iso-Propyl Alcohol (IPA)
• Test for power shorts
• . . . Go on to power up test
Zoid Labs IEW 2019 57
SMT PCB Assembly Process (3/3)
Finishing up!• Brush & clean with Iso-Propyl Alcohol (IPA)
• Test for power shorts
• . . . Go on to power up test
Zoid Labs IEW 2019 58
SMT PCB Assembly Process (3/3)
Finishing up!• Brush & clean with Iso-Propyl Alcohol (IPA)
• Test for power shorts
• . . . Go on to power up test
Zoid Labs IEW 2019 59
Process Tips
PCB & Stencil Fabrication
• Usually outsourcing is good.- $ and encourage outsourcing- Standard materials and spec, specialized job,chemical hazards, equipment/skills.
• But inspect results carefully.• “100% tested” may not be so! /• “Cut stencils” are cheap and good X
Zoid Labs IEW 2019 60
Process Tips
PCB & Stencil Fabrication
• Usually outsourcing is good.- $ and encourage outsourcing- Standard materials and spec, specialized job,chemical hazards, equipment/skills.
• But inspect results carefully.• “100% tested” may not be so! /• “Cut stencils” are cheap and good X
Zoid Labs IEW 2019 61
Process Tips
PCB & Stencil Fabrication
• Usually outsourcing is good.- $ and encourage outsourcing- Standard materials and spec, specialized job,chemical hazards, equipment/skills.
• But inspect results carefully.• “100% tested” may not be so! /• “Cut stencils” are cheap and good X
Zoid Labs IEW 2019 62
Process Tips
PCB & Stencil Fabrication
• Usually outsourcing is good.- $ and encourage outsourcing- Standard materials and spec, specialized job,chemical hazards, equipment/skills.
• But inspect results carefully.• “100% tested” may not be so! /• “Cut stencils” are cheap and good X
Zoid Labs IEW 2019 63
Paste and Cooking tips
Pasta!
• Use good “Lead Free” paste.Right Type (grain size - e.g. Type 3, Type 4)
• Store paste in fridgeLet it warm up before applying
Zoid Labs IEW 2019 64
Paste and Cooking tips
Pasta!
• Use good “Lead Free” paste.Right Type (grain size - e.g. Type 3, Type 4)
• Store paste in fridgeLet it warm up before applying
Zoid Labs IEW 2019 65
Section 4
ChallengesinPrototyping
Zoid Labs IEW 2019 66
Typical Challenges/Errors/Mistakes
• Design/Layout issues: /$$$
• Sufficient test access?
• Sufficient rework/repair access?
• Components used as per design?
• Correct placement done? (C12 in place
of R12?)
• Correct polarity / orientation?
• Correctly rated part used?
Zoid Labs IEW 2019 67
Typical Challenges/Errors/Mistakes
• Design/Layout issues: /$$$
• Sufficient test access?
• Sufficient rework/repair access?
• Components used as per design?
• Correct placement done? (C12 in place
of R12?)
• Correct polarity / orientation?
• Correctly rated part used?
Zoid Labs IEW 2019 68
Typical Challenges/Errors/Mistakes
• Design/Layout issues: /$$$
• Sufficient test access?
• Sufficient rework/repair access?
• Components used as per design?
• Correct placement done? (C12 in place
of R12?)
• Correct polarity / orientation?
• Correctly rated part used?
Zoid Labs IEW 2019 69
Typical Challenges/Errors/Mistakes
• Design/Layout issues: /$$$
• Sufficient test access?
• Sufficient rework/repair access?
• Components used as per design?
• Correct placement done? (C12 in place
of R12?)
• Correct polarity / orientation?
• Correctly rated part used?
Zoid Labs IEW 2019 70
Typical Challenges/Errors/Mistakes
• Design/Layout issues: /$$$
• Sufficient test access?
• Sufficient rework/repair access?
• Components used as per design?
• Correct placement done? (C12 in place
of R12?)
• Correct polarity / orientation?
• Correctly rated part used?
Zoid Labs IEW 2019 71
Typical Challenges/Errors/Mistakes
• Design/Layout issues: /$$$
• Sufficient test access?
• Sufficient rework/repair access?
• Components used as per design?
• Correct placement done? (C12 in place
of R12?)
• Correct polarity / orientation?
• Correctly rated part used?
Zoid Labs IEW 2019 72
Typical Challenges/Errors/Mistakes
• Design/Layout issues: /$$$
• Sufficient test access?
• Sufficient rework/repair access?
• Components used as per design?
• Correct placement done? (C12 in place
of R12?)
• Correct polarity / orientation?
• Correctly rated part used?
Zoid Labs IEW 2019 73
Some actual errors (mistakes)
Problem: Board worked for 3 days, then stopped.
Zoid Labs IEW 2019 74
Some actual errors (mistakes)
Problem: Board worked for 3 days, then stopped.
Culprit: Rating!
PCB with many decoupler caps (0.1 µF 10V)
Had a charge pump using one 0.1 µF 50V.
Assembly used the same capacitor for all.
Cap failed (dielectric punch through).
Zoid Labs IEW 2019 75
A fab error
Power board with fab error, a Vout shorted to GND
Zoid Labs IEW 2019 76
A Reflow soldering slip-up
Soldering defect revealed by careful inspection
Zoid Labs IEW 2019 77
Section 5
Reducing Cycle TimewithIn-house Assembly
Zoid Labs IEW 2019 78
Impact of errors
• Assembly error: rework 1 or entire batch
• PCB fabrication error: re-fab PCB, ...
• Schematic error: Re layout, re-fab, ...
• Fix and repeat tests
Zoid Labs IEW 2019 79
Impact of errors
• Assembly error: rework 1 or entire batch
• PCB fabrication error: re-fab PCB, ...
• Schematic error: Re layout, re-fab, ...
• Fix and repeat tests
Zoid Labs IEW 2019 80
Impact of errors
• Assembly error: rework 1 or entire batch
• PCB fabrication error: re-fab PCB, ...
• Schematic error: Re layout, re-fab, ...
• Fix and repeat tests
Zoid Labs IEW 2019 81
Impact of errors
• Assembly error: rework 1 or entire batch
• PCB fabrication error: re-fab PCB, ...
• Schematic error: Re layout, re-fab, ...
• Fix and repeat tests
Zoid Labs IEW 2019 82
Hardware-Software Co-Design
(Micheli & Gupta, Proc. IEEE, Vol.85, No.3, March 1997)
Zoid Labs IEW 2019 83
Partial Assembly & Incremental prototyping (1/2)
Examples:
• to test 1-channel in a 6-channel board
• for sub-circuit level prototyping
• for minimum h/w to get s/w dev started
• to skip some expensive parts (when not
immediately needed), e.g. connectors, some
peripherals
Zoid Labs IEW 2019 84
Partial Assembly & Incremental prototyping (1/2)
Examples:
• to test 1-channel in a 6-channel board
• for sub-circuit level prototyping
• for minimum h/w to get s/w dev started
• to skip some expensive parts (when not
immediately needed), e.g. connectors, some
peripherals
Zoid Labs IEW 2019 85
Partial Assembly & Incremental prototyping (1/2)
Examples:
• to test 1-channel in a 6-channel board
• for sub-circuit level prototyping
• for minimum h/w to get s/w dev started
• to skip some expensive parts (when not
immediately needed), e.g. connectors, some
peripherals
Zoid Labs IEW 2019 86
Partial Assembly & Incremental prototyping (1/2)
Examples:
• to test 1-channel in a 6-channel board
• for sub-circuit level prototyping
• for minimum h/w to get s/w dev started
• to skip some expensive parts (when not
immediately needed), e.g. connectors, some
peripherals
Zoid Labs IEW 2019 87
Partial Assembly & Incremental prototyping (2/2)
• Speeds up initial bring-up of proto and
test boards
• Allows Hw/Sw Co-Design during proto
• Reduces unpredictability arising from
external factors
• Reduces overall product development
time & cost
Have some in-house capability for h/w assembly!
Zoid Labs IEW 2019 88
Partial Assembly & Incremental prototyping (2/2)
• Speeds up initial bring-up of proto and
test boards
• Allows Hw/Sw Co-Design during proto
• Reduces unpredictability arising from
external factors
• Reduces overall product development
time & cost
Have some in-house capability for h/w assembly!
Zoid Labs IEW 2019 89
Partial Assembly & Incremental prototyping (2/2)
• Speeds up initial bring-up of proto and
test boards
• Allows Hw/Sw Co-Design during proto
• Reduces unpredictability arising from
external factors
• Reduces overall product development
time & cost
Have some in-house capability for h/w assembly!
Zoid Labs IEW 2019 90
Partial Assembly & Incremental prototyping (2/2)
• Speeds up initial bring-up of proto and
test boards
• Allows Hw/Sw Co-Design during proto
• Reduces unpredictability arising from
external factors
• Reduces overall product development
time & cost
Have some in-house capability for h/w assembly!
Zoid Labs IEW 2019 91
Partial Assembly & Incremental prototyping (2/2)
• Speeds up initial bring-up of proto and
test boards
• Allows Hw/Sw Co-Design during proto
• Reduces unpredictability arising from
external factors
• Reduces overall product development
time & cost
Have some in-house capability for h/w assembly!
Zoid Labs IEW 2019 92
Partial Assembly & Incremental prototyping (2/2)
• Speeds up initial bring-up of proto and
test boards
• Allows Hw/Sw Co-Design during proto
• Reduces unpredictability arising from
external factors
• Reduces overall product development
time & cost
Have some in-house capability for h/w assembly!
Zoid Labs IEW 2019 93
Assembly – Pick & Place
Zoid Labs IEW 2019 94
Assembly – on the desktop
Goals set for Zoid Labs’ Placerbot:
Placerbot
XTo fit desktopXBe portableXHandletypical partsXAccuracyXRepeatabilityXHandle cut tapesXAlso feed from trayXBe flexibleXEasy to use
Zoid Labs IEW 2019 95
Why have SMT proto capability in-house?
• To leverage Partial Assembly
• To reduce cycle time per iteration
• To reduce overall dev time and cost
• To reduce errors (e.g. below)
Zoid Labs IEW 2019 96
Why have SMT proto capability in-house?
• To leverage Partial Assembly
• To reduce cycle time per iteration
• To reduce overall dev time and cost
• To reduce errors (e.g. below)
Zoid Labs IEW 2019 97
Why have SMT proto capability in-house?
• To leverage Partial Assembly
• To reduce cycle time per iteration
• To reduce overall dev time and cost
• To reduce errors (e.g. below)
Zoid Labs IEW 2019 98
Why have SMT proto capability in-house?
• To leverage Partial Assembly
• To reduce cycle time per iteration
• To reduce overall dev time and cost
• To reduce errors (e.g. below)
Zoid Labs IEW 2019 99
Why have SMT proto capability in-house?
• To leverage Partial Assembly
• To reduce cycle time per iteration
• To reduce overall dev time and cost
• To reduce errors (e.g. below)
(from Placerbot UI)
Zoid Labs IEW 2019 100
Other benefits of in-house SMT prototyping
• Increased visibility / Early visibility into
all aspects of design
e.g. Mechanical issues, Thermal design
• Prepares for DFM and productization
• Total Control over IntellectualProperty
• Design and BOM optimization
Zoid Labs IEW 2019 101
Other benefits of in-house SMT prototyping
• Increased visibility / Early visibility into
all aspects of design
e.g. Mechanical issues, Thermal design
• Prepares for DFM and productization
• Total Control over IntellectualProperty
• Design and BOM optimization
Zoid Labs IEW 2019 102
Other benefits of in-house SMT prototyping
• Increased visibility / Early visibility into
all aspects of design
e.g. Mechanical issues, Thermal design
• Prepares for DFM and productization
• Total Control over IntellectualProperty
• Design and BOM optimization
Zoid Labs IEW 2019 103
Other benefits of in-house SMT prototyping
• Increased visibility / Early visibility into
all aspects of design
e.g. Mechanical issues, Thermal design
• Prepares for DFM and productization
• Total Control over IntellectualProperty
• Design and BOM optimization
Zoid Labs IEW 2019 104
Section 6
StreamliningwithDFP(DesignforPrototyping)
Zoid Labs IEW 2019 105
Basic Approach
DFM (Design for Manufacture) – Design Rules
DFP (Design for Prototyping) – Stricter RulesZoid Labs IEW 2019 106
Some DFP Tips (1/3)
(As practised at Zoid Labs)
General
• Provision fuses.(Final product may or may not include these)
• Use 0R’s (0Ω) or fuses to isolate power paths.• Have all DFP additions (0Ω etc) with 0805
footprints(smaller size ⇒ / / for tweezers)
Zoid Labs IEW 2019 107
Some DFP Tips (1/3)
(As practised at Zoid Labs)
General
• Provision fuses.(Final product may or may not include these)
• Use 0R’s (0Ω) or fuses to isolate power paths.• Have all DFP additions (0Ω etc) with 0805
footprints(smaller size ⇒ / / for tweezers)
Zoid Labs IEW 2019 108
Some DFP Tips (1/3)
(As practised at Zoid Labs)
General
• Provision fuses.(Final product may or may not include these)
• Use 0R’s (0Ω) or fuses to isolate power paths.• Have all DFP additions (0Ω etc) with 0805
footprints(smaller size ⇒ / / for tweezers)
Zoid Labs IEW 2019 109
More DFP Tips (2/3)
Testability
• Add testpoints liberally- say 0.5 x 0.5mm pad for occasional probing- Where needed to hook up a probe often, adda thru-hole pin pad.
• Provision configuration 0R’s- For intercepting signals- To provide alternate paths (mux/demuxing)- Strapping options
(e.g. mode inputs, I2C addresses)• Allow space for test/probe access
Zoid Labs IEW 2019 110
More DFP Tips (2/3)
Testability
• Add testpoints liberally- say 0.5 x 0.5mm pad for occasional probing- Where needed to hook up a probe often, adda thru-hole pin pad.
• Provision configuration 0R’s- For intercepting signals- To provide alternate paths (mux/demuxing)- Strapping options
(e.g. mode inputs, I2C addresses)• Allow space for test/probe access
Zoid Labs IEW 2019 111
More DFP Tips (2/3)
Testability
• Add testpoints liberally- say 0.5 x 0.5mm pad for occasional probing- Where needed to hook up a probe often, adda thru-hole pin pad.
• Provision configuration 0R’s- For intercepting signals- To provide alternate paths (mux/demuxing)- Strapping options
(e.g. mode inputs, I2C addresses)• Allow space for test/probe access
Zoid Labs IEW 2019 112
More DFP Tips (3/3)
Footprints, Layout, Stencil
• Use rounded pads in footprints- For small passives- Less likely to ’tombstone’- Better for IC’s too
• Careful with big thermal pads (belly pads)!• Prefer non-BGA packages if possible
- More leeway with solder reflow profile• Include fiducial marks (local,global)• Include fiducial marks in Stencil for easy
registration visually• Undersize stencil openings slightly
Zoid Labs IEW 2019 113
More DFP Tips (3/3)
Footprints, Layout, Stencil
• Use rounded pads in footprints- For small passives- Less likely to ’tombstone’- Better for IC’s too
• Careful with big thermal pads (belly pads)!• Prefer non-BGA packages if possible
- More leeway with solder reflow profile• Include fiducial marks (local,global)• Include fiducial marks in Stencil for easy
registration visually• Undersize stencil openings slightly
Zoid Labs IEW 2019 114
More DFP Tips (3/3)
Footprints, Layout, Stencil
• Use rounded pads in footprints- For small passives- Less likely to ’tombstone’- Better for IC’s too
• Careful with big thermal pads (belly pads)!• Prefer non-BGA packages if possible
- More leeway with solder reflow profile• Include fiducial marks (local,global)• Include fiducial marks in Stencil for easy
registration visually• Undersize stencil openings slightly
Zoid Labs IEW 2019 115
More DFP Tips (3/3)
Footprints, Layout, Stencil
• Use rounded pads in footprints- For small passives- Less likely to ’tombstone’- Better for IC’s too
• Careful with big thermal pads (belly pads)!• Prefer non-BGA packages if possible
- More leeway with solder reflow profile• Include fiducial marks (local,global)• Include fiducial marks in Stencil for easy
registration visually• Undersize stencil openings slightly
Zoid Labs IEW 2019 116
More DFP Tips (3/3)
Footprints, Layout, Stencil
• Use rounded pads in footprints- For small passives- Less likely to ’tombstone’- Better for IC’s too
• Careful with big thermal pads (belly pads)!• Prefer non-BGA packages if possible
- More leeway with solder reflow profile• Include fiducial marks (local,global)• Include fiducial marks in Stencil for easy
registration visually• Undersize stencil openings slightly
Zoid Labs IEW 2019 117
More DFP Tips (3/3)
Footprints, Layout, Stencil
• Use rounded pads in footprints- For small passives- Less likely to ’tombstone’- Better for IC’s too
• Careful with big thermal pads (belly pads)!• Prefer non-BGA packages if possible
- More leeway with solder reflow profile• Include fiducial marks (local,global)• Include fiducial marks in Stencil for easy
registration visually• Undersize stencil openings slightly
Zoid Labs IEW 2019 118
Equipment and Process Support
What Equipment?Process supportetc
Zoid Labs IEW 2019 119
Equipment• PCB mill? Evaluate use vs. $
• Stencilling machines??
• Inspection capability X• Auto Pick and Place: X
• Ensures correct parts, polarity,orientation. Faster than manual process;else paste may dry up
• Easier to repeat the run (than manual)• Should do 0402, cut tape, fine pitch ICs
• PCB Oven: X• Verify temp. profiles for Pb & Pb-free• Verify heat distribution
Zoid Labs IEW 2019 120
Equipment• PCB mill? Evaluate use vs. $
• Stencilling machines??
• Inspection capability X• Auto Pick and Place: X
• Ensures correct parts, polarity,orientation. Faster than manual process;else paste may dry up
• Easier to repeat the run (than manual)• Should do 0402, cut tape, fine pitch ICs
• PCB Oven: X• Verify temp. profiles for Pb & Pb-free• Verify heat distribution
Zoid Labs IEW 2019 121
Equipment• PCB mill? Evaluate use vs. $
• Stencilling machines??
• Inspection capability X• Auto Pick and Place: X
• Ensures correct parts, polarity,orientation. Faster than manual process;else paste may dry up
• Easier to repeat the run (than manual)• Should do 0402, cut tape, fine pitch ICs
• PCB Oven: X• Verify temp. profiles for Pb & Pb-free• Verify heat distribution
Zoid Labs IEW 2019 122
Equipment• PCB mill? Evaluate use vs. $
• Stencilling machines??
• Inspection capability X• Auto Pick and Place: X
• Ensures correct parts, polarity,orientation. Faster than manual process;else paste may dry up
• Easier to repeat the run (than manual)• Should do 0402, cut tape, fine pitch ICs
• PCB Oven: X• Verify temp. profiles for Pb & Pb-free• Verify heat distribution
Zoid Labs IEW 2019 123
Equipment• PCB mill? Evaluate use vs. $
• Stencilling machines??
• Inspection capability X• Auto Pick and Place: X
• Ensures correct parts, polarity,orientation. Faster than manual process;else paste may dry up
• Easier to repeat the run (than manual)• Should do 0402, cut tape, fine pitch ICs
• PCB Oven: X• Verify temp. profiles for Pb & Pb-free• Verify heat distribution
Zoid Labs IEW 2019 124
Equipment• PCB mill? Evaluate use vs. $
• Stencilling machines??
• Inspection capability X• Auto Pick and Place: X
• Ensures correct parts, polarity,orientation. Faster than manual process;else paste may dry up
• Easier to repeat the run (than manual)• Should do 0402, cut tape, fine pitch ICs
• PCB Oven: X• Verify temp. profiles for Pb & Pb-free• Verify heat distribution
Zoid Labs IEW 2019 125
Equipment• PCB mill? Evaluate use vs. $
• Stencilling machines??
• Inspection capability X• Auto Pick and Place: X
• Ensures correct parts, polarity,orientation. Faster than manual process;else paste may dry up
• Easier to repeat the run (than manual)• Should do 0402, cut tape, fine pitch ICs
• PCB Oven: X• Verify temp. profiles for Pb & Pb-free• Verify heat distribution
Zoid Labs IEW 2019 126
Equipment• PCB mill? Evaluate use vs. $
• Stencilling machines??
• Inspection capability X• Auto Pick and Place: X
• Ensures correct parts, polarity,orientation. Faster than manual process;else paste may dry up
• Easier to repeat the run (than manual)• Should do 0402, cut tape, fine pitch ICs
• PCB Oven: X• Verify temp. profiles for Pb & Pb-free• Verify heat distribution
Zoid Labs IEW 2019 127
Equipment• PCB mill? Evaluate use vs. $
• Stencilling machines??
• Inspection capability X• Auto Pick and Place: X
• Ensures correct parts, polarity,orientation. Faster than manual process;else paste may dry up
• Easier to repeat the run (than manual)• Should do 0402, cut tape, fine pitch ICs
• PCB Oven: X• Verify temp. profiles for Pb & Pb-free• Verify heat distribution
Zoid Labs IEW 2019 128
Equipment• PCB mill? Evaluate use vs. $
• Stencilling machines??
• Inspection capability X• Auto Pick and Place: X
• Ensures correct parts, polarity,orientation. Faster than manual process;else paste may dry up
• Easier to repeat the run (than manual)• Should do 0402, cut tape, fine pitch ICs
• PCB Oven: X• Verify temp. profiles for Pb & Pb-free• Verify heat distribution
Zoid Labs IEW 2019 129
Process Support
• Managing components: e.g. cut tapes
• Managing part numbers• HPN – House Part No, MPN – Mfr Part No,
DPN – Distributor Part No, DPN2 –Alternate
Distributer Part No. . . . etc and equivalences
between these part numbers.
Zoid Labs IEW 2019 130
Conclusions
1 SMT Prototyping can be challenging
2 To cut cycle-time/cost, have in-house
assembling capability
3 Use DFP (Design For Prototyping)
guidelines
4 Appropriate Equipment and Process
Thank You! [email protected]
Zoid Labs IEW 2019 131
Conclusions
1 SMT Prototyping can be challenging
2 To cut cycle-time/cost, have in-house
assembling capability
3 Use DFP (Design For Prototyping)
guidelines
4 Appropriate Equipment and Process
Thank You! [email protected]
Zoid Labs IEW 2019 132
Conclusions
1 SMT Prototyping can be challenging
2 To cut cycle-time/cost, have in-house
assembling capability
3 Use DFP (Design For Prototyping)
guidelines
4 Appropriate Equipment and Process
Thank You! [email protected]
Zoid Labs IEW 2019 133
Conclusions
1 SMT Prototyping can be challenging
2 To cut cycle-time/cost, have in-house
assembling capability
3 Use DFP (Design For Prototyping)
guidelines
4 Appropriate Equipment and Process
Thank You! [email protected]
Zoid Labs IEW 2019 134
Conclusions
1 SMT Prototyping can be challenging
2 To cut cycle-time/cost, have in-house
assembling capability
3 Use DFP (Design For Prototyping)
guidelines
4 Appropriate Equipment and Process
Thank You! [email protected]
Zoid Labs IEW 2019 135
Conclusions
1 SMT Prototyping can be challenging
2 To cut cycle-time/cost, have in-house
assembling capability
3 Use DFP (Design For Prototyping)
guidelines
4 Appropriate Equipment and Process
Thank You! [email protected]
Zoid Labs IEW 2019 136