Abstract—The Booth Multiplier puts to use the Booth’s

Multiplication algorithm which takes two binary numbers and

multiplies them in 2’s complement.

Index Terms— VLSI, VHDL, Layout, Multipliers, Booth’s

Multiplication Algorithm, Radix-4.

I. INTRODUCTION

HIS PROJECT aims to implement a circuit that performs

N-bit Radix-4 multiplication using Booth’s Multiplication

algorithm along with minimizing the power requirements.

Multipliers are key component in a system. They are generally

the slowest component in a system. Multipliers generally tend

to take up quite a lot of space in the layout. The project aims at

optimizing the speed as well as the area of the multiplier.

Optimizing the speed would speed up the entire system as it is

supposed to be one of the critical components. The project

aims at making a tradeoff between high speed, lower power,

and lesser area, and thereby optimizing the performance.

II. ALGORITHM

Radix-4 multiplication obtains an improvement in the

multiplication algorithm due to the less number of partial

products entering the Wallace tree to be reduced. This can be

achieved by the application of the multiplier recoding,

changing from a 2‟s complement format to a signed-digit

representation from the set {0, ±1, ±2}. Now let us assume

that we are giving a triplet of multiplier one at a time in the

form of Yi-1, Yi, Yi+1 and gets the encoded output in the

form of Neg, X1_b, X2_b, Z. In which „X2_b‟ means that the

multiplicand is not to be doubled, „X1_b‟ means multiplicand

is to be doubled and „Neg‟ means neither to be doubled nor to

be inverted. Fig. 1 shows the block diagram of the radix-4

encoder.

Fig.1 Radix-4 Encoder Block Diagram

In the partial product generator block, multiplier bits encoded

from the encoder and the multiplicand bits get multiplied and

the partial products are generated. Fig. 2 shows the block

diagram of 1-bit partial product generator block where the

input X1_b, X2_b, Neg, Z are the encoded multiplier bits from

the encoder and Xj and Xj-1 are the multiplicand bits which are

to be multiplied by the multiplier bits coming from the

encoder.

Fig.2 1-bit Partial Product Generator Block

Fig. 3 shows 9-BIT PPG block made from nine 1-bit PPG

blocks and nine half adders. Half adders are to get 2‟s

complemented form.

Fig.3 9-BIT PPG Block

Low Power N-bit Radix-4 Booth Multiplier

Arunkumar Prabhashankar, Farhaan Fowze, Rudra Prasad Baksi, Sidhartha Behura and Aishwarya C

Warrier

Department of Electrical and Computer Engineering, University of Florida, Gainesville 32611

T

III. PROJECT

The project aims at implementing the logic of the algorithm

through VHDL codes in Xilinx ISE Design suite. The layout

for the project will be implemented on Cadence Virtuoso.

REFERENCES

[1] Rajput, S. ; Dept. of Electron. & Commun., Maharaja Surajmal Inst. of Technol. (GGSIPU), New Delhi, India ; Shukla, R. ; Praveen, P. ;

Anand, A. “Implementation of High Speed and Low Power Hybrid

Adder Based Novel Radix 4 Booth Multiplier” in Communication Systems and Network Technologies (CSNT), 2013 International

Conference 6-8 April 2013.

[2] Saleh, H.H. ; ECE Dept., Khalifa Univ. of Sci., Abu Dhabi, United Arab

Emirates ; Mohammad, B.S. ; Swartzlander, E.E.. “The optimum Booth

radix for low power integer multipliers” in Design and Test Symposium (IDT), 2013 8th International 16-18 Dec. 2013.

[3] Jiaoyan Chen ; Dept. of Electr. & Electron. Eng., Univ. Coll. Cork, Cork, Ireland ; Popovici, E. ; Vasudevan, D. ; Schellekens, M. “Ultra

Low Power Booth Multiplier Using Asynchronous Logic” in

Asynchronous Circuits and Systems (ASYNC), 2012 18th IEEE International Symposium 7-9 May 2012.