VLSI Project Group2 v1

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<ul><li><p>8/6/2019 VLSI Project Group2 v1</p><p> 1/20</p><p>Group 2 team members :</p><p> (9760117)(9770117)</p><p>VLSI Final Project</p><p>Research of Comparison of 4-input NAND gates</p></li><li><p>8/6/2019 VLSI Project Group2 v1</p><p> 2/20</p><p>1</p><p> TOPIC 4 </p><p>COMPARE 4-INPUT NAND GATESSHOWN BELOW</p><p>Style # Trans Ease Ratioed? Delay Power</p><p>Comp</p><p>Static</p><p>8 1 no 3 1</p><p>CPL* 12 + 2 2 no 4 3</p><p>domino 6 + 2 4 no 2 2 + clk</p><p>DCVSL* 10 3 yes 1 4</p><p>1.Coms Static </p><p>NAND</p><p> composer</p></li><li><p>8/6/2019 VLSI Project Group2 v1</p><p> 3/20</p><p>2</p><p> LAKER</p><p> 5TXNR</p></li><li><p>8/6/2019 VLSI Project Group2 v1</p><p> 4/20</p><p>3</p><p>DRC, LVS &amp; PEX Verification</p><p>5TXY)*1&amp;&gt;9.2*</p><p> 8= ;)) )JQF^YNRJ </p><p>QNX </p><p>YWFS &amp;c&amp; TZY </p><p>)JQF^ 9UIW9UIK </p><p>99;( 5TXYQF^TZY</p><p>)JQF^9NRJSXJH</p><p>9UIW9UIK</p><p>YIJQF^"*</p><p>YIJQF^"*</p><p>YIJQF^"*</p><p>YIJQF^"*</p><p>NSUZYF[JWFLJIJQF^ YIJQF^"*</p></li><li><p>8/6/2019 VLSI Project Group2 v1</p><p> 5/20</p><p>4</p><p>248</p><p>NAND</p><p>Simulation</p><p>corner</p><p>TT</p><p>Wp(um) 3u</p><p>mp 1</p><p>Wn(um) 0.5</p><p>mn 1</p><p>Static Logic Styles</p><p>Conventional CMOS, in combination with pass-gate logic, allows very efficient</p><p>implementation of simple gates (e.g. NAND/NOR, AOI/OAI) having only few transistors</p><p>and nodes, and a small delay due to the single inversion level.</p><p>The disadvantages lie in the large PMOS transistors resulting in high input capacitances</p><p>and area requirements, and the weak output driving capability caused by series</p><p>transistors.</p></li><li><p>8/6/2019 VLSI Project Group2 v1</p><p> 6/20</p><p>5</p><p>2.(51 NAND</p><p> composer</p><p>Laker</p></li><li><p>8/6/2019 VLSI Project Group2 v1</p><p> 7/20</p><p>6</p><p>DRC, LVS &amp; PEX Verification</p></li><li><p>8/6/2019 VLSI Project Group2 v1</p><p> 8/20</p><p>7</p><p>5WJXNR IJQF^</p><p>5TXYXNR IJQF^</p></li><li><p>8/6/2019 VLSI Project Group2 v1</p><p> 9/20</p><p>8</p><p>99;( 5WJQF^TZY 5TXYQF^TZY</p><p>)JQF^9NRJSXJH9UIW9UIK</p><p> YIJQF^"*YIJQF^"*</p><p>YIJQF^"*</p><p>YIJQF^"*</p><p>NSUZYF[JWFLJIJQF^ YIJQF^"*</p><p>248</p><p>NAND Inverter(for output) Inverter(for input)</p><p>Simulatio</p><p>n corner</p><p>TT Simulatio</p><p>n corner</p><p>TT Simulation</p><p>corner</p><p>TT</p><p>Wp(um) - Wp(um) 1.5u Wp(um) 3u</p><p>mp 1 mp 1 mp 1</p></li><li><p>8/6/2019 VLSI Project Group2 v1</p><p> 10/20</p><p>9</p><p>Wn(um) 0.</p><p>7</p><p>Wn(um) 1u Wn(um) 2.5u</p><p>mn 1 mn 1 mn 1</p><p>Complementary pass-transistor logic(CPL) benefits from the small input capacitances</p><p>(NMOS network only), the fast differential stage, and the good output driving capability</p><p>(output inverter), making the implementation of complex gates (e.g. full-adders) very</p><p>efficient. On the other hand, the large number of nodes and transistors and the two</p><p>inversion levels result in relatively inefficient CPL implementations of simple gates.</p><p>Usually, pull-up PMOS transistors are necessary for swing restoration.</p><p>Larger short-circuit currents and higher wiring overhead (dual-rail signals) compared to</p><p>CMOS also increase power consumption.</p><p>Swing restored pass-transistor logic (SRPL) and double pass-transistor logic (DPL) are</p><p>closely related to CPL and are also considered in the subsequent comparisons.</p><p>3.)42.34 NAND</p><p> composer</p></li><li><p>8/6/2019 VLSI Project Group2 v1</p><p> 11/20</p><p>10</p><p>LAKER</p></li><li><p>8/6/2019 VLSI Project Group2 v1</p><p> 12/20</p><p>11</p><p>DRC, LVS &amp; PEX Verification</p></li><li><p>8/6/2019 VLSI Project Group2 v1</p><p> 13/20</p><p>12</p><p>5WJXNR 5TXNR</p><p>99;( 5TXYQF^TZY</p><p>)JQF^9NRJSXJH YWNXJ"*</p></li><li><p>8/6/2019 VLSI Project Group2 v1</p><p> 14/20</p><p>13</p><p>9UIW9UIK YFWL"*</p><p>YWNL"*</p><p>YKFQQ"*</p><p>YFWL"*</p><p>YWNL"*</p><p>NSUZYF[JWFLJIJQF^ YIJQF^"*</p><p>248</p><p>NAND</p><p>Simulation</p><p>corner</p><p>TT</p><p>Wp(um) 3u</p><p>mp 1</p><p>Wn(um) 0.4/ 0.8</p><p>mn 1</p><p>)TRNST </p><p>The circuit family used in our designs maintains a direct relationship to the performance,</p><p>power, noise tolerance, and time to market of a design. The robustness and ease of</p><p>mapping combinational functions to static logic are significant advantages that keep this</p></li><li><p>8/6/2019 VLSI Project Group2 v1</p><p> 15/20</p><p>14</p><p>logic family at the forefront of our design world. However, other logic families hold</p><p>distinct advantages in terms of power and performance over traditional static logic</p><p>design.</p><p>Circuit Comparison</p><p>a domino implementation of a six-gate two-input NAND pipeline is 40% faster with 21%</p><p>less peak switching energy than a static implementation driving an identical load.</p><p>4.)(;81 NAND</p><p> composer</p><p>5TXYXNR</p></li><li><p>8/6/2019 VLSI Project Group2 v1</p><p> 16/20</p><p>15</p><p>LAKER</p></li><li><p>8/6/2019 VLSI Project Group2 v1</p><p> 17/20</p><p>16</p><p>DRC, LVS &amp; PEX Verification</p></li><li><p>8/6/2019 VLSI Project Group2 v1</p><p> 18/20</p><p>17</p><p> 8= ;)) )JQF^YNRJ QNX </p><p>YWFS &amp;c&amp; TZY )JQF 9UIW9UIK </p><p>99;( 5TXYQF^TZY</p><p>)JQF^9NRJSXJH</p><p>9UIW9UIK</p><p>YIJQF^"*</p><p>YIJQF^"*</p><p>YIJQF^"*</p><p>YIJQF^"*</p><p>NSUZYF[JWFLJIJQF^ YIJQF^"*</p><p>248</p><p>NAND MM1 MM2</p><p>Simulatio</p><p>n corner</p><p>TT Simulatio</p><p>n corner</p><p>TT Simulation</p><p>corner</p><p>TT</p><p>Wp(um) 3u Wp(um) - Wp(um) -</p><p>mp 1 mp 1 mp 1</p><p>Wn(um) 0.</p><p>7</p><p>Wn(um) 0.8u Wn(um) 1.7u</p><p>mn 1 mn 1 mn 1</p><p>(43(1:8.43 IJQF^_ </p><p>The advantages of high functionality with few pass-transistors and of small input</p><p>capacitances in theCPL style are partially undone by the need for swing restoration</p></li><li><p>8/6/2019 VLSI Project Group2 v1</p><p> 19/20</p><p>18</p><p>circuitry, dual-rail encoding, and the resulting wiring overhead, which becomes a crucial</p><p>factor in deep submicron.</p><p>The presented investigation results show that for most simple and complex logic gates</p><p>and under realistic circuit conditions conventional CMOS combined with pass-gate</p><p>logic performs much better than CPL and related logic styles if low power is concerned.</p></li><li><p>8/6/2019 VLSI Project Group2 v1</p><p> 20/20</p><p>19</p></li></ul>