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Group 2 team members :

(9760117)(9770117)

VLSI Final Project

Research of Comparison of 4-input NAND gates

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TOPIC 4

COMPARE 4-INPUT NAND GATESSHOWN BELOW

Style # Trans Ease Ratioed? Delay Power

Comp

Static

8 1 no 3 1

CPL* 12 + 2 2 no 4 3

domino 6 + 2 4 no 2 2 + clk

DCVSL* 10 3 yes 1 4

1.Coms Static

NAND

composer

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LAKER

5TXNR

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DRC, LVS & PEX Verification

5TXY)*1&>9.2*

8= ;)) )JQF^YNRJ

QNX

YWFS &c& TZY

)JQF^ 9UIW9UIK

99;( 5TXYQF^TZY

)JQF^9NRJSXJH

9UIW9UIK

YIJQF^"*

YIJQF^"*

YIJQF^"*

YIJQF^"*

NSUZYF[JWFLJIJQF^ YIJQF^"*

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4

248

NAND

Simulation

corner

TT

Wp(um) 3u

mp 1

Wn(um) 0.5

mn 1

Static Logic Styles

Conventional CMOS, in combination with pass-gate logic, allows very efficient

implementation of simple gates (e.g. NAND/NOR, AOI/OAI) having only few transistors

and nodes, and a small delay due to the single inversion level.

The disadvantages lie in the large PMOS transistors resulting in high input capacitances

and area requirements, and the weak output driving capability caused by series

transistors.

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2.(51 NAND

composer

Laker

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DRC, LVS & PEX Verification

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5WJXNR IJQF^

5TXYXNR IJQF^

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99;( 5WJQF^TZY 5TXYQF^TZY

)JQF^9NRJSXJH9UIW9UIK

YIJQF^"*YIJQF^"*

YIJQF^"*

YIJQF^"*

NSUZYF[JWFLJIJQF^ YIJQF^"*

248

NAND Inverter(for output) Inverter(for input)

Simulatio

n corner

TT Simulatio

n corner

TT Simulation

corner

TT

Wp(um) - Wp(um) 1.5u Wp(um) 3u

mp 1 mp 1 mp 1

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Wn(um) 0.

7

Wn(um) 1u Wn(um) 2.5u

mn 1 mn 1 mn 1

Complementary pass-transistor logic(CPL) benefits from the small input capacitances

(NMOS network only), the fast differential stage, and the good output driving capability

(output inverter), making the implementation of complex gates (e.g. full-adders) very

efficient. On the other hand, the large number of nodes and transistors and the two

inversion levels result in relatively inefficient CPL implementations of simple gates.

Usually, pull-up PMOS transistors are necessary for swing restoration.

Larger short-circuit currents and higher wiring overhead (dual-rail signals) compared to

CMOS also increase power consumption.

Swing restored pass-transistor logic (SRPL) and double pass-transistor logic (DPL) are

closely related to CPL and are also considered in the subsequent comparisons.

3.)42.34 NAND

composer

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LAKER

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DRC, LVS & PEX Verification

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5WJXNR 5TXNR

99;( 5TXYQF^TZY

)JQF^9NRJSXJH YWNXJ"*

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9UIW9UIK YFWL"*

YWNL"*

YKFQQ"*

YFWL"*

YWNL"*

NSUZYF[JWFLJIJQF^ YIJQF^"*

248

NAND

Simulation

corner

TT

Wp(um) 3u

mp 1

Wn(um) 0.4/ 0.8

mn 1

)TRNST

The circuit family used in our designs maintains a direct relationship to the performance,

power, noise tolerance, and time to market of a design. The robustness and ease of

mapping combinational functions to static logic are significant advantages that keep this

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logic family at the forefront of our design world. However, other logic families hold

distinct advantages in terms of power and performance over traditional static logic

design.

Circuit Comparison

a domino implementation of a six-gate two-input NAND pipeline is 40% faster with 21%

less peak switching energy than a static implementation driving an identical load.

4.)(;81 NAND

composer

5TXYXNR

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LAKER

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DRC, LVS & PEX Verification

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8= ;)) )JQF^YNRJ QNX

YWFS &c& TZY )JQF 9UIW9UIK

99;( 5TXYQF^TZY

)JQF^9NRJSXJH

9UIW9UIK

YIJQF^"*

YIJQF^"*

YIJQF^"*

YIJQF^"*

NSUZYF[JWFLJIJQF^ YIJQF^"*

248

NAND MM1 MM2

Simulatio

n corner

TT Simulatio

n corner

TT Simulation

corner

TT

Wp(um) 3u Wp(um) - Wp(um) -

mp 1 mp 1 mp 1

Wn(um) 0.

7

Wn(um) 0.8u Wn(um) 1.7u

mn 1 mn 1 mn 1

(43(1:8.43 IJQF^_

The advantages of high functionality with few pass-transistors and of small input

capacitances in theCPL style are partially undone by the need for swing restoration

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circuitry, dual-rail encoding, and the resulting wiring overhead, which becomes a crucial

factor in deep submicron.

The presented investigation results show that for most simple and complex logic gates

and under realistic circuit conditions conventional CMOS combined with pass-gate

logic performs much better than CPL and related logic styles if low power is concerned.

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