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Project 1. Implementaon and simulaon of 64 bit ALU.--------TOP LEVEL--------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;

enty ALU_64 isgeneric(n:integer:=8);Port ( A : in STD_LOGIC_VECTOR (n-1 downto 0);B : in STD_LOGIC_VECTOR (n-1 downto 0);clk:in std_logic;S:in std_logic_vector(3 downto 0);---carry in is bit S(0);F : out STD_LOGIC_VECTOR (n-1 downto 0);cout : out STD_LOGIC);end ALU_64;

architecture Behavioral of ALU_64 iscomponent mux2generic(n:integer:=8);Port ( F1 : in STD_LOGIC_VECTOR (n-1 downto 0);F2 : in STD_LOGIC_VECTOR (n-1 downto 0);s3 : in STD_LOGIC;clk:in std_logic;Y : out STD_LOGIC_VECTOR (n-1 downto 0));end component;

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component logical_unitgeneric(n:integer:=8);Port ( A : in STD_LOGIC_VECTOR (n-1 downto 0);B : in STD_LOGIC_VECTOR (n-1 downto 0);s : in STD_LOGIC_VECTOR (2 downto 0);clk : in STD_LOGIC;F : out STD_LOGIC_VECTOR (n-1 downto 0));end component;component arith_unitgeneric(n:integer:=8);Port ( A : in STD_LOGIC_VECTOR (n-1 downto 0):=(others=>'0');B : in STD_LOGIC_VECTOR (n-1 downto 0):=(others=>'0');clk:in std_logic;s: in STD_LOGIC_vector(2 downto 0);F : out STD_LOGIC_VECTOR (n-1 downto 0):=(others=>'0');cout :out STD_LOGIC);end component;signal f1:std_logic_vector(n-1 downto 0);signal f2:std_logic_vector(n-1 downto 0);signal s1:std_logic_vector(1 downto 0);begin

s1

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case s iswhen "000" => F F F F F F F F NULL;end case;end process;end Behavioral;

Arithmec unit-------------------------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;

enty Arith_unit isgeneric(n:integer:=8);Port ( A : in STD_LOGIC_VECTOR (n-1 downto 0):=(others=>'0');

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B : in STD_LOGIC_VECTOR (n-1 downto 0):=(others=>'0');clk:in std_logic;s: in STD_LOGIC_vector(2 downto 0);F : out STD_LOGIC_VECTOR (n-1 downto 0):=(others=>'0');cout : out STD_LOGIC);end Arith_unit;

architecture Behavioral of Arith_unit issignal a1:std_logic_vector(n downto 0);signal b1:std_logic_vector(n downto 0);signal f1:std_logic_vector(n downto 0);

begina1

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when "110" => f1 f1 NULL;end case;F

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Port ( F1 : in STD_LOGIC_VECTOR (n-1 downto 0);F2 : in STD_LOGIC_VECTOR (n-1 downto 0);s3,clk : in STD_LOGIC;Y : out STD_LOGIC_VECTOR (n-1 downto 0));

end mux2;

architecture Behavioral of mux2 is

beginprocess(clk)begincase s3 iswhen '0'=> Y Y NULL;end case;end process;end Behavioral;****************************************************************************