programming the 68hc11 mpu – chapter 7courses.muscedere.com/elec32701/elec3270-ch7.pdf ·...

1© 2003-2019 Roberto Muscedere, Images and text portions © 2003 Prentice Hall

Programming the 68HC11 MPU Programming the 68HC11 MPU –– Chapter 7Chapter 7• Review Condition Code

registers INDEX REGISTER X15 0 IX

INDEX REGISTER Y15 0 IY

STACK POINTER15 0 SP

PROGRAM COUNTER15 0 PC

7 0

CVZNIHXS CCR

CARRY

OVERFLOW

ZERO

NEGATIVE

I INTERRUPT MASK

HALF-CARRY (FROM BIT 3)

X INTERRUPT MASK

STOP DISABLE

CONDITION CODE REGISTER

DOUBLE ACCUMULATOR D15 0 D

ACCUMULATOR A ACCUMULATOR B7 00 A:B


Condition Code Register (CCR)Condition Code Register (CCR)• C (Carry flag)

• The MSB results of an addition or subtraction• Can be set/cleared with SEC/CLC

• V (Overflow flag)• Indicates an overflow occurred during addition and subtraction with signed

numbers• Can be set/cleared with SEV/CLV

• Z (Zero flag)• Is set to 1 whenever any arithmetic, data transfer, or manipulation results in a

zero• N (Negative flag)

• Indicates the sign of any arithmetic, data transfer, or manipulation operation• N is the MSB


Condition Code Register (CCR)Condition Code Register (CCR)• I (Interrupt Mask)

• Indicates whether the 68HC11 responds to external interrupts from /IRQ• Can be set/cleared with SEI/CLI

• H (Half Carry)• Changed only by addition instructions• Carry between bits 3 and 4• Used to correct BCD addition

• X (X Interrupt Mask)• Indicates whether the 68HC11 responds to external interrupts from /XIRQ• Initially set to 1, but can only be set to zero once• Must use the TAP (Transfer ACCA to CCR)

• S (Stop Disable)• Prevents the STOP operation from occurring• Can only be set or cleared using TAP


Addressing ModesAddressing Modes• Extended Addressing

• Uses a 2-byte operand address• ADH is the high-order address byte, while

ADL is the low-order address byte• Requires a minimum of 3 bytes for a

complete instruction• Eg. LDAA $2E17

• Load Accumulator A with the contents at memory address $2E17

Byte 1 Op code

Byte 2 ADH

Byte 3 ADL


Addressing ModesAddressing Modes• Direct Addressing

• Uses a 1-byte operand address• ADL is the low-order address byte, ADH is

set to 0• Requires a minimum of 2 bytes for a

complete instruction• Eg. LDAA $50

• Load Accumulator A with the contents at memory address $0050

Byte 1 Op code

Byte 2 ADL


Addressing ModesAddressing Modes• Immediate Addressing

• Loads register with a value from the program code, not the data memory

• Eg. LDAA #$24• Load Accumulator A with $24• 2 byte instruction

• Eg. LDD #$1234• Load Accumulator D with $1234, ACCA with $12, and

ACCB with $34• 3 byte instruction

• Eg. LDY #$1234• Load Y index• 4 byte instruction; requires pre-byte

Byte 1 Op code

Byte 2 Operand

… …


Addressing ModesAddressing Modes• Inherent Addressing

• Instruction does not need additional information

• Requires a minimum of 1 byte for a complete instruction

• Eg. CLRA• Set Accumulator A to 0

Byte 1 Op code


Addressing ModesAddressing Modes• Indexed Addressing

• Uses a 1-byte operand offset address• Offset (unsigned) is added to

corresponding index register• Requires a minimum of 2 bytes for a

complete instruction• Eg. ADDA $32,X

• Add the contents at memory address $32+X with Accumulator A

Byte 1 Op code

Byte 2 Offset


Addressing ModesAddressing Modes• Relative Addressing

• Uses a 1-byte operand offset for the PC• Offset (signed) is added to the program counter

generally if a branch condition is met• Requires 2 bytes for a complete instruction• Eg. $C000 BRA $C002

• “BRanch Always to $C002”• Would be encoded as “$20 $00”• When the instruction is executed the PC is $C002• $00 is added to PC to get $C002, therefore it would

branch to there

Byte 1 Op code

Byte 2 Offset


68HC11 Instructions:68HC11 Instructions:Loads, Stores, and TransfersLoads, Stores, and Transfers

• CLR, CLRx• Clear memory, ACCx

• LDAx• Load ACCx

• LDD• Load ACCD

• PULx• Pull ACCx from stack

• PSHx• Push ACCx on stack

• STAx• Store ACCx

• “x” is either A or B

• STD• Store ACCD

• TAB• Transfer ACCA to ACCB

• TBA• Transfer ACCB to ACCA

• TAP• Transfer ACCA to CCR

• TPA• Transfer CCR to ACCA

• XGDr• Exchange D with Ir

• “r” is either X or Y


Sample CodeSample Code* 68HC11 ASM code; variables are previously configured

clr myvaru81clrbstab myvaru82ldaa #73 ; 8 bit valuestaa myvaru81

ldd #12345 ; 16 bit valuestd myvaru161xgdx ; X is now 12345pshx ; save it on stackldx #54321stx myvaru162xgdx ; D is now 54321pulx ; X is now 12345 againstaa myvaru82 ; A is upper 8 bits of D

/* C code */

typedef unsigned char u8;typedef signed char s8;typedef unsigned short int u16;typedef signed short int s16;

...

u8 myvaru81 = 0, myvaru82 = 0;u16 myvaru161 = 12345,

myvaru162 = 54321;

myvaru81 = 73;myvaru82 = myvaru162 >> 8;

...


68HC11 Instructions: Arithmetic68HC11 Instructions: Arithmetic• ABA

• Add ACCB to ACCA• ABr

• Add ACCB to Ir• ADCx

• Add operand and C flag to ACCx• ADDx

• Add operand to ACCx• ADDD

• Add memory to ACCD• DAA

• Decimal Adjust ACCA (for BCD addition)• Add either $00, $06, $60, or $66 to

ACCA• Set carry appropriately

• SBA• Subtract ACCB from ACCA

• SBCx• Subtract operand and C flag from ACCx

• SUBx• Subtract operand from ACCx

• SUBD• Subtract memory from ACCD

• NEG• Negate memory byte• Subtract from 0

• NEGx• Negate ACCx• Subtract from 0



; addd doesn’t use carry, only sets it; use adc to chain carry for extra; 8-bit additions from LSB to MSB

ldd myvaru321+2addd myvaru322+2 ; does first 16 bitsstd myvaru321+2ldaa myvaru321+1adca myvaru322+1 ; does next 8 bitsstaa myvaru321+1ldaa myvaru321adca myvaru322 ; does next 8 bitsstaa myvaru321

; "sub" works the same way

/* C code */

...typedef unsigned int u32;typedef signed int s32;...u32 myvaru321, myvaru322;...

myvaru321 = myvaru321 + myvaru322;

/* PCs chain the instructions just as the 68HC11 when processing addition/subtraction with data larger than a single "word" */



; only ABA, ADCx, and ADDx set H flag

ldaa myvaru161+1adda myvaru162+1daastaa myvaru161+1ldda myvaru161adca myvaru162daastaa myvaru161

; daa is done after each "add" to fix; result so it is in proper BCD

/* C code */

/* C doesn’t support Binary Coded Decimal natively. You need to use "printf" (very large function) or "itoa" (integer to ASCII) to change the value into an array of digits.Or you can just create your own function. It is likely it will take some time to operate. */


68HC11 Instructions: Arithmetic68HC11 Instructions: Arithmetic• DEC

• Decrement memory byte• DECx

• Decrement ACCx• INC

• Increment memory byte• INCx

• Increment ACCx• CBA

• Compare ACCA to ACCB• CMPx

• Compare ACCx to memory• CPD

• Compare ACCD to memory

• TST• Test for Zero or Negative on memory

byte• TSTx

• Test for Zero or Negative on ACCx• MUL

• Unsigned multiplication of ACCA and ACCB; product stored in ACCD

• IDIV• Integer divide D/IX, store quotient in IX,

and remainder in D; D>IX• FDIV

• Fractional divide D/IX, store quotient in IX, and remainder in D; D<IX



ldaa myvaru81ldab myvaru82mulstd myvaru161

tst myvaru81 ; doesn’t change A or Bbeq skipinc myvaru81dec myvaru82

skip

...

/* C code */

...myvaru161 = myvaru81 * myvaru82;...if (myvaru81){myvaru81++;myvaru82--;}...


68HC11 Instructions: Branches68HC11 Instructions: Branches• BCC (Carry Cleared) [C=0]• BCS (Carry Set) [C=1]• BNE (Not Equal) [Z=0]• BEQ (Equal) [Z=1]• BVC (Overflow Cleared) [V=0]• BVS (Overflow Set) [V=1]• BPL (Plus) [N=0]• BMI (Minus) [N=1]• BRA (Always) [true]

• Short jump (2 bytes)

• +/- is signed comparison• + is unsigned comparison

• BGE (Greater Than Equal) [+/- >=]• BGT (Greater Than) [+/- >]• BLE (Less Than Equal) [+/- <=]• BLT (Less Than) [+/- <]• BHS (Higher or Same) [+ >=]

• Same as BCC• BHI (Higher) [+ >]• BLS (Lower or Same) [+ <=]• BLO (Lower) [+ <]

• Same as BCS• BRN (Never) [false]

• 3 cycle NOP



ldaa myvaru81cmpa myvaru82bls skip1 ; + <=inc myvaru82skip1ldaa myvars81cmpa myvars82 ble skip2 ; +/i <=inc myvaru82skip2...

/* C code */

...u8 myvaru81, myvaru82;s8 myvars81, myvars82;...

if (myvaru81 > myvaru82) myvaru82++;if (myvars81 > myvars82) myvaru82++;


68HC11 Instructions: Logic68HC11 Instructions: Logic• ANDx

• AND ACCx with memory• EORx

• Exclusive OR ACCx with memory

• ORAx• OR ACCx with memory

• BITx• AND ACCx with memory

but only change CCR• COM

• 1’s complement of memory byte

• COMx• 1’s complement of ACCx


68HC11 Instructions:68HC11 Instructions:Data Testing and Bit ManipulationData Testing and Bit Manipulation

• BCLR• Clear bit(s) in memory• Eg. BCLR $85 $12

• Clear bits 1 and 4 at address $85• BSET

• Set bit(s) in memory• Eg. BSET $28,X $88

• Set bits 3 and 7 at address $28+X• Both 3 byte instructions

• Additional byte if IND,Y is used

• BRCLR• Branch if bit(s) are cleared• Eg. BRCLR $85 $12 label1

• Branch to “label1” if address $85 has both bits 1 and 4 cleared

• BRSET• Branch if bit(s) are set• Eg. BRSET $28,X $88 label2

• Branch to “label2” if address $28+X has both bits 3 and 7 set

• Both 4 byte instructions• Additional byte if IND,Y is used


68HC11 Instructions: Shift and Rotates68HC11 Instructions: Shift and Rotates• LSL* (Logic Shift Left *) - Same as ASL* - no instruction• LSR (Logic Shift Right Memory)• LSRx (Logic Shift Right ACCx)• LSRD (Logic Shift Right ACCD)

• ASL (Arithmetic Shift Left Memory)• ASLx (Arithmetic Shift Left ACCx)• ASLD (Arithmetic Shift Left ACCD)• ASR (Arithmetic Shift Right Memory)• ASRx (Arithmetic Shift Right ACCx)

• ROL (Rotate Left Memory)• ROLx (Rotate Left ACCx)• ROR (Rotate Right Memory)• RORx (Rotate Right ACCx)



ldaa myvaru82lslastaa myvaru81lsrb myvaru82 ; no variable shiftslsrb myvaru82 ; do it twiceldaa myvars82asrastaa myvars81 ldd myvaru162lsrdstd myvaru162ldd myvaru161 ; no 16 bit LSLlslb ; shift LSB first, no Crola ; shift MSB second, with Cstd myvaru161

/* C code */

...u8 myvaru81, myvaru82;s8 myvars81, myvars82;u16 myvaru161, myvaru162;...

myvaru81 = myvaru82 << 1;myvaru82 = myvaru82 >> 2;myvars81 = myvars82 >> 1;

myvaru162 = myvaru162 >> 1;myvaru161 = myvaru161 << 1;


68HC11 Instructions68HC11 Instructions: : Index RegistersIndex Registers• ABr

• Add ACCB to Ir• CPr

• Compare Ir to memory• DEr

• Decrement Ir• DES

• Decrement SP• INr

• Increment Ir• INS

• Increment SP• LDr

• Load Ir• LDS

• Load SP

• PULr• Pull Ir off stack

• PSHr• Push Ir on stack

• STr• Store Ir

• STS• Store SP

• TSr• Transfer SP to Ir

• TrS• Transfer Ir to SP

• XGDr• Exchange D with Ir


68HC11 Instructions: CCR68HC11 Instructions: CCR• CLC

• Clear the C Flag• CLI

• Clear the I Flag• CLV

• Clear the V Flag• TAP

• Transfer ACCA to CCR

• SEC• Set the C Flag

• SEI• Set the I Flag

• SEV• Set the V Flag

• TPA• Transfer CCR to ACCA


68HC11 Instructions:68HC11 Instructions:Jumps, Subroutines, Interrupts, MiscJumps, Subroutines, Interrupts, Misc

• JMP (Jump)• Jump to $HHLL

• BSR (Branch to Sub)• JSR to PC+Offset

• JSR (Jump to Sub)• Push PC on stack• Set PC to $HHLL

• RTS (Return from Sub)• Pop PC off stack

• NOP (No operation)• Do nothing

• RTI (Return from Interrupt)• Pop PC, all registers and CCR from

stack• SWI (Software Interrupt)

• Push CCR, all registers and PC on stack, call SWI vector

• WAI (Wait for interrupt)• Put MPU to sleep and wait for

interrupt• STOP

• Stop MPU


Expanding 6800 Expanding 6800 OpcodesOpcodes• Had to maintain backwards compatibility 68HC11

• Cannot change the opcodes of any mnemonics from 6800• Add to what is available (58 unused opcodes)

• “D” operations, BRSET/BRCLR, BSET/BCLR, etc.• Add “pre-bytes” ($18, $1A, and $CD) to switch the CPU into a

different opcode mode for remainder of the instruction• Include index register “Y”, and more “D” operations• Acceptable compromise when you consider the expected lifetime of the

68HC11• 68HC12 is “functionally” similar to the 68HC11, but optimized

the opcodes and introduced newer addressing modes


6800 6800 OpcodeOpcode MapMapPage 1 INH INH REL INH ACCA ACCB IND,X EXT IMM DIR IND,X EXT IMM DIR IND,X EXT

MSB 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111LSB 0 1 2 3 4 5 6 7 8 9 A B C D E F0000 0 SBA BRA TSX 00001 1 NOP CBA BRN INS 10010 2 BHI PULA 20011 3 BLS PULB 30100 4 BCC DES 40101 5 BCS TXS 50110 6 TAP TAB BNE PSHA 60111 7 TPA TBA BEQ PSHB 71000 8 INX BVC 81001 9 DEX DAA BVS RTS 91010 A CLV BPL A1011 B SEV ABA BMI RTI B1100 C CLC BGE C1101 D SEC BLT BSR D1110 E CLI BGT WAI E1111 F SEI BLE SWI F

0 1 2 3 4 5 6 7 8 9 A B C D E F

For reference only

JSRJMP LDS LDX

CLR STS STX

ADDINC CPXTST

ASL EORROL ADCDEC ORA

BITROR LDAASR STA STA

SBCCOMLSR AND

Op-Code Map ACCA ACCB

NEG SUBCMP


68HC11 68HC11 OpcodeOpcode Map (Page 1)Map (Page 1)DIR

Page 1 INH INH REL INH ACCA ACCB IND,X EXT IMM DIR IND,X EXT IMM DIR IND,X EXTMSB 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

LSB 0 1 2 3 4 5 6 7 8 9 A B C D E F0000 0 TEST SBA BRA TSX 00001 1 NOP CBA BRN INS 10010 2 IDIV BRSET BHI PULA 20011 3 EDIV BRCLR BLS PULB 30100 4 LSRD BSET BCC DES 40101 5 ASLD BCLR BCS TXS 50110 6 TAP TAB BNE PSHA 60111 7 TPA TBA BEQ PSHB 71000 8 INX PAGE2 BVC PULX 81001 9 DEX DAA BVS RTS 91010 A CLV PAGE3 BPL ABX A1011 B SEV ABA BMI RTI B1100 C CLC BSET BGE PSHX C1101 D SEC BCLR BLT MUL BSR PAGE4 D1110 E CLI BRSET BGT WAI E1111 F SEI BRCLR BLE SWI XGDX STOP F

0 1 2 3 4 5 6 7 8 9 A B C D E FIND,X

SUBCMP

For reference only

ROL

NEG

COMLSR

RORASRASL

DEC

INCTST

CLRJMP

BITLDA

STA STA

SBCSUBD ADDD

Op-Code Map

JSRLDS

STS STXLDX

STD

EORADCORAADD

CPX LDD

ACCA ACCB

AND


68HC11 68HC11 OpcodeOpcode Map (Page 2)Map (Page 2)INH INH INH IND,Y IMM DIR IND,Y EXT IMM DIR IND,Y EXT

MSB 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111LSB 0 1 2 3 4 5 6 7 8 9 A B C D E F0000 0 TSY NEG SUB SUB 00001 1 CMP CMP 10010 2 SBC SBC 20011 3 COM SUBD ADDD 30100 4 LSR AND AND 40101 5 TYS BIT BIT 50110 6 ROR LDA LDA 60111 7 ASR STA STA 71000 8 INY PULY ASL EOR EOR 81001 9 DEY ROL ADC ADC 91010 A ABY DEC ORA ORA A1011 B ADD ADD B1100 C BSET PSHY INC LDD C1101 D BCLR TST JSR STD D1110 E BRSET JMP LDS E1111 F BRCLR CLR XGDY STS F

0 1 2 3 4 5 6 7 8 9 A B C D E FIND,Y

Page 2 (18XX)

For reference only

Op-Code Map ACCA ACCB

CPY

LDYSTY


68HC11 68HC11 OpcodeOpcode Map (Page 3)Map (Page 3)IMM DIR IND,X EXT IND,X

MSB 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111LSB 0 1 2 3 4 5 6 7 8 9 A B C D E F0000 0 00001 1 10010 2 20011 3 30100 4 40101 5 50110 6 60111 7 71000 8 81001 9 91010 A A1011 B B1100 C CPY C1101 D D1110 E LDY E1111 F STY F

0 1 2 3 4 5 6 7 8 9 A B C D E F

For reference only

CPD

Op-Code Map ACCA ACCBPage 3 (1AXX)


68HC11 68HC11 OpcodeOpcode Map (Page 4)Map (Page 4)IND,Y IND,Y

MSB 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111LSB 0 1 2 3 4 5 6 7 8 9 A B C D E F0000 0 00001 1 10010 2 20011 3 CPD 30100 4 40101 5 50110 6 60111 7 71000 8 81001 9 91010 A A1011 B B1100 C CPX C1101 D D1110 E LDX E1111 F STX F

0 1 2 3 4 5 6 7 8 9 A B C D E F

For reference only

Op-Code Map ACCA ACCBPage 4 (CDXX)


Delay GenerationDelay Generation• It is quite often that a programmer must implement a

delay in a microcomputer to deal with the much slower operating speed of humans• Examples:

• Signal bounce from a switch• Pulse generation times• Interfacing with slower devices

• We may implement these delays with loops and ineffective coding (eg. NOPs)


Delay GenerationDelay Generation• A NOP requires 2

cycles• Cycle counts

respectively are:• 2 + 64x(2+2+3)

= 450 cycles• Each cycle is 500 ns• 225 μs delay

• Can add more NOPsfor better resolution

Memory Address

Contents Mnemonic Description

$C350 $86 $40 LDAA #$40 Set ACCA to 64

$C352 $01 NOP Delay 2 cycles

$C353 $4A DECA Decrement ACCA

$C354 $26 $FC BNE $C352 If not zero, branch back

$C356 ?? ?? ??


Hardware TimersHardware Timers• The 68HC11 has a free-running timer,

which is constantly running (TCNT)• Constantly incrementing based on the

E-clock and a pre-scale factor• Set to $0000 at RESET

• The timer can be read only by a 16 bit operation (LDD, LDX, LDY) to avoid timer changing in between 8 bit reads

• When the timer reaches $FFFF, it resets back to $0000

Address: $1024—Timer Mask Register 2 (TMSK2)

Bit 7 6 5 4 3 2 1 Bit 0

Read:TOI RTII PAOVI PAII 0 0 PR1 PR0

Write:

Reset: 0 0 0 0 0 0 0 0

PR1 PR0 PrescaleFactor

Crystal Frequency

223 Hz 8 MHz 4 MHz

One Count (Resolution)/Overflow (Range)

0 0 1 477 ns/31.25 ms 500 ns/32.77 ms 1 μs/65.54 ms

0 1 4 191 μs/125 ms 2 μs/131.1 ms 4 μs/262.1 ms

1 0 8 3.81 μs/250 ms 4 μs/262.1 ms 8 μs/524.3 ms

1 1 16 7.63 μs/0.5 s 8 μs/524.3 ms 16 μs/1.049 s

2.1 MHz 2 MHz 1 MHz

Bus Frequency (E Clock)

Address: $100E—Timer Counter - High Byte (TCNT)

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Address: $100F—Timer Counter - Low Byte (TCNT+1)

Read: Bit 7 6 5 4 3 2 1 Bit 0

Write:


Hardware TimersHardware Timers• How do we know when the

timer switches from $FFFF to $0000?

• A flag is set (7th bit of TFLG2) when the timer overflows

• If we are concerned about this, we can read this register to find out when it happens (or the system can generate an interrupt) so that we can handle it

Address: $100E—Timer Counter - High Byte (TCNT)

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Address: $100F—Timer Counter - Low Byte (TCNT+1)

Read: Bit 7 6 5 4 3 2 1 Bit 0

Write:

Address: $1024—Timer Mask Register 2 (TMSK2)

Bit 7 6 5 4 3 2 1 Bit 0

Read:TOI RTII PAOVI PAII

0 0PR1 PR0

Write:

Reset: 0 0 0 0 0 0 0 0

Address: $1025—Timer Flag Register 2 (TFLG2)

Bit 7 6 5 4 3 2 1 Bit 0

Read: TOFRTIF PAOVF PAIF

0 0 0 0

Write:

Reset: 0 0 0 0 0 0 0 0

programming the 68hc11 mpu – chapter 7courses.muscedere.com/elec32701/elec3270-ch7.pdf ·...

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