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•Bottom-Bottom-Up Methodology

R. V. Joshi, M. Ziegler, IBM, T. J. Watson Research Center,

Yorktown Heights, NY

Programmable Supply Boosting

Techniques for Near Threshold and

Wide Operating Voltage SRAM

This research was developed with funding from the Defense

Advanced Research Projects Agency (DARPA)

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● Introduction

● Prior Art

● Motivation

● Circuits

● Simulations

● Hardware Results

● Conclusions

Outline

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Difficulty in reducing Vmin of SRAM due to technology scaling and PVT variation

At low Vmin maintaining cell functionality is an issue

o Read stability

o Write-ability

o Data Retention

o Timing of critical signals

● Critical to maintain array performance over range of voltages (low and high)

● Reliability

● Yield

Introduction

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SRAM Cell Size

SRAM scale size continues to shrink

Technology (nm)

Cell

Siz

e (m

m2)

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To improve Performance, and Functionality (stability, write-ability) for conventional 6T/8T cells variety of circuit techniques are proposed such as:

● Static/Dynamic Power supplies for SRAM

- Dual Supply

- Power Supply Boosting Technique for either SRAM

cell or wordline drivers

- Charge pump and other means for boosting

● Usage of Multi-Vt Devices

● Short Bitlines

● Write Assist Techniques

● Addition of extra transistors to SRAM Cell (e.g 7T, 8T, 9T, 10T etc.)

In addition to these solutions to lower power and maintain functionality near threshold voltage SRAM is needed

Prior Art

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Motivation

• Design and develop low Vmin SRAM compared to

prior work

• Fabricate in 14nm Technology

• Demonstrate functionality over wider range of

operating voltages

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Concept• FinFET Based Boost Circuit

Wch = 2 x Hfin

Dfin

Boost

Boost

Transistor

With

additional

capVddv

Vdd

Macro

Logic &

Arrays

Boost

Clock

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X Y

Z

Usage of novel 3D ALDS methodology for accurately

predicting capacitances for 8T SRAM

Also wordline and bitline capacitances are extracted

Incorporation of detailed capacitance based on all possible

interaction of layout components into simulation

Evaluation of Impact on functionality and Vmin

Usage of input Vdd cap for design of boost circuit

Concept

rwl

wwl

gndbl

Vddv

blbgnd

gndrblb

Write

bitlin

e tru

e (

bl)

Write

bitlin

e c

om

p (

blb

)

Read wordline

(rwl)

Read local

bitline (rblb)

Write wordline (wwl)

cmp

tru

PGPU

PD

Stack2

Stack1

Vddv

gnd

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TCAD Based Boost Waveforms

Waveforms at high and low frequency at high and low voltages (simplified circuit)

20-50% boost can be obtained at 1 and 0.5 V respectively

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Boost Generator• Programmable boost generator

• Separate NFET and PFET Boost control for fine

granularity

NFET Boost

Vddv

Vdd

Programmable Boost

Pulse Generator

PFET Boost

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Simulations

write

wordline

decoderRead

address

DEC_RWL

DEC_WWLwrite

wordline

decoderWrite

address

Vddv

Negative

Boost

Write

Assist

Write Clock

Write Enable

datain datain0c

datain0t

datac_wradatat_wra

Programmable

bit

Load

Cells

Load

Cells

datat (bl)

datat

datacrblc

datac (blb)

Load

Cells

precharge

Boost_P Vddv

Vdd

Vdd

wwl

rwl

Vddv supply connected to

circuits inside dotted line

Read bitline

cmp

tru

Boost_N

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Simulations Impact of Boost

– Boost impact on Vddv for various booster strengths

and for dual and single boost signals.

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Statistical Design Methodology

Monte Carlo very slow to capture rare fail events

Newly Developed Mixture Importance sampling helps to

improve the rate of sampling in the important regions.

Recent Development- 6-7 orders of magnitude speed

improvement over standard MC

Probability Too many

samples!Too few

samples!

Probability

Importance

Sampling

Samples are weighted with

occurrence probability!

Mixture Importance

Sampling (MixIS)

Process parameter Process parameter

R. Kanj, R. V. Joshi, S. Nassif, “Mixture Importance Sampling and Its Application to the Analysis of SRAM Designs in the Presence of Rare Failure

Events,” Proc. 43rd Design Automation Conf 2006, pp. 69-72.

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Simulations Impact of Boost

– Yield comparison for various assist techniques using

Mixture Important Sampling

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Design Description Usage of Boost Circuits (Positive and negative) for Full

Macro (36 Kb/copy, 256 wordlines x 144 bitlines), 4 copies

144 Data out , muxed at the output to reduce to 4 bits

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Die Photo• Boosters are placed around he macro (36Kb)

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Hardware Results• Waveforms from hardware: write/read/write/read

(0.3 V)

clk

data_in

rd_ena

wr_ena

data_out

cycle

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Hardware Results• Impact of Boost Timing on Vmin

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Hardware Results• Occurrences of random chips vs. read access

time at 0.6V and 0.4V.

• Boosted Technique shows lower Access time compared to “No

Boost”

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Hardware Results• Boost Signal Timing Impact on Read access for

lower and higher voltages

•Boosted Technique shows lower Access time compared to “No Boost”

•Optimal boost timing yield can yield further lowering of the access time

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Hardware Results• Measured Power at 850 C

• Power savings by lowering the voltage through “Boost”

• “No Boost” shows no functionality below 0.45 V (in Red)

• Power reduction is at wordline pulse of 70ps vs 10ns with power at

10ns as the reference

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CONCLUSIONS

A novel boosting design is presented to offer

programmability, boost pulsewidth, and timing at

extreme low voltages with wider operating voltage range

Simulation results show that the boost gain is 15-20% at

voltages lower than 0.5V with optimized boost buffers

Hardware measurements for boosted chip demonstrate

full functionality at -10°C with Vmin of 0.3-0.4V

Boost shows 10-15% lower access time than

without the boost

Boost shows 15-20% lower power power compared to “No

Boost” by operating at lower voltages.

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ACKNOWLEDGEMENT

This research was developed with funding from the

Defense Advanced Research Projects Agency

(DARPA)