An Ultra-Low-Voltage CMOS Mixer Using Switched-Transconductance

Current-Reuse Dynamic-Threshold-Voltage Gain-Boosting

Techniques

Amir Hossein Masnadi and Shahriar MirabbasiIEEE NEWCAS, June 2012

Big Picture

Above Picture : Smart Stents, SoC and MEMS lab, UBC

• Biomedical Application

• Low Power Wireless Communication

Designing Building Blocks for Ultra-Low–Voltage/Power CMOS RF Front-End for applications such as:

Outline• Overview of Conventional Active Mixers

• Overview of techniques– Stack Reduction, LO-Gm Separation – Current-Reuse – Dynamic Threshold

• Mixer Design – Gm-Stage - Double Balanced Current Reuse Gilbert Structure – LO -Stage - Switched Supply Voltage

• Post-Layout Simulation Results and Comparison

• Concluding remarks

3

Conventional Active Mixers• Gilbert-Type Mixer (Current commutating)

– 3 stacked transistors each transistor VDS is around VDD/3• Considering Vth is around 0.4 V, minimum supply voltage is around 1.2 V

– To increase conversion gain (CG) one can increase load (CGαRL×)• Penalty: more voltage drop across load trade-off between VDD and CG

– Mixer core is always ON (For Biasing the transistors)

Even more challenging if IIP3 has to be improved

Limitations for Supply-Voltage:

Power Consumption issue:

Challenge of biasing current source in saturation for low supply voltage (e.g. VDD < 1.5)

Reduce the voltage drop across the Load Resistor to increase M1 drain Voltage

Supply Voltage (V) – Year (1997-2012)

Range of Threshold Voltage

1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 20130

0.10.20.30.40.50.60.70.80.9

11.11.21.31.41.51.61.71.81.9

22.12.22.32.42.52.62.72.82.9

33.1

f(x) = 3.94139347072221E+051 exp( − 0.0591562151041283 x )

y = -0.0853x + 172.44

Roughly Reduction of 0.085 V/Year

•Bulk_Driven and Folded Methods•Very Low CG (1<CG<9)

Mixer Power (mW)– Year (1997-2012)

1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 20130123456789

1011121314151617181920212223242526272829303132

f(x) = 9.53238791092096E+121 exp( − 0.139410024325391 x )

y = -0.8847x + 1781

Roughly a reduction of 0.88 mW/Year (it is leveling off)

Design Bottlenecks • Stacked Architectures : For decreasing Supply Voltage we should reduce Number of transistor

Stacked stages , we have different methods , below we bring ONLY two of them :

– Bulk-Driven Method • Low Conversion Gain (Mostly below 10)• Constant Biasing Current

– Folded Gilbert Architecture • Moderate Conversion Gain – Wide Band • Constant Biasing Current • Bulky Inductors

• Threshold Voltage : If decreases the headroom will increases, so it would be nice if we have lower threshold Voltage

We can't find any significant publication for reducing threshold voltage in Mixers

Proposed Techniques for Ultra Low Voltage Mixer 1. Reducing Stacked Transistors by Switched Transconductance:

– LO-Stage and Gm-Stage can be separated by switching supply voltage of Gm-Stage

– Turn ON & Off Gm-Stage with LO Save Power

Gm1 Gm2

VDD

GND

VDD

GND

VDD

+VIF

VDD

RL

RL

-VRF

VDDVDD

VDD VDD

+VRF +VRF-VRF

-VIF

+LO -LO

-LO +LO(a)

Gm-Stage

LO-Stage

-VRF+VRF

VDD

RL VIF

-LO+LO

Gm-Stage

LO-Stage

-VRF+VRF

VDD

RL VIF

-LO+LO

Gm1

VDD

GNDRL

VDD

VRF Gm.VRF

Current Commutating Approach Gm ON/OFF Approach

Proposed Techniques for Ultra-Low-Voltage Mixer

2. Choosing Gm-Stage, Maximizing Conversion Gain and Linearity: Pick a proper Gm-Stage for High Conversion Gain (High output Gm) and High Linearity Current-Reuse technique– Overal Gm = gmn+gmp

– Linearity will be improved

Total Gm=gmn+gmp

Total Gm=gmn

Current-Reuse is similar to Push-Pull Buffer

DTM

OS

Inverter

Switching Stage• We should implement a switch between VDD and GND

– Different Options :• Simple Digital Inverter• High-speed comparator (compare LO with GND, requires low LO power)

VDD

-LO

A

• Inverter with Dynamic Threshold-Voltage:Reduce VTH of NMOS transistors by connecting inverter output to body of

NMOS (DTMOS)

VDD

LO

CL

VDD

LO

CL

A B

(a) (b)

Output voltage of the inverter with CL=1pF, PLO= −8 dBm, 2.45 GHz LO signal

and DC value of LO is 0.3 V, (a) with dynamic threshold (DTMOS) inverter (b) without DTMOS..

Proposed Building Block For ULV Mixer

M1

M2

Cd

VRF

-LO

VDD

RLVIF

+LO

Current Reuse

Gm stage

Switching Stage

10K 10K

10K10K

VBP

VBN

M1 M2

M3 M4

Cd Cd

-VRF+VRF

10K 10K

10K10K

VBP

VBN

M7 M8

M5 M6

Cd Cd

-VRF +VRF

-LO

+LO

VDD

RL

RL

+VIF

VDD

-VIF

PMOS

NMOS

NMOS

PMOS

DTMOSInverter

DTMOSInverter

A

B

+

-Vout

DifferentialCurrentReuse1

DifferentialCurrentReuse2

Proposed Double-Balanced Design

Post-Layout Simulation Results Case 1 :

SubThreshold

Case 2 : Sub

Threshold

Case 3 : Super

Threshold

Case 4 : Super

Threshold

Case 5 : Super

Threshold

VDD (V) 0.35 0.4 0.5 0.8 1.2VBN (V) 0.35 0.40 0.47 0.4 0.75VBP (V) 0.00 0.00 0.00 0.4 0.6

PLO (dBm) -3.75 -4.00 - 4.1 -6.6 -7.5NF (dB) 12.7 11.2 10.56 12 11.1CG (dB) 13 14.7 15.8 15.2 17.3

IIP3 (dBm) -3.08 -5.54 -8.6 -7.04 -8.1

PDC (mW) 0.48 0.6 1.6 3.4 12

-10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0-15

-10

-5

0

5

10

15

20

PLO(dBm)

Co

nv

ersio

n G

ain

(d

B)

VDD=1.2VDD=0.8VDD=0.5VDD=0.4VDD=0.35

• IBM0.13-µm CMOS• VTH≈ 0.42 V

Effect of Dynamic Threshold Technique

-10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0-40

-30

-20

-10

0

10

20

PLO(dBm)

Con

vers

ion

Gain

(dB

)

VDD=0.5 With DTNMOSVDD=0.5 Without DTNMOSVDD=1.2 With DTNMOSVDD=1.2 Without DTNMOS

DTM

OS

Inverter

Standard Inverter

Conversion Gain at Different Supply Voltages

-5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1-15

-10

-5

0

5

10

15

PLO(dBm)

Co

nv

ersi

on G

ain

(dB

)

VDD=0.25Volt

VDD from 0.4V to 0.2V

Parameters This Work* This Work* JSSC RFIC RFIC MTT MTTLO-Gm Architecture Separated Separated Separated Stacked Folded Folded Folded

LO-Gm Separation Method

DTMOS Inverter

DTMOS Inverter

Conventional Inverter

N/A N/A N/A N/A

Gm-Stage Current Reuse

Current Reuse

NMOS NMOS Current

Reuse

Current Reuse

NMOS

RF (GHz) 2.5 2.5 2.01 2.4 2.4 5.3 8.6IF (MHz) 50 50 10 60 1 1 4350PLO(dBm) −3.75 −4.1 −4 −9 −2.0 −3.6 −3.3

VDD(V) 0.35 Subthreshold

0.5 1 1 Subthreshold

1.8 0.9 0.6

PDC(mW) 0.48 1.6 0.5 0.5 8.1 6.6 0.6NF (dB) 12.7 10.56 23.7 18.3 12.9 24 15.9

IIP3(dBm) −3.08 −8.6 7 −9 1 −11.6 −8Conversion Gain (dB) 13 15.8 9.8 15.7 15.7 8.9 6

CMOS Technology (µm) 0.13 0.13 0.18 0.13 0.13 0.13 0.13FOM1 / FOM2

31.65 / 26.3 25.78 / 22 18.62 / 17.83

22.15/ 21.36

14.41 /

16.171.75 / 0.50

24.32 /21.31

Concluding Remarks

TSMC 90nm Process

Mixer Core Resonator Buffer

Active Balun

RF LO

IF+

IF-

Techniques to improve mixer performance:•Reduce stacked levels • For Gm-Stage , try to choose blocks with higher output Gm and Linearity• Reduce VTH by body effect (Dynamic Threshold Technique), Both for Gm-Stage and LO-Stage, so we can use it for increasing headroom an• Turn-off circuit when you don’t want to use it to save power

Resonator

VDD (V) 0.3

PLO (dBm) -8.4

CG (dB) 27-15

Frequency

DC-12GHz

PDC (mW) 0.09 mWatt

Acknowledgments1. NSERC2. CMC Microsystems

• IBM•TSMC

And thank you for listening!19

REFERENCES

• E.A.M. KLUMPERINK, S.M. LOUWSMA, G.J.M. WIENK, AND B. NAUTA, “A CMOS SWITCHED TRANSCONDUCTOR MIXER,“ IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.39, NO.8, PP. 1231- 1240, AUG. 2004.

• Hanil Lee; Mohammadi, S., “A 500μW 2.4GHz CMOS Subthreshold Mixer for Ultra Low Power Applications,“ IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, vol., no., pp.325-328, 3-5 June 2007.

• Kihwa Choi; Dong Hun Shin; Yue, C.P., “A 1.2-V, 5.8-mW, Ultra-Wideband Folded Mixer in 0.13-μm CMOS,“ IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, vol., no., pp.489-492, 3-5 June 2007.

• Assaderaghi, F.; Sinitsky, D.; Parke, S.A.; Bokor, J.; Ko, P.K.; Chenming Hu; "Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI ," Electron Devices, IEEE Transactions on , vol.44, no.3, pp.414-422, Mar 1997.

• V. Vidojkovic, et al., “A Low-Voltage Folded-Switching Mixer in 0.18-um CMOS, “ IEEE J. Solid-State Circuits, vol. 40, pp. 1259-1264, June 2006.

• S. He and C.E. Saavedra, “An Ultra-Low-Voltage and Low-Power 2 Subharmonic Downconverter Mixer,” IEEE Transactions on Microwave Theory and Techniques, vol. 60, no. 2, pp. 311-317, Feb. 2012.

• M. Huang, et al., "A 5.25-GHz CMOS Folded-Cascode Even-Harmonic Mixer for Low-Voltage Applications," IEEE Trans. Microwave Theory Tech., vol. 54, no. 2, pp. 660-669, Feb. 2006.