Proceedings of the ASP-DAC '99

Asia and South Pacific Design Automation Conference 1999

January 18-21, 1999 Hong Kong Convention and Exhibition Centre

Wanchai, Hong Kong

Sponsors

IEEE Hong Kong Section Computer Chapter and CASKOM Chapter

Hong Kong Institute of Engineers (Electronics Division)

City University of Hong Kong

The Chinese University of Hong Kong

The Hong Kong University of Science & Technology

Supporters

In Technical Cooperation with: Design Automation Conference

In Cooperation with: ACM SIGDA

Chinese Institute of Electronics,

Hong Kong Computer Society,

Hong Kong Productivity Council, and

Institute of Electronics, Information and Communication Engineers

Donors

K C Wong Education Foundation (to provide financial support to conference participants from the mainland of China),

Cadence Design Systems Asia Ltd,

Hewlett Packard Hong Kong Ltd,

Sun Microsystems of California Ltd and Automated Systems (HK) Ltd

The University of Hong Kong

Additional copies may be ordered from:

IEEE Order Dept. Hoes Lane P.O. Box 1331 Piscataway, NJ 08854, U.S.A.

Copyright and Reprint Permission: Abstracting is permitted with credit to the source. Libraries are permitted to photocopy beyond the limit of U.S. copyright law for private use of patrons those articles in this volume that carry a code at the bottom of the first page, provided the per-copy fee indicated in the code is paid through Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923. For other copying, reprint or republication permission, write to IEEE Copyrights Manager, IEEE Service Center, 445 Hoes Lane, P.O. Box 1331, Piscataway, NJ 08855-1331. All rights reserved. Copyright01999 by the Institute of Electrical and Electronics Engineers, Inc.

IEEE Catalog Number 99EX198 ISBN 0-7803-5012-X (Softbound Edition) ISBN 0-7803-5013-8 (Microfiche Edition) ISBN 0-7803-5014-6 (CD-ROM Edition) Library of Congress: 98-86104

ASP-DAC'99 Organizing Committee

General Co-chairs Secretary

Richard M. M. Chen City University of Hong Kong

Andrew M. Layfield City University of Hong Kong

Qian-Ling Zhang Fudan University, Shanghai

Anthony S. S. Fong City University of Hong Kong

Vice General Chair Tutorial Co-chairs

C. K. Wong The Chinese University of Hong Kong

Philip H. W. Leong The Chinese University of Hong Kong

Technical Programme Co-chairs Jack Poon

Philip C. H. Chan The Hong Kong University of Science and Technology

Motorola Semicconductors Hong Kong Ltd.

Xian-Long Hong Tony T.K. Lee Tsinghua University, Beijing The Chinese University of Hong Kong

Hiroaki Kunieda Tokyo Institute of Technology

Masao Yanagisawa Waseda University

Finance Co-chairs

Angus K. M. WU City University of Hong Kong

... 111

Finance Co-chairs

Kevin J. Chen City University of Hong Kong

Exhibition Chair

Wai-On Law Motorola Semiconductors Hong Kong Ltd. -w

Publication Chair Industrial Sponsorship Chair

David Y. L. Wu The Chinese University of Hong Kong

Anthony S. S. Fong City University of Hong Kong

Publicity Chair

Howard C. Luong The Hong Kong University of Science and Technology

Registration Chair

Hei Wong City University of Hong Kong

Design Contest Co-chairs

Chi-Ying Tsui The Hong Kong University of Science and Technology

Local Arrangement Chair

Oliver C. S. Choy The Chinese University of Hong Kong

Other 0. C. Members

S. T. Lai Hua KO Electronic Co., Ltd., Hong Kong

International Liaison Chair

Paul Y. S. Cheng The University of Hong Kong

C. K. Tang Telecom Technology Centre, Hong Kong

iv

P. E Tsui Vocational Training Council, Hong Kong

K. Y. Tong The Hong Kong Polytechnic University

Mike W. T. Wong The Hong Kong Polytechnic University

V

International Advisory Committee Chair Omar Wing

The Chinese University of Hong Kong (retired)

International Advisory Committee Members

Raul Camposano Synopsys, USA

Francis Y. L. Chin The University of Hong Kong

Tokinori Kozawa STARC, Tokyo

San-Li Li Tsinghua University, Beijing

Steve Youn-Long Lin Tsing Hua University, Hsinchu

Isao Shirakawa Engineering Osaka University

Alexander L Stempkovsky Russian Academy of Sciences

Regional Representatives

Zhenmin Chai Chinese Academy of Sciences, Beijing

Jacob Katzenelson Israel Institute of Technology, Haifa

Chong-Min Kyung Korea Advanced Institute of Science & Tech., Taejon

Hon-Wai Leong National University of Singapore

Steve Youn-Long Lin Tsing Hua University, Hsinchu

Eric Lindberg Technical University of Denmark

Mahesh Mehendale Texas Instruments, Bangalore

Tsuneo Nakata Fujitsu Laboratories Ltd., Kawasaki

Anatoly 1.Petrenko Ukrainian Academy of Engineering Sciences

Wolfgang Rosenstiel Universitaet Tuebingen, Germany

David Skellern Macquarie University, Sydney

Ting-Ao Tang Fudan University, Shanghai

Xue-Ren Zheng South China University of Technology, Guangzhou

Tohei Kono Sinorex (Japan) Limited, Tokyo

ASP-DAC'99 Secretariat

c/o Prof. Philip Chan Department of Electrical and Electronic Engineering

The Hong Kong University of Science and Technology Clear Water Bay, Kowloon, Hong Kong

Fax: (852) 2358-1485 Email: eepchan@ust.hk ASP-DAC'99 Website

http://www.ee.ust. hMASPDAC99

vi

ASP-DAC Steering Committee

Chair

Tatsuo Ohtsuki Philip Chan Department of Electronics, Information & Communication Engineering Science and Technology Waseda University 3-4-1 Okubo, Shinjuku Tokyo 169, Japan

The Hong Kong University of

Tel: +81-3-5286-3387 Fax: +81-3-3203-9184 E-mail: ohtsuki@ohtsuki.comm.waseda.ac.jp

Vice Chair

Fumiyasu Hirose Cadence Design Systems, Japan E-mail: hirose@cadence.com

Secretary

Tsuneo Nakata Fujitsu Laboratories Ltd. E-mail: nakata@flab.fujitsu.co.jp

ASP-DAC '99 General Chair

Tokinori Kozawa Semiconductor Technology Academic Research Center (STARC)

ASP-DAC '99 Secretary

Toshihiro Hattori Hitachi Ltd.

ASP-DAC '99 Technical Program Co-chairs

IEICE TGCAS Chair

Akinori Nishihara Tokyo Institute of Technology

IEICE TGVLD Chair

Hitoshi Kitazawa .- NTT Corporation

IEICE TGICD Chair

Gensuke Goto Fujitsu Laboratories Ltd.

IPSJ SIGDA Chair

Kenii Yoshida &- Toshiba Corporation

JIPC Representative

I

Shuji Tsukiyama Chuo University

vii

Kunihiro Asada University of Tokyo

ACM SIGDA Representative Chong-Min Kyung

Nikil Dutt and Technology

University of California at Irvine

Korea Advanced Institute of Science

IEEE CAS Representative Hon-Wai Leong

Graham R. Hellestrand University of New South Wales

National University of Singapore

DAC Representative

Basant R. Chawla Lucent Technologies

EDA Technofair Chair

Yoshitada Fujinami NEC Corporation

EIAJ EDA TC Representative

Sagoro Hazama Fujitsu Limited

International Members

Xian-Long Hong Tsinghua University, Beijing

Youn-Long Steve Lin Tsing Hua University, Hsin-Chu

Sunil D. Sherlekar Silicon Automatlon Systems (India) Pvt. Ltd.

David Skellem Macquarie University

Omar Wing The Chinese University of Hong Kong (retired)

... V l l l

Ellen J. Yoffa IBM Corporation

Qianling Zhang Fudan University, Shanghai

Nobuaki Kawato Fujitsu Laboratories of America

Shigeo Kuninobu Matsushita Electric Industrial Co., Ltd.

Advisory Members (Industries) Masami Masuyama

Kazuyuki Hirakawa Oki Electric Industry Co., Ltd.

Seiko Instruments Inc.

Eisaburo Iwamoto Sony Corporation

Takashi Kambe Sharp Corporation

Osamu Karatsu Advanced Telecommunication Research Institute International

Shin'ichi Murai Mitsubishi Electric Corporation

Fusao Wada Zuken Inc.

Kenji Yoshida Toshiba Corporation

ix

Takeshi Yoshimura NEC Corporation

Hideo Fujiwara Nara Institute of Science and Technology

Yoshikazu Miyanaga Hokkaido University

Advisory Members (Academia) Yukihiro Nakamura

Toshiro Akino Kinki University

Kyoto University

Hidetoshi Onodera Kyoto University

Masaharu Imai Osaka University

Michitaka Kameyama Tohoku University

Hiroaki Kunieda Tokyo Institute of Technology

Tsutomu Sasao Kyushu Institute of Technology

Isao Shirakawa Osaka University

Kazuhiro Ueda Shibaura Institute of Technology

X

Shin’ichi Wakabayashi Hiroshima University

Masao Yanagisawa (formerly Sato) Waseda University

Hiroto Yasuura Kyushu University

xi

Welcome to ASP-DAC’99

The 1999 Asia South Pacific Design Automation Conference, or ASP-DAC‘99, is the fourth in a series of annual international conferences on Design Automation(DA) in this region. For the first time, it is held outside of Japan, in Hong Kong.

Hong Kong is a Special Administrative Region of China. Under the policy of “one country two systems”, all of the circumstances which have contributed to Hong Kong’s success in the past such as low taxes, free trade, and rule of law, have continued unaltered. What has changed is the new awareness of the importance of advanced technology in the economic development of Hong Kong. Indeed, the government has recently set aside HK$5 billion to support and to encourage new initiatives in technology research and development.

Asia is one of the hottest silicon areas in the world. It has become a significant center of VLSI production and design. Thus it is most appropriate, and it is a privilege, to hold the ASP-DAC’99 in Hong Kong this year. It provides an opportunity for experts and practicing engineers to exchange ideas and to learn about the latest developments in DA and in integrated circuits and systems design, which are the subjects of the conference.

Four internationally renowned experts in this field will present keynote speeches at this Conference. They are Professor Hitoshi Watanabe, Dean of Faculty of Engineering at Soka University; Dr Chi-Foon Chan, President and Chief Operating Officer of Synopsys; Dr Robert Yung, Director of Intel China Research Center; and Dr Dipender Saluja, Vice President of Engineering & Services of Cadence Design System. Their topics include key areas of DA technology of general interest and the microprocessor technology for the 2 1 st Century.

Our Technical Program Committee, led by Co-chairs Professors Philip Chan, Xian-Long Hong and Hiroaki Kunieda, has assembled an excellent technical program consisting of keynote addresses, oral and poster paper presentations, embedded tutorials, panel discussion and university design contest. A number of invited speakers will give presentations in their expert areas.

The Tutorial Program Co-chairs have arranged three full-day tutorials on Monday, the first day of the Conference. An Exhibition of EDA software and hardware platform is organized by the Hong Kong Productivity Council in conjunction with the Organizing Committee. This exhibition will be held at conference venue during the conference period. Another EDA Techno Fair will be held in Japan by the end of January 1999.

We would like to acknowledge financial sponsorship of IEEE, ACM, HKIE and the universities in Hong Kong, the support of the Steering Committee, the advice of the International Advisory Committee, and the dedicated work of our Organizing Committee members. We also want to thank members of the Regional Representatives for their assistance. We are greatly indebted to our Steering Committee Chair Professor Tatsuo Ohtsuki and International Advisory Committee Chair Professor Omar Wing for their valuable guidance, advice and support during the past 22 months.

We welcome your participation at ASP-DAC’99 and sincerely hope that you will enjoy the Conference program and activities during your stay in Hong Kong.

Richard M. M. Chen and Qian-Ling Zhang General Co-chairs ASP-DAC’99 OC

xii

Welcome to ASP-DAC’99 Exhibition

Date: Show hours: Venue:

Admission:

Managed by:

January 18 (Monday) - 21 (Thursday), 1999 1O:OO AM - 5:OO PM Room 401, Hong Kong Convention and Exhibition Centre, 1 Harbour Road, Wanchai, Hong Kong Free of charge (registration is required at the exhibition entrance) Hong Kong Productivity Council

On behalf of the ASPDAC’99 Organizing Committee, I would like to invite you to attend the ASPDAC’99 Exhibition, which will be held in conjunction with the ASPDAC’99 Conference. Exhibitors will include companies involved in EDA tools, systems, related-products, and services, as well as local universities showing their EDA programs, systems and related achievements. The objectives are to promote the latest EDA technologies and products, to provide the latest information, and to provide an opportunity for the attending electronic design professionals and researchers to exchange ideas. Through the exhibition and the conference, we hope to contribute to the development and the growth of the EDA and electronic designs in Asia and South Pacific Region, which is the fastest growing region of the semiconductor industry.

Wai-On Law Chair, Exhibition ASPDAC’99 Organizing Committee

... Xl l l

Invitation to ASP-DAC 2000

ASP-DAC 2000 is the fifth in a series of annual international conferences on Design Automation to be held in Asia and South Pacific region. It will be held in Pacific0 Yokohama, Yokohama, Japan, during January 25 - 28,2000.

Asia and the South Pacific Region is one of the hottest silicon areas in the world in the sense that the amount of VLSI production is rapidly growing. Thus the conference aims at providing the Asian and South Pacific CAD/DA and Design community with opportunities of establishing leading edge research not only on specific design concepts but also on new aspects of approaches to integrated design concepts.

Emphasized in the ASP-DAC 2000 will be more interaction between DA community and designers' community, which is essential to overcome the so-called "Design Crisis". We would like to welcome submissions on the wider range of design issues, including design practices/experiences themselves, as well as novel algorithms or tools, from system level down to physical and TCAD levels. Also, we continue the University LSI Design Contest to encourage academic educationhesearch of LSI design implementations.

EDA TechnoFair 2000, the premier Japanese EDA exhibition, will also be collocated with the ASP-DAC 2000. Exhibitors included will be leading edge EDA vendors and ASIC vendors, as well as universities who will demonstrate their researcldeducation results.

On behalf of the ASP-DAC 2000 Organizing Committee, it is my pleasure to invite ASP- DAC 2000 participants and other researchers, designers and professionals in our technical fields to submit papers and design to ASP-DAC 2000. For the conference, University LSI Design Contest and paper submission details, please visit our web site at http://www.jesa.or.jp/ASPDAC/

We look forward to having your participation.

Kenji Yoshida General Chair, ASP-DAC 2000

xiv

ASP-DAC’99 Technical Program Committee

Co-chairs

Philip C. H. Chan The Hong Kong University of Science and Technology

Xian-Long Hong Tsinghua University, Beijing

Hiroaki Kunieda Tokyo Institute of Technology

Members

Raul Camposano S ynopsys

Richard M. M. Chen City University of Hong Kong

Oliver C. S . Choy The Chinese University of Hong Kong

Jason Cong UCLA

Anthony S. S. Fong City University of Hong Kong

Jing-Yang Jou Chiao Tung University, Hsinchu

Andrew Kahng UCLA

Ryota Kasai NTT System Electronics Labs

Chong-Min Kyung KAIST

Wai On Law Motorola, HK

Mike Lee Avanti! Corporation

Philip H. W. Leong The Chinese University of Hong Kong

Howard Luong The Hong Kong University of Science and Technology

Mahesh Mehendale Texas Instruments, Bangalore

Sudhakar Muddu Silicon Graphics

Massoud Pedram University of Southern California

Wolfgang Rosenstiel Universitaet Tuebingen

Pushan Tang Fudan University

C. Y. Tsui The Hong Kong University of Science and Technology

Omar Wing The Chinese University of Hong Kong (retired)

C. K. Wong The Chinese University of Hong Kong

Hei Wong City University of Hong Kong

Mike W. T. Wong The Hong Kong Polytechnic University

Allen C. H. Wu Tsing Hua University, Hsinchu

Angus K. M. Wu City University of Hong Kong

David Y. L. Wu The Chinese University of Hong Kong

Hongxi Xue Tsinghua University, Beijing

Zhilian Yang Tsinghua University, Beijing

Kenneth Yun University of California, San Diego

Qian-Ling Zhang Fudan University

xv

3A. 1

3A.2

4A.2

6A. 1

7B .2

7B.3

7B .4

Best Paper Award Candidates Asia and South Pacific Design Automation Conference 1999

(ASP-DAC'99)

Reduced-Order Modelling of Time-Varying Systems Jaij eet Roychowdhury

Analysing Forced Oscillators with Multiple Time Scales Onuttom Narayan, Jaijeet Roychowdhury

Enhancing the Efficiency of Reduction of Large RC networks by Pole Analysis via Congruence Transformations Hui Zheng, Wenjun Zhang, Lilin Tian, Zhilian Yang

Design Method of MTCMOS Power Switch for Low-Voltage High-speed LSIS Shin'ichiro Mutoh, Satosh Shigematsu, Yoshinori Gotoh, Shinsuke Konaka

Optimal Wire Shape with Consideration of Coupling Capacitance under Elmore Delay Model Youxin Gao, D. F. Wong

New Multilevel and Hierarchical Algorithms for Layout Density Control Andrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky

Function Smoothing with Applications to VLSI Layout Ross Baldick, Andrew B. Kahng, Andrew Kennings, Igor L. Markov

1 1B.3 Combining GAS and Symbolic Methods for High Quality Tests of Sequential Circuits Martin Keim, Nicole Drechsler, Bernd Becker

xvi

ASP-DAC'99 University LSI Design Contest Committee

Co-chairs

Ryota Kasai NTT System Electronics Labs

Chi-ying Tsui The Hong Kong University of Science and Technology

Members

Kwok-ying Tong The Hong Kong Polytechnic University

Akinori Nishihara Tokyo Institute of Technology

Hidetoshi Onodera Kyoto University

Howard Luong The Hong Kong University of Science and Technology

Hiroaki Hirata Kyoto Institute of Technology

Toshio Kondo NTT System Electronics Labs.

Hideharu Amano Keio University

Neil Weste Macquarie University

C.P. Ravikumar India Institute of Technology, Delhi

Oliver Chiu-sing Choy The Chinese University of Hong Kong

Angus K. M. Wu City University, Hong Kong

Mike Lee Avanti! Corporation

xvii

University LSI Design Contest Summary Eight designs were submitted from three countries, Japan, Korea and Indonesia. Statistics in terms of the application areas, and design methodologies are summarized as follows:

A: Analog or A/D Mixed Signal; D: DSPMultimedia Application; M: Microprocessor; C: Custom Application; F/C: Full Custom or Cell-based; G/A: Gate Array

The submitted designs were reviewed by the members of the Design Contest Committee. After the review, seven designs were selected and one design was rejected. From the selected designs, the Design Contest Committee decided to confer an Outstanding Design Award and a Special Feature Award to two specific designs, which are summarized as follows.

Outstandinc Design Award

“A 16-bit DSP and System for BasebancWoiceband Processing of IS-136 Cellular Telephony”

Tae Hun Kim, Jeongsik Yang, Kyoo Hyun Lim, Jin Wook Kim, Jeong Eun Lee, Hyoung Sik Nam, Young Gon Kim, Jeong Pyo Kim,

Sang Jin Byun, Bae Sung Kwon, and Beomsup Kim

Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Taejon, Korea

(Digital Signal Processor, Full Custom Design)

Special Feature Award

“Motion Estimator LSI for MPEG2 High Level Standard”

Li, Jiang, Dongju Li, Shintaro Haba, Chawalit Honsawek, and Hiroaki Kunieda

Department of Electrical and Electronics Engineering, Tokyo Institute of Technology, Tokyo, Japan

(Digital Signal Processor, Full Custom Design)

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Table of Contents ... Organizing Committee ........................................................................................................................... 111

International Advisory Committee ......................................................................................................... vi

Steering Committee ............................................................................................................................... vii

Welcome to ASP-DAC'99 ..................................................................................................................... xii

Welcome to ASP-DAC'99 Exhibition ................................................................................................. xiii

Invitation to ASP-DAC 2000 ............................................................................................................... xiv

Technical Program Committee .............................................................................................................. xv

Best Paper Award Candidates .............................................................................................................. xvi

University LSI Design Contest Committee ......................................................................................... xvii

University LSI Design Contest Summary .............................. ....................................................... X V l l l

...

...

Session 1 Keynote Speech 1

Chair: 0. Wing

Session 2A Analog CAD

Chair: 0. Wing Co-chair: H. Yang

2A.1 Balanced Multi-Level Multi-Way Partitioning of Large Analog Circuits for Hierarchical Symbolic Analysis Xiang-Dong Tan and C.-J. Richard Shi ....................................................................................... 1

2A.2 Symmetry Detection for Automatic Analog Layout Recycling Youcef Bourai and C.-J. Richard Shi .......................................................................................... 5

2A.3 An SA-Based Nonlinear Function Synthesizer for Linear Analog Integrated Circuits Huazhong Yang, Rong Luo, Hui Wang and Runsheng Liu .......................................................... 9

Session 2B Physical Design 1 - Floorplanning

Chair: C. K. Wong Co-chair: X. Hong

2B.1 Relaxed Simulated Tempering for VLSI Floorplan Designs Jason Cong, Tianming Kong and Dongmin Xu ......................................................................... 13

2B.2 Slicing Floorplans with Boundary Constraint F. Y. Young and D. F. Wong ...................................................................................................... 17

2B.3 Design and Optimization of Power/Ground Network for Cell-Based VLSIs with Macro Cells Xiaohai Wu, Changge Qiao and Xianlong Hong ....................................................................... 21

xix

Session 2C Design Contest

Chair: C, Y. Tsui Co-chair: R. Kasai

2C. 1 An 8b 52 MHz Double-Channel CMOS A/D Converter for High-speed Data Communications Ju-Hyung Kim, Sung-Wook Hwang, Seung-Hoon Lee and Yong Jee ........................................ 25

2C.2 A 10b 50 MHz CMOS A/D Converter for High-speed Video Applications Byeong-Lyeol Jeon, Kang-Jin Lee, Seung-Hoon Lee and Sang-Won Yoon ............................... 29

2C.3 The Design of Delay Insensitive Asynchronous 16-bit Microprocessor Byung-Soo Choi, Dong- Wook Lee and Dong-Ik Lee ................................................................. 33

2C.4 An LSI Implementation of an Adaptive Genetic Algorithm with On-the-Fly Crossover Operator Selection Shin’ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Mutsuaki Goto, Yoshikatsu Nakayama and Koichi Hatta ................................................................................... 31

Motion Estimator LSI for MPEG2 High Level Standard Li Jiang, Dongju Li, Shintaro Haba, Chawalit Honsawek and Hiroaki Kunieda .................... 41

2C.5

2C.6 A Single-Chip CMOS CCD Camera Interface Circuit with Digitally Controlled AGC Jin-Kug Lee, Dong-Young Chang, Geun-Soon Kang and Seung-Hoon Lee ............................. 45

2C.7 16-bit DSP and System for Baseband / Voiceband Processing of IS-136 Cellular Telephony Tae Hun Kim, Jeongsik Yang, Kyoo Hyun Lim, Jin Wook Kim, Jeong Eun Lee, Hyoung Sik Nam, Young Gon Kim, Jeong Pyo Kim, Sang Jin Byun, Bae Sung Kwon and Beomsup Kim ...................................................................................................................... 49

Session 3A Circuit Simulation 1

Chair: R. M. M. Chen Co-chair: H. Yang

Reduced-Order Modelling of Time-Varying Systems Jaijeet Roychowdhury ................................................................................................................ 53

3A.1

3A.2 Analysing Forced Oscillators with Multiple Time Scales Onuttom Narayan and Jaijeet Roychowdhury ........................................................................... 57

3A.3 Waveform Relaxation of Linear Integral-Differential Equations for Circuit Simulation Yao-Lin Jiang and Omar Wing .................................................................................................. 61

3A.4 A New Technique to Exploit Frequency Domain Latency in Harmonic Balance Simulators M. M, Gourary, S. G. Rusakov, S. L. Ulyanov, M. M. Zharov, K. K. Gullapalli and B. J. Mulvaney ................................................................................................................................ 65

xx

3B.1

3B.2

3B.3

3B.4

4A.1

4A.2

4A.3

4B.1

4B.2

4B.3

4 c

Session 3B Physical Design 2 - Partitioning

Chair: A. B. Kahng Co-chair: C. K. Wong

An Efficient Two-Level Partitioning Algorithm for VLSI Circuits Jong-Sheng Chemg, Suo-Jie Chen, Chia-Chun Tsai and Jan-Ming Ho ................................... 69

An Efficient Iterative Improvement Technique for VLSI Circuit Partitioning Using Hybrid Bucket Structures C. K. Eem and J. W, Chong ....................................................................................................... 73

A Clustering Based Linear Ordering Algorithm for K-Way Spectral Partitioning Shiuann-Shiuh Lin, Wen-Hsin Chen, Wen- Wei Lin and Ting Ting Hwang .............................. .77

Faster and Better Spectral Algorithms for Multi-Way Partitioning Jan-Yang Chang, Yu-Chen Liu and Ting-Chi Wang ................................................................. 81

Session 3C EDA Roadmap

Chair: Y. Furui

Session 4A Circuit Simulation 2

Chair: H. Yang Co-chair: R. M. M. Chen

VCO Jitter Simulation and Its Comparison With Measurement Masayuki Takahashi, Kimihiro Ogawa and Kenneth S, Kundert .............................................. 85

Enhancing the Efficiency of Reduction of Large RC networks by Pole Analysis via Congruence Transformations Hui Zheng, Wenjun Zhang, Lilin Tian and Zhilian Yang .......................................................... 89

The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance Jinsong Hou, Zeyi Wang and Xianlong Hong ........................................................................... 93

Session 4B Physical Design 3 - Interconnection

Chair: D. F. Wong Co-chair: C, K. Wong

Interconnect Delay Estimation Models for Synthesis and Design Planning Jason Cong and David Zhigang Pan ......................................................................................... 97

An Analytical Delay Model for SRAM-Based FPGA Interconnections Feng Zhou, Zhijun Huang, Jiarong Tong and Pushan Tang ................................................... 101

Timing-Driven Bipartitioning with Replication Using Iterative Quadratic Programming Shihliang Ou and Massoud Pedram ........................................................................................ 105

Embedded Tutorial: An Integrated Battery-Hardware Model for Portable Electronics Massoud Pedram, Chi-Ying Tsui and Qing Wu ....................................................................... 109

xxi

6A.1

6A.2

6A.3

6A.4

6B.1

6B.2

6B.3

6B.4

Session 5A Keynote Speech 2

Chair: P. Chan

Session 6A Circuit 1 - Low-powermigh-speed

Chair: R. Kasai Co-chair: P. Leong

Design Method of MTCMOS Power Switch for Low-Voltage High-speed LSIs Shin’ichiro Mutoh, Satosh Shigematsu, Yoshinori Gotoh and Shinsuke Konaka .................... 113

A New Single-Clock Flip-Flop for Half-Swing Clocking Young-Su Kwon, Bong-il Park, In-Cheol Park and Chong-Min Kyung .................................. 117

Optimal Evaluation Clocking of Self-Resetting Domino Pipelines Kenneth Y. Yun and Ayoob E. Dooply ..................................................................................... 121

Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion Tomoyuki Yoda, Atsushi Takahashi and Yoji Kajitani ............................................................. 125

Session 6B Physical Design 4 - Analog, Noise

Chair: X. Hong Co-chair: D. Y. L. Wu

A Performance-Driven YO Pin Routing Algorithm Dongsheng Wang, Ping Zhang, Chung-Kuan Cheng and Arunabha Sen ............................... 129

An Automatic Router for the Pin Grid Array Package Shuenn-Shi Chen, Jong-Jang Chen, Suo-Jie Chen and Chia-Chun Tsai ................................. 133

Crosstalk Reduction by Transistor Sizing Tong Xiao and Malgorzata Marek-Sadowska ......................................................................... 137

A Technology-Independent Methodology of Placement Generation for Analog Circuit Wai-chee Wong, Philip C. H. Chan and Wai-On Law ............................................................. 141

Session 6C DA for Electronic Packages

Chair: G. Choksi

xxii

Session 6D Poster Session

6D.1

6D.2

6D.3

6D.4

6D.5

6D.6

6D.7

6D.8

6D.9

6D.10

6D.11

6D.12

6D.13

7A.1

7A.2

7A.3

7A.4

Technology Mapping for Low Power

An Efficient Approach to Constrained Via Minimization for Two-Layer VLSI Routing

Automatic Constraint Transformation with Integrated Parameter Space Exploration in Analog System Synthesis

Node Sampling Technique to Speed Up Probability-Based Power Estimation Methods

Chingwei Yeh, Chin-Chao Chang and Jinn-Shyan Wang ....................................................... 145

Maolin Tan, Karmran Eshraghian and Hon Nin Cheung ....................................................... 149

Nagu R. Dhanwada, Adrian Nunez-Aldana and Ranga Vemuri .............................................. 153

Hoon Choi, Hansoo Kim, In-Cheol Park, Seung Ho Hwang and Chong-Min Kyung ............. 157

Acceleration of Linear Block Code Evaluations Using New Reconfigurable Computing Approach

A New Numerical Method for Transient Noise Analysis of Nonlinear Circuits

Low Power CMOS Off-Chip Drivers with Slew-rate Difference Rung-Bin Lin and Jinq-Chang Chen ....................................................................................... 169

Benchmark Circuits Improve the Quality of a Standard Cell Library Rung-Bin Lin, Isaac Shuo-Hsiu Chou and Chi-Ming Tsai ...................................................... 173

Formal Design Verification for Correctness of Pipelined Microprocessors with Out-of-order Instruction Execution Takashi Takenaka, Junji Kitamichi, Teruo Higashino and Kenichi Taniguchi ....................... 177

Solving the Rectangular Packing Problem by an Adaptive GA Based on Sequence-Pair Koichi Hatta, Shin’ichi Wakabayashi and Tetsushi Koide ..........

Hazard-Free Synthesis and Decomposition of Asynchronous Circuits Ren-Der Chen, Jer Min Jou and Yeu-Horng Shiau ................................................................. 185

Hierarchical Floorplan Design on the Internet Jiann-Homg Lin, Jing-Yang Jou and Hui-Ru Jiang ................................................................ 189

A Scheduling Method for Synchronous Communication in the Bach Hardware Compiler Ryoji Sakurai, Mizuki Takahashi, Andrew Kay, Akihisa Yamada, Tetsuya Fujimoto and Takashi Kambe ................................................................................................................. 193

Hidehisa Nagano, Takayuki Suyama and Akira Nagoya ......................................................... 161

M. M. Gourary, S. G. Rusakov, S. L. Ulyanov, M. M, Zharov and B. J. Mulvaney ................. 165

Session 7A Circuit 2 - Multmedia chip designs

Chair: H. Kunieda Co-chair: A. K. M. Wu

Electronics Development of Silicon Mircodisplay for Virtual Reality Applications P. W. Cheng and H. C. Huang ................................................................................................. 197

High-speed and Low-Power Real-Time Programmable Video Multi-Processor for MPEG-2 Multimedia Chip on 0.6?m TLM CMOS Technology Seung-Min Lee, Jin-Hong Chung and M. M. -0. Lee ............................................................. 201

A Scalable Pipelined Architecture for Separable 2-D Discrete Wavelet Transform Jer Min Jou, Pei-Yin Chen, Yeu-Homg Shiau and Ming-Shiang Liang .................................. 205

A New Pipelined Architecture for Fuzzy Color Correction Jer Min Jou, Shiann-Rong Kuang and Yeu-Homg Shiau ........................................................ 209

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7B.1

7B.2

7B.3

7B.4

8A.1

8A.2

8A.3

8B.1

8B.2

8B.3

8C

Session 7B Physical Design 5 - Special Topics

Chair: D. Y. L. Wu Co-chair: X. Hong

Watermarking Layout Topologies Edoardo Charbon and Ilhami Torunoglu ................................................................................ 213

Optimal Wire Space with Consideration of Coupling Capacitance under Elmore Delay Model Youxin Gao and D. F. Wong .................................................................................................... 217

New Multilevel and Hierarchical Algorithms for Layout Density Control Andrew B. Kahng, Gabriel Robins, Anish Singh and Alexander Zelikovsky ........................... 221

Ross Baldick, Andrew B. Kahng, Andrew Kennings and Igor L. Markov ............................... 225 Function Smoothing with Applications to VLSI Layout

Session 7C Panel - System-on-a-chip

Chair: P. KO

Session 8A Timing analysis

Chair: w. 0. Law Co-chair: C. Y. Tsui

Layout-based Logic Decomposition for Timing Optimization Yun-Yin Lian and Youn-Long Lin ............................................................................................ 229

Timing Optimization of Logic Network Using Gate Duplication Chun-hong Chen and Chi-ying Tsui ........................................................................................ 233

Model Order Reduction of Large Circuits Using Balanced Truncation Payam Rabiei and Massoud Pedram ....................................................................................... 231

Session 8B Physical Design 6 - Placement & Route

Chair: J. Cong Co-chair: D. Y. L. Wu

Optimization of Linear Placements for Wirelength Minimization with Free Sites Andrew B. Kahng, Paul Tucker and Alex Zelikovsky .............................................................. 241

A New Global Routing Algorithm Independent of Net Ordering Haiyun Bao, Xianlong Hong and Yici Cai ............................................................................... 245

A Timing-Driven Block Placer Based on Sequence Pair Model Gang Huang, Xianlong Hong, Changge Qiao and Yici Cai .................................................... 249

Embedded Tutorial: Recent Advances in Asynchronous Design Methodologies Kenneth Y. Yun ......................................................................................................................... 253

Session 9 Keynote Speech 3

Chair: R. M. M. Chen

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10A.1

10A.2

10A.3

10A.4

10B.l

10B.2

10B.3

10B.4

l lA . l

llA.2

11A.3

llA.4

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llB.2

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llB.4

Session 10A Circuit 3 - Analog & Mixed Circuit

Chair: H. Luong Co-chair: P. b o n g

Universal Switched-Current Integrator Blocks for SI Filter Design Jack L. Chan and Steve S. Chung ............................................................................................ 261

An On-Chip Automatic Tuning Circuit Using Integration Level Approximation Technique Sung-Due Lee, Myung-Jun Jang and Won-Hyo Lee ................................................................ 265

A High-speed and Low Power Phase-Frequency Detector and Charge Pump Won-Hyo Lee, Jun-Dong Cho and Sung-Due Lee ................................................................... 269

A Single-Chip CMOS CCD Camera Interface Circuit with Digitally Controlled AGC Jin-Kug Lee, Dong-Young Chang, Geun-Soon Kang and Seung-Hoon Lee ........................... 273

Session 10B Testing 1

Chair: P. Cheung Co-chair: A. K. M. Wu

Data Path Synthesis for BIST with Low Area Overhead Xiaowei Li and Paul Y. S. Cheung ........................................................................................... 275

Testing Interconnects of Dynamic Reconfigurable FPGAs Chi-Feng Wu and Cheng-Wen Wu ........................................................................................... 279

Diagnosing Single Faults for Interconnects in SRAM Based FPGAs Yinlei Yu, Jian Xu, Wei Kang Huang and Fabrizio Lombardi ................................................ 283

An Adaptive BIST to Detect Multiple Stuck-Open Faults in CMOS Circuits Hafijur Rahaman, Debesh K. Das and Bhargab B. Bhattachaiya .......................................... 287

Session 11A Power EstimatiodLow-power

Chair: M. Pedram Co-chair: C Y Tsui

A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit Partition Kai Zhang, Tsuyoshi Shinogi, Haruhiko Takase and Terumine Hayashi ................................ 291

Estimation of Peak Current through CMOS VLSI Circuit Supply Lines Toshio Murayama, Kimihiro Ogawa and Haruhiko Yamaguchi ............................................. 295

Power Consumption in XOR-Based Circuits Yibin Ye, Kaushik Roy and Rolf Drechsler .............................................................................. 299

Exploiting Don’t Cares During Data Sequencing using Genetic Algorithms Nicole Drechler and Rolf Drechsler ........................................................................................ 303

Session 11B Testing 2 - Testing and formal Verification

Chair: M. Wong Co-chair: w. 0. Law

An Efficient Structural Approach to Board Interconnect Diagnosis Chun-Keung Lo and Philip C. H. Chan ................................................................................... 307

On the Testing Quality of Random and Pseudo-random Sequences for Permanent and Intermittent Faults Jin Ding and Yu-Liang Wu ...................................................................................................... 311

Combining GAS and Symbolic Methods for High Quality Tests of Sequential Circuits Martin Keim, Nicole Drechsler and Bemd Becker .................................................................. 3 15

Formal Verification Method for Combinatorial Circuits at High Level Design Junji Kitamichi, Hiroyuki Kageyama and Nobuo Funabiki .................................................... 319

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Chair:

Session 11C Panel - VLSI Design Education

Pro$ Asada

12A.1

12A.2

12A.3

12B.1

12B.2

12B.3

12B.4

12c.1

12c.2

12C.3

12C.4

Session 12A BDD

Chair: R. Drechsler Co-chair: A. Fong

Minimization of Free BDDs Wolfgang Giinther and Rolf Drechsler .................................................................................... 323

Application Driven Variable Reordering and an Example Implementation in Reachability Analysis Christoph Meindl, Klaus Schwettmann and Anna Slobodova ................................................. 327

Realization of Regular Ternary Logic Functions using Double-Rail Logic Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura and Atsumu Iseno .............................. 331

Session 12B Systems/HW SW co-design

Chair: T. Ohtsuki Co-chair: J. Poon

A HardwareBoftware Partitioning Algorithm for Processor Cores of Digital Signal Processing Nozomu Togawa, Takashi Sakurai, Masao Yanagisawa and Tatsuo Ohtsuki ......................... 335

Generation of Interpretive and Compiled Instruction Set Simulators Rainer Leupers, Johann Elste and Birger Landwehr .............................................................. 339

Combining Speculative Execution and Conditional Resource Sharing to Efficiently Schedule Conditional Behaviors Apostolos A. Kountouris and Christophe Wolinski .................................................................. 343

Fast Instruction Cache Simulation Strategies in a Hardware/Software Co- Design Environment Marcello Lajolo, Lucian0 lavagno and Alberto Sangiovanni-Vincentelli ............................... 347

Session 12C BehavioraVFPGA

Chair: H. Xue Co-chair: P. Leong

A Multi-Level FPGA Synthesis Method Supporting HDL Debugging for Emulation-Based Designs Wen-Jong Fang, Peng-Cheng Kao and Allen C.-H. Wu .......................................................... 351

A Genetic Algorithm Based Approach for Multi-Objective Data-Flow Graph Optimization Birger Landwehr ...................................................................................................................... 355

Fast Boolean Matching under Permutation Using Representative Debatosh Debnath and Tsutomu Sasao ................................................................................... 359

FSM Modeling of Synchronous VHDL Design for Symbolic Model Checking Jinsong Bei, Hongxing Li, Jinian Bian, Hongxi Xue and Xianlong Hong .............................. 363

Conference Author Index ................................................................................................................ 367

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